authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2020-12-09 14:19:58-05:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2020-12-09 12:21:28-07:00
logb124d04e6a42457882652276d3988d0a8747a3b0
tree54ef5246976b6b7e127ae62bdbcfd32bc73ae938
parenta7eea0813fcec1d381ca17ded13595c6172ad396

Merge pull request #7366 from LemonBoy/fix-7346

Some compiler-rt fixes

5 files changed, 103 insertions(+), 94 deletions(-)

doc/langref.html.in+1-1
......@@ -7988,7 +7988,7 @@ test "@wasmMemoryGrow" {
79887988 {#header_close#}
79897989
79907990 {#header_open|@setEvalBranchQuota#}
7991 <pre>{#syntax#}@setEvalBranchQuota(new_quota: usize){#endsyntax#}</pre>
7991 <pre>{#syntax#}@setEvalBranchQuota(new_quota: u32){#endsyntax#}</pre>
79927992 <p>
79937993 Changes the maximum number of backwards branches that compile-time code
79947994 execution can use before giving up and making a compile error.
lib/std/math/exp2.zig+3-3
......@@ -95,7 +95,7 @@ fn exp2_32(x: f32) f32 {
9595 uf -= redux;
9696
9797 const z: f64 = x - uf;
98 var r: f64 = exp2ft[i_0];
98 var r: f64 = exp2ft[@intCast(usize, i_0)];
9999 const t: f64 = r * z;
100100 r = r + t * (P1 + z * P2) + t * (z * z) * (P3 + z * P4);
101101 return @floatCast(f32, r * uk);
......@@ -418,8 +418,8 @@ fn exp2_64(x: f64) f64 {
418418
419419 // r = exp2(y) = exp2t[i_0] * p(z - eps[i])
420420 var z = x - uf;
421 const t = exp2dt[2 * i_0];
422 z -= exp2dt[2 * i_0 + 1];
421 const t = exp2dt[@intCast(usize, 2 * i_0)];
422 z -= exp2dt[@intCast(usize, 2 * i_0 + 1)];
423423 const r = t + t * z * (P1 + z * (P2 + z * (P3 + z * (P4 + z * P5))));
424424
425425 return math.scalbn(r, ik);
lib/std/special/compiler_rt/atomics.zig+89-76
......@@ -8,6 +8,31 @@ const builtin = std.builtin;
88
99const linkage: builtin.GlobalLinkage = if (builtin.is_test) .Internal else .Weak;
1010
11// This parameter is true iff the target architecture supports the bare minimum
12// to implement the atomic load/store intrinsics.
13// Some architectures support atomic load/stores but no CAS, but we ignore this
14// detail to keep the export logic clean and because we need some kind of CAS to
15// implement the spinlocks.
16const supports_atomic_ops = switch (builtin.arch) {
17 .msp430, .avr => false,
18 .arm, .armeb, .thumb, .thumbeb =>
19 // The ARM v6m ISA has no ldrex/strex and so it's impossible to do CAS
20 // operations (unless we're targeting Linux, the kernel provides a way to
21 // perform CAS operations).
22 // XXX: The Linux code path is not implemented yet.
23 !std.Target.arm.featureSetHas(std.Target.current.cpu.features, .has_v6m),
24 else => true,
25};
26
27// The size (in bytes) of the biggest object that the architecture can
28// load/store atomically.
29// Objects bigger than this threshold require the use of a lock.
30const largest_atomic_size = switch (builtin.arch) {
31 // XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b
32 // and set this parameter accordingly.
33 else => @sizeOf(usize),
34};
35
1136const cache_line_size = 64;
1237
1338const SpinlockTable = struct {
......@@ -94,40 +119,18 @@ fn __atomic_compare_exchange(
94119}
95120
96121comptime {
97 @export(__atomic_load, .{ .name = "__atomic_load", .linkage = linkage });
98 @export(__atomic_store, .{ .name = "__atomic_store", .linkage = linkage });
99 @export(__atomic_exchange, .{ .name = "__atomic_exchange", .linkage = linkage });
100 @export(__atomic_compare_exchange, .{ .name = "__atomic_compare_exchange", .linkage = linkage });
122 if (supports_atomic_ops) {
123 @export(__atomic_load, .{ .name = "__atomic_load", .linkage = linkage });
124 @export(__atomic_store, .{ .name = "__atomic_store", .linkage = linkage });
125 @export(__atomic_exchange, .{ .name = "__atomic_exchange", .linkage = linkage });
126 @export(__atomic_compare_exchange, .{ .name = "__atomic_compare_exchange", .linkage = linkage });
127 }
101128}
102129
103130// Specialized versions of the GCC atomic builtin functions.
104131// LLVM emits those iff the object size is known and the pointers are correctly
105132// aligned.
106133
107// The size (in bytes) of the biggest object that the architecture can
108// load/store atomically.
109// Objects bigger than this threshold require the use of a lock.
110const largest_atomic_size = switch (builtin.arch) {
111 .x86_64 => 16,
112 else => @sizeOf(usize),
113};
114
115// The size (in bytes) of the biggest object that the architecture can perform
116// an atomic CAS operation with.
117// Objects bigger than this threshold require the use of a lock.
118const largest_atomic_cas_size = switch (builtin.arch) {
119 .arm, .armeb, .thumb, .thumbeb =>
120 // The ARM v6m ISA has no ldrex/strex and so it's impossible to do CAS
121 // operations unless we're targeting Linux or the user provides the missing
122 // builtin functions.
123 if (std.Target.arm.featureSetHas(std.Target.current.cpu.features, .has_v6m) and
124 std.Target.current.os.tag != .linux)
125 0
126 else
127 @sizeOf(usize),
128 else => @sizeOf(usize),
129};
130
131134fn atomicLoadFn(comptime T: type) fn (*T, i32) callconv(.C) T {
132135 return struct {
133136 fn atomic_load_N(src: *T, model: i32) callconv(.C) T {
......@@ -143,10 +146,12 @@ fn atomicLoadFn(comptime T: type) fn (*T, i32) callconv(.C) T {
143146}
144147
145148comptime {
146 @export(atomicLoadFn(u8), .{ .name = "__atomic_load_1", .linkage = linkage });
147 @export(atomicLoadFn(u16), .{ .name = "__atomic_load_2", .linkage = linkage });
148 @export(atomicLoadFn(u32), .{ .name = "__atomic_load_4", .linkage = linkage });
149 @export(atomicLoadFn(u64), .{ .name = "__atomic_load_8", .linkage = linkage });
149 if (supports_atomic_ops) {
150 @export(atomicLoadFn(u8), .{ .name = "__atomic_load_1", .linkage = linkage });
151 @export(atomicLoadFn(u16), .{ .name = "__atomic_load_2", .linkage = linkage });
152 @export(atomicLoadFn(u32), .{ .name = "__atomic_load_4", .linkage = linkage });
153 @export(atomicLoadFn(u64), .{ .name = "__atomic_load_8", .linkage = linkage });
154 }
150155}
151156
152157fn atomicStoreFn(comptime T: type) fn (*T, T, i32) callconv(.C) void {
......@@ -164,16 +169,18 @@ fn atomicStoreFn(comptime T: type) fn (*T, T, i32) callconv(.C) void {
164169}
165170
166171comptime {
167 @export(atomicStoreFn(u8), .{ .name = "__atomic_store_1", .linkage = linkage });
168 @export(atomicStoreFn(u16), .{ .name = "__atomic_store_2", .linkage = linkage });
169 @export(atomicStoreFn(u32), .{ .name = "__atomic_store_4", .linkage = linkage });
170 @export(atomicStoreFn(u64), .{ .name = "__atomic_store_8", .linkage = linkage });
172 if (supports_atomic_ops) {
173 @export(atomicStoreFn(u8), .{ .name = "__atomic_store_1", .linkage = linkage });
174 @export(atomicStoreFn(u16), .{ .name = "__atomic_store_2", .linkage = linkage });
175 @export(atomicStoreFn(u32), .{ .name = "__atomic_store_4", .linkage = linkage });
176 @export(atomicStoreFn(u64), .{ .name = "__atomic_store_8", .linkage = linkage });
177 }
171178}
172179
173180fn atomicExchangeFn(comptime T: type) fn (*T, T, i32) callconv(.C) T {
174181 return struct {
175182 fn atomic_exchange_N(ptr: *T, val: T, model: i32) callconv(.C) T {
176 if (@sizeOf(T) > largest_atomic_cas_size) {
183 if (@sizeOf(T) > largest_atomic_size) {
177184 var sl = spinlocks.get(@ptrToInt(ptr));
178185 defer sl.release();
179186 const value = ptr.*;
......@@ -187,16 +194,18 @@ fn atomicExchangeFn(comptime T: type) fn (*T, T, i32) callconv(.C) T {
187194}
188195
189196comptime {
190 @export(atomicExchangeFn(u8), .{ .name = "__atomic_exchange_1", .linkage = linkage });
191 @export(atomicExchangeFn(u16), .{ .name = "__atomic_exchange_2", .linkage = linkage });
192 @export(atomicExchangeFn(u32), .{ .name = "__atomic_exchange_4", .linkage = linkage });
193 @export(atomicExchangeFn(u64), .{ .name = "__atomic_exchange_8", .linkage = linkage });
197 if (supports_atomic_ops) {
198 @export(atomicExchangeFn(u8), .{ .name = "__atomic_exchange_1", .linkage = linkage });
199 @export(atomicExchangeFn(u16), .{ .name = "__atomic_exchange_2", .linkage = linkage });
200 @export(atomicExchangeFn(u32), .{ .name = "__atomic_exchange_4", .linkage = linkage });
201 @export(atomicExchangeFn(u64), .{ .name = "__atomic_exchange_8", .linkage = linkage });
202 }
194203}
195204
196205fn atomicCompareExchangeFn(comptime T: type) fn (*T, *T, T, i32, i32) callconv(.C) i32 {
197206 return struct {
198207 fn atomic_compare_exchange_N(ptr: *T, expected: *T, desired: T, success: i32, failure: i32) callconv(.C) i32 {
199 if (@sizeOf(T) > largest_atomic_cas_size) {
208 if (@sizeOf(T) > largest_atomic_size) {
200209 var sl = spinlocks.get(@ptrToInt(ptr));
201210 defer sl.release();
202211 const value = ptr.*;
......@@ -218,16 +227,18 @@ fn atomicCompareExchangeFn(comptime T: type) fn (*T, *T, T, i32, i32) callconv(.
218227}
219228
220229comptime {
221 @export(atomicCompareExchangeFn(u8), .{ .name = "__atomic_compare_exchange_1", .linkage = linkage });
222 @export(atomicCompareExchangeFn(u16), .{ .name = "__atomic_compare_exchange_2", .linkage = linkage });
223 @export(atomicCompareExchangeFn(u32), .{ .name = "__atomic_compare_exchange_4", .linkage = linkage });
224 @export(atomicCompareExchangeFn(u64), .{ .name = "__atomic_compare_exchange_8", .linkage = linkage });
230 if (supports_atomic_ops) {
231 @export(atomicCompareExchangeFn(u8), .{ .name = "__atomic_compare_exchange_1", .linkage = linkage });
232 @export(atomicCompareExchangeFn(u16), .{ .name = "__atomic_compare_exchange_2", .linkage = linkage });
233 @export(atomicCompareExchangeFn(u32), .{ .name = "__atomic_compare_exchange_4", .linkage = linkage });
234 @export(atomicCompareExchangeFn(u64), .{ .name = "__atomic_compare_exchange_8", .linkage = linkage });
235 }
225236}
226237
227238fn fetchFn(comptime T: type, comptime op: builtin.AtomicRmwOp) fn (*T, T, i32) callconv(.C) T {
228239 return struct {
229240 pub fn fetch_op_N(ptr: *T, val: T, model: i32) callconv(.C) T {
230 if (@sizeOf(T) > largest_atomic_cas_size) {
241 if (@sizeOf(T) > largest_atomic_size) {
231242 var sl = spinlocks.get(@ptrToInt(ptr));
232243 defer sl.release();
233244
......@@ -251,33 +262,35 @@ fn fetchFn(comptime T: type, comptime op: builtin.AtomicRmwOp) fn (*T, T, i32) c
251262}
252263
253264comptime {
254 @export(fetchFn(u8, .Add), .{ .name = "__atomic_fetch_add_1", .linkage = linkage });
255 @export(fetchFn(u16, .Add), .{ .name = "__atomic_fetch_add_2", .linkage = linkage });
256 @export(fetchFn(u32, .Add), .{ .name = "__atomic_fetch_add_4", .linkage = linkage });
257 @export(fetchFn(u64, .Add), .{ .name = "__atomic_fetch_add_8", .linkage = linkage });
258
259 @export(fetchFn(u8, .Sub), .{ .name = "__atomic_fetch_sub_1", .linkage = linkage });
260 @export(fetchFn(u16, .Sub), .{ .name = "__atomic_fetch_sub_2", .linkage = linkage });
261 @export(fetchFn(u32, .Sub), .{ .name = "__atomic_fetch_sub_4", .linkage = linkage });
262 @export(fetchFn(u64, .Sub), .{ .name = "__atomic_fetch_sub_8", .linkage = linkage });
263
264 @export(fetchFn(u8, .And), .{ .name = "__atomic_fetch_and_1", .linkage = linkage });
265 @export(fetchFn(u16, .And), .{ .name = "__atomic_fetch_and_2", .linkage = linkage });
266 @export(fetchFn(u32, .And), .{ .name = "__atomic_fetch_and_4", .linkage = linkage });
267 @export(fetchFn(u64, .And), .{ .name = "__atomic_fetch_and_8", .linkage = linkage });
268
269 @export(fetchFn(u8, .Or), .{ .name = "__atomic_fetch_or_1", .linkage = linkage });
270 @export(fetchFn(u16, .Or), .{ .name = "__atomic_fetch_or_2", .linkage = linkage });
271 @export(fetchFn(u32, .Or), .{ .name = "__atomic_fetch_or_4", .linkage = linkage });
272 @export(fetchFn(u64, .Or), .{ .name = "__atomic_fetch_or_8", .linkage = linkage });
273
274 @export(fetchFn(u8, .Xor), .{ .name = "__atomic_fetch_xor_1", .linkage = linkage });
275 @export(fetchFn(u16, .Xor), .{ .name = "__atomic_fetch_xor_2", .linkage = linkage });
276 @export(fetchFn(u32, .Xor), .{ .name = "__atomic_fetch_xor_4", .linkage = linkage });
277 @export(fetchFn(u64, .Xor), .{ .name = "__atomic_fetch_xor_8", .linkage = linkage });
278
279 @export(fetchFn(u8, .Nand), .{ .name = "__atomic_fetch_nand_1", .linkage = linkage });
280 @export(fetchFn(u16, .Nand), .{ .name = "__atomic_fetch_nand_2", .linkage = linkage });
281 @export(fetchFn(u32, .Nand), .{ .name = "__atomic_fetch_nand_4", .linkage = linkage });
282 @export(fetchFn(u64, .Nand), .{ .name = "__atomic_fetch_nand_8", .linkage = linkage });
265 if (supports_atomic_ops) {
266 @export(fetchFn(u8, .Add), .{ .name = "__atomic_fetch_add_1", .linkage = linkage });
267 @export(fetchFn(u16, .Add), .{ .name = "__atomic_fetch_add_2", .linkage = linkage });
268 @export(fetchFn(u32, .Add), .{ .name = "__atomic_fetch_add_4", .linkage = linkage });
269 @export(fetchFn(u64, .Add), .{ .name = "__atomic_fetch_add_8", .linkage = linkage });
270
271 @export(fetchFn(u8, .Sub), .{ .name = "__atomic_fetch_sub_1", .linkage = linkage });
272 @export(fetchFn(u16, .Sub), .{ .name = "__atomic_fetch_sub_2", .linkage = linkage });
273 @export(fetchFn(u32, .Sub), .{ .name = "__atomic_fetch_sub_4", .linkage = linkage });
274 @export(fetchFn(u64, .Sub), .{ .name = "__atomic_fetch_sub_8", .linkage = linkage });
275
276 @export(fetchFn(u8, .And), .{ .name = "__atomic_fetch_and_1", .linkage = linkage });
277 @export(fetchFn(u16, .And), .{ .name = "__atomic_fetch_and_2", .linkage = linkage });
278 @export(fetchFn(u32, .And), .{ .name = "__atomic_fetch_and_4", .linkage = linkage });
279 @export(fetchFn(u64, .And), .{ .name = "__atomic_fetch_and_8", .linkage = linkage });
280
281 @export(fetchFn(u8, .Or), .{ .name = "__atomic_fetch_or_1", .linkage = linkage });
282 @export(fetchFn(u16, .Or), .{ .name = "__atomic_fetch_or_2", .linkage = linkage });
283 @export(fetchFn(u32, .Or), .{ .name = "__atomic_fetch_or_4", .linkage = linkage });
284 @export(fetchFn(u64, .Or), .{ .name = "__atomic_fetch_or_8", .linkage = linkage });
285
286 @export(fetchFn(u8, .Xor), .{ .name = "__atomic_fetch_xor_1", .linkage = linkage });
287 @export(fetchFn(u16, .Xor), .{ .name = "__atomic_fetch_xor_2", .linkage = linkage });
288 @export(fetchFn(u32, .Xor), .{ .name = "__atomic_fetch_xor_4", .linkage = linkage });
289 @export(fetchFn(u64, .Xor), .{ .name = "__atomic_fetch_xor_8", .linkage = linkage });
290
291 @export(fetchFn(u8, .Nand), .{ .name = "__atomic_fetch_nand_1", .linkage = linkage });
292 @export(fetchFn(u16, .Nand), .{ .name = "__atomic_fetch_nand_2", .linkage = linkage });
293 @export(fetchFn(u32, .Nand), .{ .name = "__atomic_fetch_nand_4", .linkage = linkage });
294 @export(fetchFn(u64, .Nand), .{ .name = "__atomic_fetch_nand_8", .linkage = linkage });
295 }
283296}
lib/std/special/compiler_rt/clzsi2.zig+9-13
......@@ -3,7 +3,8 @@
33// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
44// The MIT license requires this copyright notice to be included in all copies
55// and substantial portions of the software.
6const builtin = @import("builtin");
6const std = @import("std");
7const builtin = std.builtin;
78
89fn __clzsi2_generic(a: i32) callconv(.C) i32 {
910 @setRuntimeSafety(builtin.is_test);
......@@ -25,8 +26,6 @@ fn __clzsi2_generic(a: i32) callconv(.C) i32 {
2526}
2627
2728fn __clzsi2_thumb1() callconv(.Naked) void {
28 @setRuntimeSafety(builtin.is_test);
29
3029 // Similar to the generic version with the last two rounds replaced by a LUT
3130 asm volatile (
3231 \\ movs r1, #32
......@@ -59,8 +58,6 @@ fn __clzsi2_thumb1() callconv(.Naked) void {
5958}
6059
6160fn __clzsi2_arm32() callconv(.Naked) void {
62 @setRuntimeSafety(builtin.is_test);
63
6461 asm volatile (
6562 \\ // Assumption: n != 0
6663 \\ // r0: n
......@@ -107,14 +104,13 @@ fn __clzsi2_arm32() callconv(.Naked) void {
107104 unreachable;
108105}
109106
110pub const __clzsi2 = blk: {
111 if (builtin.arch.isARM()) {
112 break :blk __clzsi2_arm32;
113 } else if (builtin.arch.isThumb()) {
114 break :blk __clzsi2_thumb1;
115 } else {
116 break :blk __clzsi2_generic;
117 }
107pub const __clzsi2 = switch (std.Target.current.cpu.arch) {
108 .arm, .armeb => if (std.Target.arm.featureSetHas(std.Target.current.cpu.features, .noarm))
109 __clzsi2_thumb1
110 else
111 __clzsi2_arm32,
112 .thumb, .thumbeb => __clzsi2_thumb1,
113 else => __clzsi2_generic,
118114};
119115
120116test "test clzsi2" {
src/stage1/ir.cpp+1-1
......@@ -26697,7 +26697,7 @@ static IrInstGen *ir_analyze_instruction_set_eval_branch_quota(IrAnalyze *ira,
2669726697 IrInstSrcSetEvalBranchQuota *instruction)
2669826698{
2669926699 uint64_t new_quota;
26700 if (!ir_resolve_usize(ira, instruction->new_quota->child, &new_quota))
26700 if (!ir_resolve_unsigned(ira, instruction->new_quota->child, ira->codegen->builtin_types.entry_u32, &new_quota))
2670126701 return ira->codegen->invalid_inst_gen;
2670226702
2670326703 if (new_quota > *ira->new_irb.exec->backward_branch_quota) {