authorgravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2021-12-29 20:55:05+01:00
committergravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2021-12-29 22:06:38+01:00
logb7e223597395358dc63cf88c92ace5eaa455cf89
tree51108f8b375f49eac43b24bbc839dfefdada4f3e
parent08ea1a2eab9472389d57ddbd97e307fcb096a992

stage2: lower 1-byte and 2-byte values saved to stack

* fix handling of `ah`, `bh`, `ch`, and `dh` registers (which are actually used as aliases to `dil`, etc. registers). Currenly, we treat them as aliases only meaning when we encounter `ah` we make sure to set the REX.W to promote the instruction to 64bits and use `dil` register instead - otherwise we might have mismatch between registers used in different parts of the codegen. In the future, we can and should use `ah`, etc. as upper 8bit halves of 16bit registers `ax`, etc. * fix bug in `airCmp` where `.cmp` MIR instruction shouldn't force type `Bool` but let the type of the original type propagate downwards - we need this to make an informed choice of the target register size and hence choose the right encoding down the line. * implement lowering of 1-byte and 2-byte values to stack and add matching stage2 tests for x86_64 codegen

3 files changed, 103 insertions(+), 33 deletions(-)

src/arch/x86_64/CodeGen.zig+16-15
......@@ -1642,11 +1642,11 @@ fn genBinMathOpMir(
16421642 });
16431643 },
16441644 .immediate => |imm| {
1645 // TODO I am not quite sure why we need to set the size of the register here...
1645 const abi_size = dst_ty.abiSize(self.target.*);
16461646 _ = try self.addInst(.{
16471647 .tag = mir_tag,
16481648 .ops = (Mir.Ops{
1649 .reg1 = dst_reg.to32(),
1649 .reg1 = registerAlias(dst_reg, @intCast(u32, abi_size)),
16501650 }).encode(),
16511651 .data = .{ .imm = @intCast(i32, imm) },
16521652 });
......@@ -1751,13 +1751,14 @@ fn genIMulOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: MCValue) !
17511751 });
17521752 },
17531753 .immediate => |imm| {
1754 // TODO take into account the type's ABI size when selecting the register alias
17541755 // register, immediate
17551756 if (imm <= math.maxInt(i32)) {
17561757 _ = try self.addInst(.{
17571758 .tag = .imul_complex,
17581759 .ops = (Mir.Ops{
1759 .reg1 = dst_reg,
1760 .reg2 = dst_reg,
1760 .reg1 = dst_reg.to32(),
1761 .reg2 = dst_reg.to32(),
17611762 .flags = 0b10,
17621763 }).encode(),
17631764 .data = .{ .imm = @intCast(i32, imm) },
......@@ -2147,7 +2148,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
21472148 // This instruction supports only signed 32-bit immediates at most.
21482149 const src_mcv = try self.limitImmediateType(bin_op.rhs, i32);
21492150
2150 try self.genBinMathOpMir(.cmp, Type.initTag(.bool), dst_mcv, src_mcv);
2151 try self.genBinMathOpMir(.cmp, ty, dst_mcv, src_mcv);
21512152 break :result switch (ty.isSignedInt()) {
21522153 true => MCValue{ .compare_flags_signed = op },
21532154 false => MCValue{ .compare_flags_unsigned = op },
......@@ -2792,16 +2793,10 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
27922793 return self.fail("TODO implement set stack variable with large stack offset", .{});
27932794 }
27942795 switch (abi_size) {
2795 1 => {
2796 return self.fail("TODO implement set abi_size=1 stack variable with immediate", .{});
2797 },
2798 2 => {
2799 return self.fail("TODO implement set abi_size=2 stack variable with immediate", .{});
2800 },
2801 4 => {
2796 1, 2, 4 => {
28022797 // We have a positive stack offset value but we want a twos complement negative
28032798 // offset from rbp, which is at the top of the stack frame.
2804 // mov DWORD PTR [rbp+offset], immediate
2799 // mov [rbp+offset], immediate
28052800 const payload = try self.addExtra(Mir.ImmPair{
28062801 .dest_off = -@intCast(i32, adj_off),
28072802 .operand = @bitCast(i32, @intCast(u32, x_big)),
......@@ -2810,7 +2805,12 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
28102805 .tag = .mov_mem_imm,
28112806 .ops = (Mir.Ops{
28122807 .reg1 = .rbp,
2813 .flags = 0b10,
2808 .flags = switch (abi_size) {
2809 1 => 0b00,
2810 2 => 0b01,
2811 4 => 0b10,
2812 else => unreachable,
2813 },
28142814 }).encode(),
28152815 .data = .{ .payload = payload },
28162816 });
......@@ -2954,11 +2954,12 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
29542954 return;
29552955 }
29562956 if (x <= math.maxInt(i32)) {
2957 const abi_size = ty.abiSize(self.target.*);
29572958 // Next best case: if we set the lower four bytes, the upper four will be zeroed.
29582959 _ = try self.addInst(.{
29592960 .tag = .mov,
29602961 .ops = (Mir.Ops{
2961 .reg1 = reg.to32(),
2962 .reg1 = registerAlias(reg, @intCast(u32, abi_size)),
29622963 }).encode(),
29632964 .data = .{ .imm = @intCast(i32, x) },
29642965 });
src/arch/x86_64/Emit.zig+29-18
......@@ -468,7 +468,15 @@ fn mirArithMemImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
468468 ) catch |err| emit.failWithLoweringError(err);
469469}
470470
471fn immOpSize(imm: i64) u8 {
471inline fn setRexWRegister(reg: Register) bool {
472 if (reg.size() == 64) return true;
473 return switch (reg) {
474 .ah, .bh, .ch, .dh => true,
475 else => false,
476 };
477}
478
479inline fn immOpSize(imm: i64) u8 {
472480 blk: {
473481 _ = math.cast(i8, imm) catch break :blk;
474482 return 8;
......@@ -1370,7 +1378,10 @@ fn lowerToMEnc(tag: Tag, reg_or_mem: RegisterOrMemory, code: *std.ArrayList(u8))
13701378 encoder.opcode_1byte(0x66);
13711379 }
13721380 encoder.rex(.{
1373 .w = tag.isSetCC(),
1381 .w = switch (reg) {
1382 .ah, .bh, .ch, .dh => true,
1383 else => false,
1384 },
13741385 .b = reg.isExtended(),
13751386 });
13761387 opc.encode(encoder);
......@@ -1389,7 +1400,7 @@ fn lowerToMEnc(tag: Tag, reg_or_mem: RegisterOrMemory, code: *std.ArrayList(u8))
13891400 return error.OperandSizeMismatch;
13901401 }
13911402 encoder.rex(.{
1392 .w = tag.isSetCC(),
1403 .w = false,
13931404 .b = reg.isExtended(),
13941405 });
13951406 opc.encode(encoder);
......@@ -1455,7 +1466,7 @@ fn lowerToTdFdEnc(tag: Tag, reg: Register, moffs: i64, code: *std.ArrayList(u8),
14551466 encoder.opcode_1byte(0x66);
14561467 }
14571468 encoder.rex(.{
1458 .w = reg.size() == 64,
1469 .w = setRexWRegister(reg),
14591470 });
14601471 opc.encode(encoder);
14611472 switch (reg.size()) {
......@@ -1488,7 +1499,7 @@ fn lowerToOiEnc(tag: Tag, reg: Register, imm: i64, code: *std.ArrayList(u8)) Low
14881499 encoder.opcode_1byte(0x66);
14891500 }
14901501 encoder.rex(.{
1491 .w = reg.size() == 64,
1502 .w = setRexWRegister(reg),
14921503 .b = reg.isExtended(),
14931504 });
14941505 opc.encodeWithReg(encoder, reg);
......@@ -1525,7 +1536,7 @@ fn lowerToMiEnc(tag: Tag, reg_or_mem: RegisterOrMemory, imm: i32, code: *std.Arr
15251536 encoder.opcode_1byte(0x66);
15261537 }
15271538 encoder.rex(.{
1528 .w = dst_reg.size() == 64,
1539 .w = setRexWRegister(dst_reg),
15291540 .b = dst_reg.isExtended(),
15301541 });
15311542 opc.encode(encoder);
......@@ -1623,7 +1634,7 @@ fn lowerToRmEnc(
16231634 }
16241635 const encoder = try Encoder.init(code, 3);
16251636 encoder.rex(.{
1626 .w = reg.size() == 64,
1637 .w = setRexWRegister(reg) or setRexWRegister(src_reg),
16271638 .r = reg.isExtended(),
16281639 .b = src_reg.isExtended(),
16291640 });
......@@ -1645,7 +1656,7 @@ fn lowerToRmEnc(
16451656 return error.OperandSizeMismatch;
16461657 }
16471658 encoder.rex(.{
1648 .w = reg.size() == 64,
1659 .w = setRexWRegister(reg),
16491660 .r = reg.isExtended(),
16501661 .b = src_reg.isExtended(),
16511662 });
......@@ -1676,7 +1687,7 @@ fn lowerToRmEnc(
16761687 }
16771688 } else {
16781689 encoder.rex(.{
1679 .w = reg.size() == 64,
1690 .w = setRexWRegister(reg),
16801691 .r = reg.isExtended(),
16811692 });
16821693 opc.encode(encoder);
......@@ -1706,7 +1717,7 @@ fn lowerToMrEnc(
17061717 }
17071718 const encoder = try Encoder.init(code, 3);
17081719 encoder.rex(.{
1709 .w = dst_reg.size() == 64,
1720 .w = setRexWRegister(dst_reg) or setRexWRegister(reg),
17101721 .r = reg.isExtended(),
17111722 .b = dst_reg.isExtended(),
17121723 });
......@@ -1726,7 +1737,7 @@ fn lowerToMrEnc(
17261737 return error.OperandSizeMismatch;
17271738 }
17281739 encoder.rex(.{
1729 .w = dst_mem.ptr_size == .qword_ptr,
1740 .w = dst_mem.ptr_size == .qword_ptr or setRexWRegister(reg),
17301741 .r = reg.isExtended(),
17311742 .b = dst_reg.isExtended(),
17321743 });
......@@ -1757,7 +1768,7 @@ fn lowerToMrEnc(
17571768 }
17581769 } else {
17591770 encoder.rex(.{
1760 .w = dst_mem.ptr_size == .qword_ptr,
1771 .w = dst_mem.ptr_size == .qword_ptr or setRexWRegister(reg),
17611772 .r = reg.isExtended(),
17621773 });
17631774 opc.encode(encoder);
......@@ -1794,7 +1805,7 @@ fn lowerToRmiEnc(
17941805 return error.OperandSizeMismatch;
17951806 }
17961807 encoder.rex(.{
1797 .w = reg.size() == 64,
1808 .w = setRexWRegister(reg) or setRexWRegister(src_reg),
17981809 .r = reg.isExtended(),
17991810 .b = src_reg.isExtended(),
18001811 });
......@@ -1812,7 +1823,7 @@ fn lowerToRmiEnc(
18121823 return error.OperandSizeMismatch;
18131824 }
18141825 encoder.rex(.{
1815 .w = reg.size() == 64,
1826 .w = setRexWRegister(reg),
18161827 .r = reg.isExtended(),
18171828 .b = src_reg.isExtended(),
18181829 });
......@@ -1843,7 +1854,7 @@ fn lowerToRmiEnc(
18431854 }
18441855 } else {
18451856 encoder.rex(.{
1846 .w = reg.size() == 64,
1857 .w = setRexWRegister(reg),
18471858 .r = reg.isExtended(),
18481859 });
18491860 opc.encode(encoder);
......@@ -2089,7 +2100,7 @@ test "lower M encoding" {
20892100 try lowerToMEnc(.jmp_near, RegisterOrMemory.mem(null, 0x10, .qword_ptr), code.buffer());
20902101 try expectEqualHexStrings("\xFF\x24\x25\x10\x00\x00\x00", code.emitted(), "jmp qword ptr [ds:0x10]");
20912102 try lowerToMEnc(.seta, RegisterOrMemory.reg(.r11b), code.buffer());
2092 try expectEqualHexStrings("\x49\x0F\x97\xC3", code.emitted(), "seta r11b");
2103 try expectEqualHexStrings("\x41\x0F\x97\xC3", code.emitted(), "seta r11b");
20932104}
20942105
20952106test "lower O encoding" {
......@@ -2111,9 +2122,9 @@ test "lower RMI encoding" {
21112122 "imul rax, qword ptr [rbp - 8], 0x10",
21122123 );
21132124 try lowerToRmiEnc(.imul, .eax, RegisterOrMemory.mem(.rbp, -4, .dword_ptr), 0x10, code.buffer());
2114 try expectEqualHexStrings("\x69\x45\xFC\x10\x00\x00\x00", code.emitted(), "imul ax, [rbp - 2], 0x10");
2125 try expectEqualHexStrings("\x69\x45\xFC\x10\x00\x00\x00", code.emitted(), "imul eax, dword ptr [rbp - 4], 0x10");
21152126 try lowerToRmiEnc(.imul, .ax, RegisterOrMemory.mem(.rbp, -2, .word_ptr), 0x10, code.buffer());
2116 try expectEqualHexStrings("\x66\x69\x45\xFE\x10\x00", code.emitted(), "imul eax, [rbp - 4], 0x10");
2127 try expectEqualHexStrings("\x66\x69\x45\xFE\x10\x00", code.emitted(), "imul ax, word ptr [rbp - 2], 0x10");
21172128 try lowerToRmiEnc(.imul, .r12, RegisterOrMemory.reg(.r12), 0x10, code.buffer());
21182129 try expectEqualHexStrings("\x4D\x69\xE4\x10\x00\x00\x00", code.emitted(), "imul r12, r12, 0x10");
21192130 try lowerToRmiEnc(.imul, .r12w, RegisterOrMemory.reg(.r12w), 0x10, code.buffer());
test/stage2/x86_64.zig+58
......@@ -1604,6 +1604,64 @@ pub fn addCases(ctx: *TestContext) !void {
16041604 ":2:28: error: cannot set address space of local variable 'foo'",
16051605 });
16061606 }
1607
1608 {
1609 var case = ctx.exe("saving vars of different ABI size to stack", target);
1610
1611 case.addCompareOutput(
1612 \\pub fn main() void {
1613 \\ assert(callMe(2) == 24);
1614 \\}
1615 \\
1616 \\fn callMe(a: u8) u8 {
1617 \\ var b: u8 = a + 10;
1618 \\ const c = 2 * b;
1619 \\ return c;
1620 \\}
1621 \\
1622 \\pub fn assert(ok: bool) void {
1623 \\ if (!ok) unreachable; // assertion failure
1624 \\}
1625 ,
1626 "",
1627 );
1628
1629 case.addCompareOutput(
1630 \\pub fn main() void {
1631 \\ assert(callMe(2) == 24);
1632 \\}
1633 \\
1634 \\fn callMe(a: u16) u16 {
1635 \\ var b: u16 = a + 10;
1636 \\ const c = 2 * b;
1637 \\ return c;
1638 \\}
1639 \\
1640 \\pub fn assert(ok: bool) void {
1641 \\ if (!ok) unreachable; // assertion failure
1642 \\}
1643 ,
1644 "",
1645 );
1646
1647 case.addCompareOutput(
1648 \\pub fn main() void {
1649 \\ assert(callMe(2) == 24);
1650 \\}
1651 \\
1652 \\fn callMe(a: u32) u32 {
1653 \\ var b: u32 = a + 10;
1654 \\ const c = 2 * b;
1655 \\ return c;
1656 \\}
1657 \\
1658 \\pub fn assert(ok: bool) void {
1659 \\ if (!ok) unreachable; // assertion failure
1660 \\}
1661 ,
1662 "",
1663 );
1664 }
16071665 }
16081666}
16091667