From c825b567b26c475e058e074e5d22af006854fab6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= <alex@alexrp.com>
Date: Sun, 21 Jul 2024 14:04:52 +0200
Subject: [PATCH] std.Target: Remove the `r600` arch tag.

These are quite old GPUs, and it is unlikely that Zig will ever be able to
target them.

See: https://en.wikipedia.org/wiki/Radeon_HD_2000_series
---
 lib/compiler/aro/aro/target.zig | 3 ---
 lib/std/Target.zig              | 8 --------
 src/Type.zig                    | 1 -
 src/Zcu.zig                     | 1 -
 src/codegen/llvm.zig            | 3 ---
 src/target.zig                  | 1 -
 test/behavior/align.zig         | 1 -
 test/llvm_targets.zig           | 1 -
 8 files changed, 19 deletions(-)

diff --git a/lib/compiler/aro/aro/target.zig b/lib/compiler/aro/aro/target.zig
index 83ee4f886097a3dc0fa5f7d10206f39dafb9a087..7c6c879683e21ae48a4a25ab22cc2e2c7cc7f6d6 100644
--- a/lib/compiler/aro/aro/target.zig
+++ b/lib/compiler/aro/aro/target.zig
@@ -470,7 +470,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
         .mipsel,
         .powerpc,
         .powerpcle,
-        .r600,
         .riscv32,
         .sparc,
         .sparcel,
@@ -527,7 +526,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
         .lanai,
         .m68k,
         .msp430,
-        .r600,
         .shave,
         .sparcel,
         .spu_2,
@@ -616,7 +614,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
         .powerpcle => "powerpcle",
         .powerpc64 => "powerpc64",
         .powerpc64le => "powerpc64le",
-        .r600 => "r600",
         .amdgcn => "amdgcn",
         .riscv32 => "riscv32",
         .riscv64 => "riscv64",
diff --git a/lib/std/Target.zig b/lib/std/Target.zig
index aa800114b550f7ec5622afca2c8589829179dc40..d281bcf6dbeebaed0ba76aba24de2a2c680cb7e0 100644
--- a/lib/std/Target.zig
+++ b/lib/std/Target.zig
@@ -994,7 +994,6 @@ pub const Cpu = struct {
         powerpcle,
         powerpc64,
         powerpc64le,
-        r600,
         amdgcn,
         riscv32,
         riscv64,
@@ -1146,7 +1145,6 @@ pub const Cpu = struct {
                 .mips => .MIPS,
                 .mipsel => .MIPS_RS3_LE,
                 .powerpc, .powerpcle => .PPC,
-                .r600 => .NONE,
                 .riscv32 => .RISCV,
                 .sparc => .SPARC,
                 .sparcel => .SPARC,
@@ -1208,7 +1206,6 @@ pub const Cpu = struct {
                 .mips => .Unknown,
                 .mipsel => .Unknown,
                 .powerpc, .powerpcle => .POWERPC,
-                .r600 => .Unknown,
                 .riscv32 => .RISCV32,
                 .sparc => .Unknown,
                 .sparcel => .Unknown,
@@ -1282,7 +1279,6 @@ pub const Cpu = struct {
                 .tcele,
                 .powerpcle,
                 .powerpc64le,
-                .r600,
                 .riscv32,
                 .riscv64,
                 .x86,
@@ -1772,7 +1768,6 @@ pub const DynamicLinker = struct {
                 .hexagon,
                 .m68k,
                 .msp430,
-                .r600,
                 .amdgcn,
                 .tce,
                 .tcele,
@@ -1874,7 +1869,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
         .mipsel,
         .powerpc,
         .powerpcle,
-        .r600,
         .riscv32,
         .sparcel,
         .tce,
@@ -2436,7 +2430,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
             .lanai,
             .nvptx,
             .nvptx64,
-            .r600,
             .s390x,
             .spir64,
             .spirv64,
@@ -2560,7 +2553,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
             .lanai,
             .nvptx,
             .nvptx64,
-            .r600,
             .s390x,
             .spir64,
             .spirv64,
diff --git a/src/Type.zig b/src/Type.zig
index 80dd3bed40a677066f1fa3d654d491c4e503d3dc..bfe9a94d33b7c793010b4c053f13614ec6e44b84 100644
--- a/src/Type.zig
+++ b/src/Type.zig
@@ -1599,7 +1599,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
         .mipsel,
         .powerpc,
         .powerpcle,
-        .r600,
         .amdgcn,
         .riscv32,
         .sparc,
diff --git a/src/Zcu.zig b/src/Zcu.zig
index 741ca825fd3dd7e6e32a56624c3a4034afc21516..dbece763ec27461ad159886d220700e232cc74ab 100644
--- a/src/Zcu.zig
+++ b/src/Zcu.zig
@@ -3246,7 +3246,6 @@ pub fn atomicPtrAlignment(
         .nvptx,
         .powerpc,
         .powerpcle,
-        .r600,
         .riscv32,
         .sparc,
         .sparcel,
diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig
index 2835d627f70889a753a248fddac64fc7dda75e3d..b56ca01484b96c9249e5f377f70c224ded922c47 100644
--- a/src/codegen/llvm.zig
+++ b/src/codegen/llvm.zig
@@ -65,7 +65,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
         .powerpcle => "powerpcle",
         .powerpc64 => "powerpc64",
         .powerpc64le => "powerpc64le",
-        .r600 => "r600",
         .amdgcn => "amdgcn",
         .riscv32 => "riscv32",
         .riscv64 => "riscv64",
@@ -287,7 +286,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
         .powerpcle => .ppcle,
         .powerpc64 => .ppc64,
         .powerpc64le => .ppc64le,
-        .r600 => .r600,
         .amdgcn => .amdgcn,
         .riscv32 => .riscv32,
         .riscv64 => .riscv64,
@@ -12090,7 +12088,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
         // LLVM backends that have no initialization functions.
         .tce,
         .tcele,
-        .r600,
         .amdil,
         .amdil64,
         .hsail,
diff --git a/src/target.zig b/src/target.zig
index c69ac6d0bf7117c4bcb1e964ebbb170dea55fa1c..19b8320cd829c0e6962134385c703da232b68f3a 100644
--- a/src/target.zig
+++ b/src/target.zig
@@ -135,7 +135,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
         .powerpcle,
         .powerpc64,
         .powerpc64le,
-        .r600,
         .amdgcn,
         .riscv32,
         .riscv64,
diff --git a/test/behavior/align.zig b/test/behavior/align.zig
index 1ede6ad433f0ef934e6369c956882a934679ba6e..0b588ce091d8aa476a0a20856bfd4d635721af7b 100644
--- a/test/behavior/align.zig
+++ b/test/behavior/align.zig
@@ -94,7 +94,6 @@ test "alignment and size of structs with 128-bit fields" {
         .mipsel,
         .powerpc,
         .powerpcle,
-        .r600,
         .amdgcn,
         .riscv32,
         .sparc,
diff --git a/test/llvm_targets.zig b/test/llvm_targets.zig
index 31b355a862e73c44bc7459233d1524f9faeff132..07db7ad7826ff158df5306f5663f81aa96e62e52 100644
--- a/test/llvm_targets.zig
+++ b/test/llvm_targets.zig
@@ -76,7 +76,6 @@ const targets = [_]std.Target.Query{
     .{ .cpu_arch = .powerpc64le, .os_tag = .linux, .abi = .gnu },
     .{ .cpu_arch = .powerpc64le, .os_tag = .linux, .abi = .musl },
     .{ .cpu_arch = .powerpc64le, .os_tag = .linux, .abi = .none },
-    //.{ .cpu_arch = .r600, .os_tag = .mesa3d, .abi = .none },
     .{ .cpu_arch = .riscv32, .os_tag = .freestanding, .abi = .none },
     .{ .cpu_arch = .riscv32, .os_tag = .linux, .abi = .none },
     .{ .cpu_arch = .riscv64, .os_tag = .freestanding, .abi = .none },
-- 
2.54.0