authorgravatar for mlugg@mlugg.co.ukMatthew Lugg <mlugg@mlugg.co.uk> 2026-06-23 09:59:02+01:00
committergravatar for mlugg@mlugg.co.ukMatthew Lugg <mlugg@mlugg.co.uk> 2026-06-24 10:20:57+01:00
logcbef1f5a013c664979e68d3ea8fa3ba378e3f0f6
tree171014c35405b12edeb213fd0f4155ac2aac780c
parent664c1d0198c1d5027167461cc0013faf5fc53347
signaturelock-open Commit is signed but in an unrecognized format.

c_abi: disable some tests on ARM

This is an existing bug which has started causing a miscompilation in this branch due to changes to our emitted LLVM IR. Tracked by https://codeberg.org/ziglang/zig/issues/35899.

1 files changed, 2 insertions(+), 0 deletions(-)

test/c_abi/main.zig+2
...@@ -14501,6 +14501,7 @@ test "@Vector(4, f64)" {...@@ -14501,6 +14501,7 @@ test "@Vector(4, f64)" {
14501 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;14501 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
14502 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;14502 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
14503 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;14503 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
14504 if (builtin.cpu.arch.isArm()) return error.SkipZigTest; // https://codeberg.org/ziglang/zig/issues/35899
1450414505
14505 const v = c_ret_vector_4_f64();14506 const v = c_ret_vector_4_f64();
14506 try expect(v[0] == 33);14507 try expect(v[0] == 33);
...@@ -14570,6 +14571,7 @@ test "@Vector(8, f64)" {...@@ -14570,6 +14571,7 @@ test "@Vector(8, f64)" {
14570 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;14571 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
14571 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;14572 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
14572 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;14573 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
14574 if (builtin.cpu.arch.isArm()) return error.SkipZigTest; // https://codeberg.org/ziglang/zig/issues/35899
1457314575
14574 const v = c_ret_vector_8_f64();14576 const v = c_ret_vector_8_f64();
14575 try expect(v[0] == 81);14577 try expect(v[0] == 81);