| ... | @@ -1685,6 +1685,7 @@ fn airLoad(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -1685,6 +1685,7 @@ fn airLoad(self: *Self, inst: Air.Inst.Index) !void { |
| 1685 | | 1685 | |
| 1686 | fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type) InnerError!void { | 1686 | fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type) InnerError!void { |
| 1687 | _ = ptr_ty; | 1687 | _ = ptr_ty; |
| | 1688 | const abi_size = value_ty.abiSize(self.target.*); |
| 1688 | switch (ptr) { | 1689 | switch (ptr) { |
| 1689 | .none => unreachable, | 1690 | .none => unreachable, |
| 1690 | .undef => unreachable, | 1691 | .undef => unreachable, |
| ... | @@ -1705,6 +1706,9 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type | ... | @@ -1705,6 +1706,9 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type |
| 1705 | return self.fail("TODO implement storing to MCValue.embedded_in_code", .{}); | 1706 | return self.fail("TODO implement storing to MCValue.embedded_in_code", .{}); |
| 1706 | }, | 1707 | }, |
| 1707 | .register => |reg| { | 1708 | .register => |reg| { |
| | 1709 | self.register_manager.freezeRegs(&.{reg}); |
| | 1710 | defer self.register_manager.unfreezeRegs(&.{reg}); |
| | 1711 | |
| 1708 | switch (value) { | 1712 | switch (value) { |
| 1709 | .none => unreachable, | 1713 | .none => unreachable, |
| 1710 | .undef => unreachable, | 1714 | .undef => unreachable, |
| ... | @@ -1713,7 +1717,6 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type | ... | @@ -1713,7 +1717,6 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type |
| 1713 | .compare_flags_unsigned => unreachable, | 1717 | .compare_flags_unsigned => unreachable, |
| 1714 | .compare_flags_signed => unreachable, | 1718 | .compare_flags_signed => unreachable, |
| 1715 | .immediate => |imm| { | 1719 | .immediate => |imm| { |
| 1716 | const abi_size = value_ty.abiSize(self.target.*); | | |
| 1717 | switch (abi_size) { | 1720 | switch (abi_size) { |
| 1718 | 1, 2, 4 => { | 1721 | 1, 2, 4 => { |
| 1719 | // TODO this is wasteful! | 1722 | // TODO this is wasteful! |
| ... | @@ -1736,13 +1739,30 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type | ... | @@ -1736,13 +1739,30 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type |
| 1736 | .data = .{ .payload = payload }, | 1739 | .data = .{ .payload = payload }, |
| 1737 | }); | 1740 | }); |
| 1738 | }, | 1741 | }, |
| | 1742 | 8 => { |
| | 1743 | // TODO: optimization: if the imm is only using the lower |
| | 1744 | // 4 bytes and can be sign extended we can use a normal mov |
| | 1745 | // with indirect addressing (mov [reg64], imm32). |
| | 1746 | |
| | 1747 | // movabs does not support indirect register addressing |
| | 1748 | // so we need an extra register and an extra mov. |
| | 1749 | const tmp_reg = try self.copyToTmpRegister(value_ty, value); |
| | 1750 | _ = try self.addInst(.{ |
| | 1751 | .tag = .mov, |
| | 1752 | .ops = (Mir.Ops{ |
| | 1753 | .reg1 = reg.to64(), |
| | 1754 | .reg2 = tmp_reg.to64(), |
| | 1755 | .flags = 0b10, |
| | 1756 | }).encode(), |
| | 1757 | .data = .{ .imm = 0 }, |
| | 1758 | }); |
| | 1759 | }, |
| 1739 | else => { | 1760 | else => { |
| 1740 | return self.fail("TODO implement set pointee with immediate of ABI size {d}", .{abi_size}); | 1761 | return self.fail("TODO implement set pointee with immediate of ABI size {d}", .{abi_size}); |
| 1741 | }, | 1762 | }, |
| 1742 | } | 1763 | } |
| 1743 | }, | 1764 | }, |
| 1744 | .register => |src_reg| { | 1765 | .register => |src_reg| { |
| 1745 | const abi_size = value_ty.abiSize(self.target.*); | | |
| 1746 | _ = try self.addInst(.{ | 1766 | _ = try self.addInst(.{ |
| 1747 | .tag = .mov, | 1767 | .tag = .mov, |
| 1748 | .ops = (Mir.Ops{ | 1768 | .ops = (Mir.Ops{ |
| ... | @@ -1758,8 +1778,80 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type | ... | @@ -1758,8 +1778,80 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type |
| 1758 | }, | 1778 | }, |
| 1759 | } | 1779 | } |
| 1760 | }, | 1780 | }, |
| 1761 | .memory => { | 1781 | .memory => |addr| { |
| 1762 | return self.fail("TODO implement storing to MCValue.memory", .{}); | 1782 | if (self.bin_file.options.pie) { |
| | 1783 | return self.fail("TODO implement storing to memory when targeting PIE", .{}); |
| | 1784 | } |
| | 1785 | |
| | 1786 | // TODO: in case the address fits in an imm32 we can use [ds:imm32] |
| | 1787 | // instead of wasting an instruction copying the address to a register |
| | 1788 | |
| | 1789 | if (value.isRegister()) self.register_manager.freezeRegs(&.{value.register}); |
| | 1790 | defer if (value.isRegister()) self.register_manager.unfreezeRegs(&.{value.register}); |
| | 1791 | |
| | 1792 | const addr_reg = try self.copyToTmpRegister(ptr_ty, .{ .immediate = addr }); |
| | 1793 | // to get the actual address of the value we want to modify we have to go through the GOT |
| | 1794 | // mov reg, [reg] |
| | 1795 | _ = try self.addInst(.{ |
| | 1796 | .tag = .mov, |
| | 1797 | .ops = (Mir.Ops{ |
| | 1798 | .reg1 = addr_reg.to64(), |
| | 1799 | .reg2 = addr_reg.to64(), |
| | 1800 | .flags = 0b01, |
| | 1801 | }).encode(), |
| | 1802 | .data = .{ .imm = 0 }, |
| | 1803 | }); |
| | 1804 | |
| | 1805 | switch (value) { |
| | 1806 | .immediate => |imm| { |
| | 1807 | if (abi_size > 8) { |
| | 1808 | return self.fail("TODO saving imm to memory for abi_size {}", .{abi_size}); |
| | 1809 | } |
| | 1810 | |
| | 1811 | const payload = try self.addExtra(Mir.ImmPair{ |
| | 1812 | .dest_off = 0, |
| | 1813 | .operand = @intCast(u32, imm), |
| | 1814 | }); |
| | 1815 | const flags: u2 = switch (abi_size) { |
| | 1816 | 1 => 0b00, |
| | 1817 | 2 => 0b01, |
| | 1818 | 4 => 0b10, |
| | 1819 | 8 => 0b11, |
| | 1820 | else => unreachable, |
| | 1821 | }; |
| | 1822 | if (flags == 0b11) { |
| | 1823 | const top_bits: u32 = @intCast(u32, imm >> 32); |
| | 1824 | const can_extend = if (value_ty.isUnsignedInt()) |
| | 1825 | (top_bits == 0) and (imm & 0x8000_0000) == 0 |
| | 1826 | else |
| | 1827 | top_bits == 0xffff_ffff; |
| | 1828 | |
| | 1829 | if (!can_extend) { |
| | 1830 | return self.fail("TODO imm64 would get incorrectly sign extended", .{}); |
| | 1831 | } |
| | 1832 | } |
| | 1833 | _ = try self.addInst(.{ |
| | 1834 | .tag = .mov_mem_imm, |
| | 1835 | .ops = (Mir.Ops{ |
| | 1836 | .reg1 = addr_reg.to64(), |
| | 1837 | .flags = flags, |
| | 1838 | }).encode(), |
| | 1839 | .data = .{ .payload = payload }, |
| | 1840 | }); |
| | 1841 | }, |
| | 1842 | .register => |reg| { |
| | 1843 | _ = try self.addInst(.{ |
| | 1844 | .tag = .mov, |
| | 1845 | .ops = (Mir.Ops{ |
| | 1846 | .reg1 = addr_reg.to64(), |
| | 1847 | .reg2 = reg, |
| | 1848 | .flags = 0b10, |
| | 1849 | }).encode(), |
| | 1850 | .data = .{ .imm = 0 }, |
| | 1851 | }); |
| | 1852 | }, |
| | 1853 | else => return self.fail("TODO implement storing {} to MCValue.memory", .{value}), |
| | 1854 | } |
| 1763 | }, | 1855 | }, |
| 1764 | .stack_offset => { | 1856 | .stack_offset => { |
| 1765 | return self.fail("TODO implement storing to MCValue.stack_offset", .{}); | 1857 | return self.fail("TODO implement storing to MCValue.stack_offset", .{}); |