Commit d17f492017c77d5d52d2fbd65eaa5c1e08b24161 | zig

author	Andrew Kelley <andrew@ziglang.org> 2021-07-16 23:06:59-07:00
committer	Andrew Kelley <andrew@ziglang.org> 2021-07-20 12:19:16-07:00
log	d17f492017c77d5d52d2fbd65eaa5c1e08b24161
tree	4b5f2ecc801b19f546982a0bc159e2db979f90b2
parent	2438f61f1c37aefa16852130370df44b3fabf785

stage2: miscellaneous fixes for the branch

 * Breaking language change: inline assembly must use string literal
   syntax. This is in preparation for inline assembly improvements that
   involve more integration with the Zig language. This means we cannot
   rely on text substitution.
 * Liveness: properly handle inline assembly and function calls with
   more than 3 operands.
   - More than 35 operands is not yet supported. This is a low priority
     to implement.
   - This required implementation in codegen.zig as well.
 * Liveness: fix bug causing incorrect tomb bits.
 * Sema: enable switch expressions that are evaluated at compile-time.
   - Runtime switch instructions still need to be reworked in this
     branch. There was a TODO left here (by me) with a suggestion to do
     some bigger changes as part of the AIR memory reworking. Now that
     time has come and I plan to honor the suggestion in a future commit
     before merging this branch.
 * AIR printing: fix missing ')' on alive instructions.

We're back to "hello world" working for the x86_64 backend.

8 files changed, 441 insertions(+), 232 deletions(-)

lib
- std
  - Thread.zig
  - atomic.zig
  - atomic
    Atomic.zig
src

lib/std/Thread.zig+43-21

...	...	@@ -505,8 +505,8 @@ const LinuxThreadImpl = struct {
505	505	/// Ported over from musl libc's pthread detached implementation:
506	506	/// https://github.com/ifduyue/musl/search?q=__unmapself
507	507	fn freeAndExit(self: *ThreadCompletion) noreturn {
508		const unmap_and_exit: []const u8 = switch (target.cpu.arch) {
509		.i386 => (
	508	switch (target.cpu.arch) {
	509	.i386 => asm volatile (
510	510	\\ movl $91, %%eax
511	511	\\ movl %[ptr], %%ebx
512	512	\\ movl %[len], %%ecx
...	...	@@ -514,8 +514,12 @@ const LinuxThreadImpl = struct {
514	514	\\ movl $1, %%eax
515	515	\\ movl $0, %%ebx
516	516	\\ int $128
	517	:
	518	: [ptr] "r" (@ptrToInt(self.mapped.ptr)),
	519	[len] "r" (self.mapped.len)
	520	: "memory"
517	521	),
518		.x86_64 => (
	522	.x86_64 => asm volatile (
519	523	\\ movq $11, %%rax
520	524	\\ movq %[ptr], %%rbx
521	525	\\ movq %[len], %%rcx
...	...	@@ -523,8 +527,12 @@ const LinuxThreadImpl = struct {
523	527	\\ movq $60, %%rax
524	528	\\ movq $1, %%rdi
525	529	\\ syscall
	530	:
	531	: [ptr] "r" (@ptrToInt(self.mapped.ptr)),
	532	[len] "r" (self.mapped.len)
	533	: "memory"
526	534	),
527		.arm, .armeb, .thumb, .thumbeb => (
	535	.arm, .armeb, .thumb, .thumbeb => asm volatile (
528	536	\\ mov r7, #91
529	537	\\ mov r0, %[ptr]
530	538	\\ mov r1, %[len]
...	...	@@ -532,8 +540,12 @@ const LinuxThreadImpl = struct {
532	540	\\ mov r7, #1
533	541	\\ mov r0, #0
534	542	\\ svc 0
	543	:
	544	: [ptr] "r" (@ptrToInt(self.mapped.ptr)),
	545	[len] "r" (self.mapped.len)
	546	: "memory"
535	547	),
536		.aarch64, .aarch64_be, .aarch64_32 => (
	548	.aarch64, .aarch64_be, .aarch64_32 => asm volatile (
537	549	\\ mov x8, #215
538	550	\\ mov x0, %[ptr]
539	551	\\ mov x1, %[len]
...	...	@@ -541,8 +553,12 @@ const LinuxThreadImpl = struct {
541	553	\\ mov x8, #93
542	554	\\ mov x0, #0
543	555	\\ svc 0
	556	:
	557	: [ptr] "r" (@ptrToInt(self.mapped.ptr)),
	558	[len] "r" (self.mapped.len)
	559	: "memory"
544	560	),
545		.mips, .mipsel => (
	561	.mips, .mipsel => asm volatile (
546	562	\\ move $sp, $25
547	563	\\ li $2, 4091
548	564	\\ move $4, %[ptr]
...	...	@@ -551,8 +567,12 @@ const LinuxThreadImpl = struct {
551	567	\\ li $2, 4001
552	568	\\ li $4, 0
553	569	\\ syscall
	570	:
	571	: [ptr] "r" (@ptrToInt(self.mapped.ptr)),
	572	[len] "r" (self.mapped.len)
	573	: "memory"
554	574	),
555		.mips64, .mips64el => (
	575	.mips64, .mips64el => asm volatile (
556	576	\\ li $2, 4091
557	577	\\ move $4, %[ptr]
558	578	\\ move $5, %[len]
...	...	@@ -560,8 +580,12 @@ const LinuxThreadImpl = struct {
560	580	\\ li $2, 4001
561	581	\\ li $4, 0
562	582	\\ syscall
	583	:
	584	: [ptr] "r" (@ptrToInt(self.mapped.ptr)),
	585	[len] "r" (self.mapped.len)
	586	: "memory"
563	587	),
564		.powerpc, .powerpcle, .powerpc64, .powerpc64le => (
	588	.powerpc, .powerpcle, .powerpc64, .powerpc64le => asm volatile (
565	589	\\ li 0, 91
566	590	\\ mr %[ptr], 3
567	591	\\ mr %[len], 4
...	...	@@ -570,8 +594,12 @@ const LinuxThreadImpl = struct {
570	594	\\ li 3, 0
571	595	\\ sc
572	596	\\ blr
	597	:
	598	: [ptr] "r" (@ptrToInt(self.mapped.ptr)),
	599	[len] "r" (self.mapped.len)
	600	: "memory"
573	601	),
574		.riscv64 => (
	602	.riscv64 => asm volatile (
575	603	\\ li a7, 215
576	604	\\ mv a0, %[ptr]
577	605	\\ mv a1, %[len]
...	...	@@ -579,19 +607,13 @@ const LinuxThreadImpl = struct {
579	607	\\ li a7, 93
580	608	\\ mv a0, zero
581	609	\\ ecall
	610	:
	611	: [ptr] "r" (@ptrToInt(self.mapped.ptr)),
	612	[len] "r" (self.mapped.len)
	613	: "memory"
582	614	),
583		else => \|cpu_arch\| {
584		@compileLog("Unsupported linux arch ", cpu_arch);
585		},
586		};
587
588		asm volatile (unmap_and_exit
589		:
590		: [ptr] "r" (@ptrToInt(self.mapped.ptr)),
591		[len] "r" (self.mapped.len)
592		: "memory"
593		);
594
	615	else => \|cpu_arch\| @compileError("Unsupported linux arch: " ++ @tagName(cpu_arch)),
	616	}
595	617	unreachable;
596	618	}
597	619	};

lib/std/atomic.zig+21-17

...	...	@@ -46,34 +46,38 @@ test "fence/compilerFence" {
46	46
47	47	/// Signals to the processor that the caller is inside a busy-wait spin-loop.
48	48	pub inline fn spinLoopHint() void {
49		const hint_instruction = switch (target.cpu.arch) {
50		// No-op instruction that can hint to save (or share with a hardware-thread) pipelining/power resources
	49	switch (target.cpu.arch) {
	50	// No-op instruction that can hint to save (or share with a hardware-thread)
	51	// pipelining/power resources
51	52	// https://software.intel.com/content/www/us/en/develop/articles/benefitting-power-and-performance-sleep-loops.html
52		.i386, .x86_64 => "pause",
	53	.i386, .x86_64 => asm volatile ("pause" ::: "memory"),
53	54
54	55	// No-op instruction that serves as a hardware-thread resource yield hint.
55	56	// https://stackoverflow.com/a/7588941
56		.powerpc64, .powerpc64le => "or 27, 27, 27",
	57	.powerpc64, .powerpc64le => asm volatile ("or 27, 27, 27" ::: "memory"),
57	58
58		// `isb` appears more reliable for releasing execution resources than `yield` on common aarch64 CPUs.
	59	// `isb` appears more reliable for releasing execution resources than `yield`
	60	// on common aarch64 CPUs.
59	61	// https://bugs.java.com/bugdatabase/view_bug.do?bug_id=8258604
60	62	// https://bugs.mysql.com/bug.php?id=100664
61		.aarch64, .aarch64_be, .aarch64_32 => "isb",
	63	.aarch64, .aarch64_be, .aarch64_32 => asm volatile ("isb" ::: "memory"),
62	64
63	65	// `yield` was introduced in v6k but is also available on v6m.
64	66	// https://www.keil.com/support/man/docs/armasm/armasm_dom1361289926796.htm
65		.arm, .armeb, .thumb, .thumbeb => blk: {
66		const can_yield = comptime std.Target.arm.featureSetHasAny(target.cpu.features, .{ .has_v6k, .has_v6m });
67		const instruction = if (can_yield) "yield" else "";
68		break :blk instruction;
	67	.arm, .armeb, .thumb, .thumbeb => {
	68	const can_yield = comptime std.Target.arm.featureSetHasAny(target.cpu.features, .{
	69	.has_v6k, .has_v6m,
	70	});
	71	if (can_yield) {
	72	asm volatile ("yield" ::: "memory");
	73	} else {
	74	asm volatile ("" ::: "memory");
	75	}
69	76	},
70
71		else => "",
72		};
73
74		// Memory barrier to prevent the compiler from optimizing away the spin-loop
75		// even if no hint_instruction was provided.
76		asm volatile (hint_instruction ::: "memory");
	77	// Memory barrier to prevent the compiler from optimizing away the spin-loop
	78	// even if no hint_instruction was provided.
	79	else => asm volatile ("" ::: "memory"),
	80	}
77	81	}
78	82
79	83	test "spinLoopHint" {

lib/std/atomic/Atomic.zig+70-18

...	...	@@ -178,26 +178,78 @@ pub fn Atomic(comptime T: type) type {
178	178	) u1 {
179	179	// x86 supports dedicated bitwise instructions
180	180	if (comptime target.cpu.arch.isX86() and @sizeOf(T) >= 2 and @sizeOf(T) <= 8) {
181		const instruction = switch (op) {
182		.Set => "lock bts",
183		.Reset => "lock btr",
184		.Toggle => "lock btc",
185		};
186
187		const suffix = switch (@sizeOf(T)) {
188		2 => "w",
189		4 => "l",
190		8 => "q",
	181	const old_bit: u8 = switch (@sizeOf(T)) {
	182	2 => switch (op) {
	183	.Set => asm volatile ("lock btsw %[bit], %[ptr]"
	184	// LLVM doesn't support u1 flag register return values
	185	: [result] "={@ccc}" (-> u8)
	186	: [ptr] "*p" (&self.value),
	187	[bit] "X" (@as(T, bit))
	188	: "cc", "memory"
	189	),
	190	.Reset => asm volatile ("lock btrw %[bit], %[ptr]"
	191	// LLVM doesn't support u1 flag register return values
	192	: [result] "={@ccc}" (-> u8)
	193	: [ptr] "*p" (&self.value),
	194	[bit] "X" (@as(T, bit))
	195	: "cc", "memory"
	196	),
	197	.Toggle => asm volatile ("lock btcw %[bit], %[ptr]"
	198	// LLVM doesn't support u1 flag register return values
	199	: [result] "={@ccc}" (-> u8)
	200	: [ptr] "*p" (&self.value),
	201	[bit] "X" (@as(T, bit))
	202	: "cc", "memory"
	203	),
	204	},
	205	4 => switch (op) {
	206	.Set => asm volatile ("lock btsl %[bit], %[ptr]"
	207	// LLVM doesn't support u1 flag register return values
	208	: [result] "={@ccc}" (-> u8)
	209	: [ptr] "*p" (&self.value),
	210	[bit] "X" (@as(T, bit))
	211	: "cc", "memory"
	212	),
	213	.Reset => asm volatile ("lock btrl %[bit], %[ptr]"
	214	// LLVM doesn't support u1 flag register return values
	215	: [result] "={@ccc}" (-> u8)
	216	: [ptr] "*p" (&self.value),
	217	[bit] "X" (@as(T, bit))
	218	: "cc", "memory"
	219	),
	220	.Toggle => asm volatile ("lock btcl %[bit], %[ptr]"
	221	// LLVM doesn't support u1 flag register return values
	222	: [result] "={@ccc}" (-> u8)
	223	: [ptr] "*p" (&self.value),
	224	[bit] "X" (@as(T, bit))
	225	: "cc", "memory"
	226	),
	227	},
	228	8 => switch (op) {
	229	.Set => asm volatile ("lock btsq %[bit], %[ptr]"
	230	// LLVM doesn't support u1 flag register return values
	231	: [result] "={@ccc}" (-> u8)
	232	: [ptr] "*p" (&self.value),
	233	[bit] "X" (@as(T, bit))
	234	: "cc", "memory"
	235	),
	236	.Reset => asm volatile ("lock btrq %[bit], %[ptr]"
	237	// LLVM doesn't support u1 flag register return values
	238	: [result] "={@ccc}" (-> u8)
	239	: [ptr] "*p" (&self.value),
	240	[bit] "X" (@as(T, bit))
	241	: "cc", "memory"
	242	),
	243	.Toggle => asm volatile ("lock btcq %[bit], %[ptr]"
	244	// LLVM doesn't support u1 flag register return values
	245	: [result] "={@ccc}" (-> u8)
	246	: [ptr] "*p" (&self.value),
	247	[bit] "X" (@as(T, bit))
	248	: "cc", "memory"
	249	),
	250	},
191	251	else => @compileError("Invalid atomic type " ++ @typeName(T)),
192	252	};
193
194		const old_bit = asm volatile (instruction ++ suffix ++ " %[bit], %[ptr]"
195		: [result] "={@ccc}" (-> u8) // LLVM doesn't support u1 flag register return values
196		: [ptr] "*p" (&self.value),
197		[bit] "X" (@as(T, bit))
198		: "cc", "memory"
199		);
200
201	253	return @intCast(u1, old_bit);
202	254	}
203	255

src/AstGen.zig+1-1

...	...	@@ -6601,7 +6601,7 @@ fn asmExpr(
6601	6601	const asm_source = switch (node_tags[full.ast.template]) {
6602	6602	.string_literal => try astgen.strLitAsString(main_tokens[full.ast.template]),
6603	6603	.multiline_string_literal => try astgen.strLitNodeAsString(full.ast.template),
6604		else => return astgen.failNode(node, "assembly code must use string literal syntax", .{}),
	6604	else => return astgen.failNode(full.ast.template, "assembly code must use string literal syntax", .{}),
6605	6605	};
6606	6606
6607	6607	// See https://github.com/ziglang/zig/issues/215 and related issues discussing

src/Liveness.zig+69-3

...	...	@@ -24,6 +24,11 @@ const Log2Int = std.math.Log2Int;
24	24	tomb_bits: []usize,
25	25	/// Sparse table of specially handled instructions. The value is an index into the `extra`
26	26	/// array. The meaning of the data depends on the AIR tag.
	27	/// * `cond_br` - points to a `CondBr` in `extra` at this index.
	28	/// * `switch_br` - points to a `SwitchBr` in `extra` at this index.
	29	/// * `asm`, `call` - the value is a set of bits which are the extra tomb bits of operands.
	30	/// The main tomb bits are still used and the extra ones are starting with the lsb of the
	31	/// value here.
27	32	special: std.AutoHashMapUnmanaged(Air.Inst.Index, u32),
28	33	/// Auxilliary data. The way this data is interpreted is determined contextually.
29	34	extra: []const u32,
...	...	@@ -67,6 +72,8 @@ pub fn analyze(gpa: *Allocator, air: Air, zir: Zir) Allocator.Error!Liveness {
67	72	defer a.extra.deinit(gpa);
68	73	defer a.table.deinit(gpa);
69	74
	75	std.mem.set(usize, a.tomb_bits, 0);
	76
70	77	const main_body = air.getMainBody();
71	78	try a.table.ensureTotalCapacity(gpa, @intCast(u32, main_body.len));
72	79	try analyzeWithContext(&a, null, main_body);
...	...	@@ -103,7 +110,7 @@ pub fn clearOperandDeath(l: Liveness, inst: Air.Inst.Index, operand: OperandInt)
103	110	const usize_index = (inst * bpi) / @bitSizeOf(usize);
104	111	const mask = @as(usize, 1) <<
105	112	@intCast(Log2Int(usize), (inst % (@bitSizeOf(usize) / bpi)) * bpi + operand);
106		l.tomb_bits[usize_index] \|= mask;
	113	l.tomb_bits[usize_index] &= ~mask;
107	114	}
108	115
109	116	/// Higher level API.
...	...	@@ -298,7 +305,17 @@ fn analyzeInst(
298	305	std.mem.copy(Air.Inst.Ref, buf[1..], args);
299	306	return trackOperands(a, new_set, inst, main_tomb, buf);
300	307	}
301		@panic("TODO: liveness analysis for function call with greater than 2 args");
	308	var extra_tombs: ExtraTombs = .{
	309	.analysis = a,
	310	.new_set = new_set,
	311	.inst = inst,
	312	.main_tomb = main_tomb,
	313	};
	314	try extra_tombs.feed(callee);
	315	for (args) \|arg\| {
	316	try extra_tombs.feed(arg);
	317	}
	318	return extra_tombs.finish();
302	319	},
303	320	.struct_field_ptr => {
304	321	const extra = a.air.extraData(Air.StructField, inst_datas[inst].ty_pl.payload).data;
...	...	@@ -317,7 +334,19 @@ fn analyzeInst(
317	334	std.mem.copy(Air.Inst.Ref, buf[outputs.len..], args);
318	335	return trackOperands(a, new_set, inst, main_tomb, buf);
319	336	}
320		@panic("TODO: liveness analysis for asm with greater than 3 args");
	337	var extra_tombs: ExtraTombs = .{
	338	.analysis = a,
	339	.new_set = new_set,
	340	.inst = inst,
	341	.main_tomb = main_tomb,
	342	};
	343	for (outputs) \|output\| {
	344	try extra_tombs.feed(output);
	345	}
	346	for (args) \|arg\| {
	347	try extra_tombs.feed(arg);
	348	}
	349	return extra_tombs.finish();
321	350	},
322	351	.block => {
323	352	const extra = a.air.extraData(Air.Block, inst_datas[inst].ty_pl.payload);
...	...	@@ -531,3 +560,40 @@ fn trackOperands(
531	560	}
532	561	a.storeTombBits(inst, tomb_bits);
533	562	}
	563
	564	const ExtraTombs = struct {
	565	analysis: *Analysis,
	566	new_set: ?*std.AutoHashMapUnmanaged(Air.Inst.Index, void),
	567	inst: Air.Inst.Index,
	568	main_tomb: bool,
	569	bit_index: usize = 0,
	570	tomb_bits: Bpi = 0,
	571	big_tomb_bits: u32 = 0,
	572
	573	fn feed(et: *ExtraTombs, op_ref: Air.Inst.Ref) !void {
	574	const this_bit_index = et.bit_index;
	575	assert(this_bit_index < 32); // TODO mechanism for when there are greater than 32 operands
	576	et.bit_index += 1;
	577	const gpa = et.analysis.gpa;
	578	const op_int = @enumToInt(op_ref);
	579	if (op_int < Air.Inst.Ref.typed_value_map.len) return;
	580	const op_index: Air.Inst.Index = op_int - @intCast(u32, Air.Inst.Ref.typed_value_map.len);
	581	const prev = try et.analysis.table.fetchPut(gpa, op_index, {});
	582	if (prev == null) {
	583	// Death.
	584	if (et.new_set) \|ns\| try ns.putNoClobber(gpa, op_index, {});
	585	if (this_bit_index < bpi - 1) {
	586	et.tomb_bits \|= @as(Bpi, 1) << @intCast(OperandInt, this_bit_index);
	587	} else {
	588	const big_bit_index = this_bit_index - (bpi - 1);
	589	et.big_tomb_bits \|= @as(u32, 1) << @intCast(u5, big_bit_index);
	590	}
	591	}
	592	}
	593
	594	fn finish(et: *ExtraTombs) !void {
	595	et.tomb_bits \|= @as(Bpi, @boolToInt(et.main_tomb)) << (bpi - 1);
	596	et.analysis.storeTombBits(et.inst, et.tomb_bits);
	597	try et.analysis.special.put(et.analysis.gpa, et.inst, et.big_tomb_bits);
	598	}
	599	};

src/Sema.zig+167-166

...	...	@@ -258,24 +258,24 @@ pub fn analyzeBody(
258	258	.slice_sentinel => try sema.zirSliceSentinel(block, inst),
259	259	.slice_start => try sema.zirSliceStart(block, inst),
260	260	.str => try sema.zirStr(block, inst),
261		//.switch_block => try sema.zirSwitchBlock(block, inst, false, .none),
262		//.switch_block_multi => try sema.zirSwitchBlockMulti(block, inst, false, .none),
263		//.switch_block_else => try sema.zirSwitchBlock(block, inst, false, .@"else"),
264		//.switch_block_else_multi => try sema.zirSwitchBlockMulti(block, inst, false, .@"else"),
265		//.switch_block_under => try sema.zirSwitchBlock(block, inst, false, .under),
266		//.switch_block_under_multi => try sema.zirSwitchBlockMulti(block, inst, false, .under),
267		//.switch_block_ref => try sema.zirSwitchBlock(block, inst, true, .none),
268		//.switch_block_ref_multi => try sema.zirSwitchBlockMulti(block, inst, true, .none),
269		//.switch_block_ref_else => try sema.zirSwitchBlock(block, inst, true, .@"else"),
270		//.switch_block_ref_else_multi => try sema.zirSwitchBlockMulti(block, inst, true, .@"else"),
271		//.switch_block_ref_under => try sema.zirSwitchBlock(block, inst, true, .under),
272		//.switch_block_ref_under_multi => try sema.zirSwitchBlockMulti(block, inst, true, .under),
273		//.switch_capture => try sema.zirSwitchCapture(block, inst, false, false),
274		//.switch_capture_ref => try sema.zirSwitchCapture(block, inst, false, true),
275		//.switch_capture_multi => try sema.zirSwitchCapture(block, inst, true, false),
276		//.switch_capture_multi_ref => try sema.zirSwitchCapture(block, inst, true, true),
277		//.switch_capture_else => try sema.zirSwitchCaptureElse(block, inst, false),
278		//.switch_capture_else_ref => try sema.zirSwitchCaptureElse(block, inst, true),
	261	.switch_block => try sema.zirSwitchBlock(block, inst, false, .none),
	262	.switch_block_multi => try sema.zirSwitchBlockMulti(block, inst, false, .none),
	263	.switch_block_else => try sema.zirSwitchBlock(block, inst, false, .@"else"),
	264	.switch_block_else_multi => try sema.zirSwitchBlockMulti(block, inst, false, .@"else"),
	265	.switch_block_under => try sema.zirSwitchBlock(block, inst, false, .under),
	266	.switch_block_under_multi => try sema.zirSwitchBlockMulti(block, inst, false, .under),
	267	.switch_block_ref => try sema.zirSwitchBlock(block, inst, true, .none),
	268	.switch_block_ref_multi => try sema.zirSwitchBlockMulti(block, inst, true, .none),
	269	.switch_block_ref_else => try sema.zirSwitchBlock(block, inst, true, .@"else"),
	270	.switch_block_ref_else_multi => try sema.zirSwitchBlockMulti(block, inst, true, .@"else"),
	271	.switch_block_ref_under => try sema.zirSwitchBlock(block, inst, true, .under),
	272	.switch_block_ref_under_multi => try sema.zirSwitchBlockMulti(block, inst, true, .under),
	273	.switch_capture => try sema.zirSwitchCapture(block, inst, false, false),
	274	.switch_capture_ref => try sema.zirSwitchCapture(block, inst, false, true),
	275	.switch_capture_multi => try sema.zirSwitchCapture(block, inst, true, false),
	276	.switch_capture_multi_ref => try sema.zirSwitchCapture(block, inst, true, true),
	277	.switch_capture_else => try sema.zirSwitchCaptureElse(block, inst, false),
	278	.switch_capture_else_ref => try sema.zirSwitchCaptureElse(block, inst, true),
279	279	.type_info => try sema.zirTypeInfo(block, inst),
280	280	.size_of => try sema.zirSizeOf(block, inst),
281	281	.bit_size_of => try sema.zirBitSizeOf(block, inst),
...	...	@@ -534,7 +534,6 @@ pub fn analyzeBody(
534	534	return break_inst;
535	535	}
536	536	},
537		else => \|t\| @panic(@tagName(t)),
538	537	};
539	538	if (sema.typeOf(air_inst).isNoReturn())
540	539	return always_noreturn;
...	...	@@ -4110,8 +4109,8 @@ fn analyzeSwitch(
4110	4109	const body = sema.code.extra[extra_index..][0..body_len];
4111	4110	extra_index += body_len;
4112	4111
	4112	const item = sema.resolveInst(item_ref);
4113	4113	// Validation above ensured these will succeed.
4114		const item = sema.resolveInst(item_ref) catch unreachable;
4115	4114	const item_val = sema.resolveConstValue(&child_block, .unneeded, item) catch unreachable;
4116	4115	if (operand_val.eql(item_val)) {
4117	4116	return sema.resolveBlockBody(block, src, &child_block, body, merges);
...	...	@@ -4132,9 +4131,9 @@ fn analyzeSwitch(
4132	4131	const body = sema.code.extra[extra_index + 2 * ranges_len ..][0..body_len];
4133	4132
4134	4133	for (items) \|item_ref\| {
	4134	const item = sema.resolveInst(item_ref);
4135	4135	// Validation above ensured these will succeed.
4136		const item = sema.resolveInst(item_ref) catch unreachable;
4137		const item_val = sema.resolveConstValue(&child_block, item.src, item) catch unreachable;
	4136	const item_val = sema.resolveConstValue(&child_block, .unneeded, item) catch unreachable;
4138	4137	if (operand_val.eql(item_val)) {
4139	4138	return sema.resolveBlockBody(block, src, &child_block, body, merges);
4140	4139	}
...	...	@@ -4171,156 +4170,157 @@ fn analyzeSwitch(
4171	4170
4172	4171	// TODO when reworking AIR memory layout make multi cases get generated as cases,
4173	4172	// not as part of the "else" block.
4174		const cases = try sema.arena.alloc(Inst.SwitchBr.Case, scalar_cases_len);
	4173	return mod.fail(&block.base, src, "TODO rework runtime switch Sema", .{});
	4174	//const cases = try sema.arena.alloc(Inst.SwitchBr.Case, scalar_cases_len);
4175	4175
4176		var case_block = child_block.makeSubBlock();
4177		case_block.runtime_loop = null;
4178		case_block.runtime_cond = operand.src;
4179		case_block.runtime_index += 1;
4180		defer case_block.instructions.deinit(gpa);
	4176	//var case_block = child_block.makeSubBlock();
	4177	//case_block.runtime_loop = null;
	4178	//case_block.runtime_cond = operand.src;
	4179	//case_block.runtime_index += 1;
	4180	//defer case_block.instructions.deinit(gpa);
4181	4181
4182		var extra_index: usize = special.end;
	4182	//var extra_index: usize = special.end;
4183	4183
4184		var scalar_i: usize = 0;
4185		while (scalar_i < scalar_cases_len) : (scalar_i += 1) {
4186		const item_ref = @intToEnum(Zir.Inst.Ref, sema.code.extra[extra_index]);
4187		extra_index += 1;
4188		const body_len = sema.code.extra[extra_index];
4189		extra_index += 1;
4190		const body = sema.code.extra[extra_index..][0..body_len];
4191		extra_index += body_len;
4192
4193		case_block.instructions.shrinkRetainingCapacity(0);
4194		// We validate these above; these two calls are guaranteed to succeed.
4195		const item = sema.resolveInst(item_ref) catch unreachable;
4196		const item_val = sema.resolveConstValue(&case_block, .unneeded, item) catch unreachable;
4197
4198		_ = try sema.analyzeBody(&case_block, body);
4199
4200		cases[scalar_i] = .{
4201		.item = item_val,
4202		.body = .{ .instructions = try sema.arena.dupe(Air.Inst.Index, case_block.instructions.items) },
4203		};
4204		}
4205
4206		var first_else_body: Body = undefined;
4207		var prev_condbr: ?*Inst.CondBr = null;
4208
4209		var multi_i: usize = 0;
4210		while (multi_i < multi_cases_len) : (multi_i += 1) {
4211		const items_len = sema.code.extra[extra_index];
4212		extra_index += 1;
4213		const ranges_len = sema.code.extra[extra_index];
4214		extra_index += 1;
4215		const body_len = sema.code.extra[extra_index];
4216		extra_index += 1;
4217		const items = sema.code.refSlice(extra_index, items_len);
4218		extra_index += items_len;
4219
4220		case_block.instructions.shrinkRetainingCapacity(0);
4221
4222		var any_ok: ?Air.Inst.Index = null;
4223
4224		for (items) \|item_ref\| {
4225		const item = sema.resolveInst(item_ref);
4226		_ = try sema.resolveConstValue(&child_block, item.src, item);
4227
4228		const cmp_ok = try case_block.addBinOp(.cmp_eq, operand, item);
4229		if (any_ok) \|some\| {
4230		any_ok = try case_block.addBinOp(.bool_or, some, cmp_ok);
4231		} else {
4232		any_ok = cmp_ok;
4233		}
4234		}
4235
4236		var range_i: usize = 0;
4237		while (range_i < ranges_len) : (range_i += 1) {
4238		const first_ref = @intToEnum(Zir.Inst.Ref, sema.code.extra[extra_index]);
4239		extra_index += 1;
4240		const last_ref = @intToEnum(Zir.Inst.Ref, sema.code.extra[extra_index]);
4241		extra_index += 1;
4242
4243		const item_first = sema.resolveInst(first_ref);
4244		const item_last = sema.resolveInst(last_ref);
4245
4246		_ = try sema.resolveConstValue(&child_block, item_first.src, item_first);
4247		_ = try sema.resolveConstValue(&child_block, item_last.src, item_last);
	4184	//var scalar_i: usize = 0;
	4185	//while (scalar_i < scalar_cases_len) : (scalar_i += 1) {
	4186	// const item_ref = @intToEnum(Zir.Inst.Ref, sema.code.extra[extra_index]);
	4187	// extra_index += 1;
	4188	// const body_len = sema.code.extra[extra_index];
	4189	// extra_index += 1;
	4190	// const body = sema.code.extra[extra_index..][0..body_len];
	4191	// extra_index += body_len;
4248	4192
4249		// operand >= first and operand <= last
4250		const range_first_ok = try case_block.addBinOp(
4251		.cmp_gte,
4252		operand,
4253		item_first,
4254		);
4255		const range_last_ok = try case_block.addBinOp(
4256		.cmp_lte,
4257		operand,
4258		item_last,
4259		);
4260		const range_ok = try case_block.addBinOp(
4261		.bool_and,
4262		range_first_ok,
4263		range_last_ok,
4264		);
4265		if (any_ok) \|some\| {
4266		any_ok = try case_block.addBinOp(.bool_or, some, range_ok);
4267		} else {
4268		any_ok = range_ok;
4269		}
4270		}
	4193	// case_block.instructions.shrinkRetainingCapacity(0);
	4194	// const item = sema.resolveInst(item_ref);
	4195	// // We validate these above; these two calls are guaranteed to succeed.
	4196	// const item_val = sema.resolveConstValue(&case_block, .unneeded, item) catch unreachable;
4271	4197
4272		const new_condbr = try sema.arena.create(Inst.CondBr);
4273		new_condbr.* = .{
4274		.base = .{
4275		.tag = .condbr,
4276		.ty = Type.initTag(.noreturn),
4277		.src = src,
4278		},
4279		.condition = any_ok.?,
4280		.then_body = undefined,
4281		.else_body = undefined,
4282		};
4283		try case_block.instructions.append(gpa, &new_condbr.base);
	4198	// _ = try sema.analyzeBody(&case_block, body);
4284	4199
4285		const cond_body: Body = .{
4286		.instructions = try sema.arena.dupe(Air.Inst.Index, case_block.instructions.items),
4287		};
	4200	// cases[scalar_i] = .{
	4201	// .item = item_val,
	4202	// .body = .{ .instructions = try sema.arena.dupe(Air.Inst.Index, case_block.instructions.items) },
	4203	// };
	4204	//}
4288	4205
4289		case_block.instructions.shrinkRetainingCapacity(0);
4290		const body = sema.code.extra[extra_index..][0..body_len];
4291		extra_index += body_len;
4292		_ = try sema.analyzeBody(&case_block, body);
4293		new_condbr.then_body = .{
4294		.instructions = try sema.arena.dupe(Air.Inst.Index, case_block.instructions.items),
4295		};
4296		if (prev_condbr) \|condbr\| {
4297		condbr.else_body = cond_body;
4298		} else {
4299		first_else_body = cond_body;
4300		}
4301		prev_condbr = new_condbr;
4302		}
4303
4304		const final_else_body: Body = blk: {
4305		if (special.body.len != 0) {
4306		case_block.instructions.shrinkRetainingCapacity(0);
4307		_ = try sema.analyzeBody(&case_block, special.body);
4308		const else_body: Body = .{
4309		.instructions = try sema.arena.dupe(Air.Inst.Index, case_block.instructions.items),
4310		};
4311		if (prev_condbr) \|condbr\| {
4312		condbr.else_body = else_body;
4313		break :blk first_else_body;
4314		} else {
4315		break :blk else_body;
4316		}
4317		} else {
4318		break :blk .{ .instructions = &.{} };
4319		}
4320		};
	4206	//var first_else_body: Body = undefined;
	4207	//var prev_condbr: ?*Inst.CondBr = null;
4321	4208
4322		_ = try child_block.addSwitchBr(src, operand, cases, final_else_body);
4323		return sema.analyzeBlockBody(block, src, &child_block, merges);
	4209	//var multi_i: usize = 0;
	4210	//while (multi_i < multi_cases_len) : (multi_i += 1) {
	4211	// const items_len = sema.code.extra[extra_index];
	4212	// extra_index += 1;
	4213	// const ranges_len = sema.code.extra[extra_index];
	4214	// extra_index += 1;
	4215	// const body_len = sema.code.extra[extra_index];
	4216	// extra_index += 1;
	4217	// const items = sema.code.refSlice(extra_index, items_len);
	4218	// extra_index += items_len;
	4219
	4220	// case_block.instructions.shrinkRetainingCapacity(0);
	4221
	4222	// var any_ok: ?Air.Inst.Index = null;
	4223
	4224	// for (items) \|item_ref\| {
	4225	// const item = sema.resolveInst(item_ref);
	4226	// _ = try sema.resolveConstValue(&child_block, item.src, item);
	4227
	4228	// const cmp_ok = try case_block.addBinOp(.cmp_eq, operand, item);
	4229	// if (any_ok) \|some\| {
	4230	// any_ok = try case_block.addBinOp(.bool_or, some, cmp_ok);
	4231	// } else {
	4232	// any_ok = cmp_ok;
	4233	// }
	4234	// }
	4235
	4236	// var range_i: usize = 0;
	4237	// while (range_i < ranges_len) : (range_i += 1) {
	4238	// const first_ref = @intToEnum(Zir.Inst.Ref, sema.code.extra[extra_index]);
	4239	// extra_index += 1;
	4240	// const last_ref = @intToEnum(Zir.Inst.Ref, sema.code.extra[extra_index]);
	4241	// extra_index += 1;
	4242
	4243	// const item_first = sema.resolveInst(first_ref);
	4244	// const item_last = sema.resolveInst(last_ref);
	4245
	4246	// _ = try sema.resolveConstValue(&child_block, item_first.src, item_first);
	4247	// _ = try sema.resolveConstValue(&child_block, item_last.src, item_last);
	4248
	4249	// // operand >= first and operand <= last
	4250	// const range_first_ok = try case_block.addBinOp(
	4251	// .cmp_gte,
	4252	// operand,
	4253	// item_first,
	4254	// );
	4255	// const range_last_ok = try case_block.addBinOp(
	4256	// .cmp_lte,
	4257	// operand,
	4258	// item_last,
	4259	// );
	4260	// const range_ok = try case_block.addBinOp(
	4261	// .bool_and,
	4262	// range_first_ok,
	4263	// range_last_ok,
	4264	// );
	4265	// if (any_ok) \|some\| {
	4266	// any_ok = try case_block.addBinOp(.bool_or, some, range_ok);
	4267	// } else {
	4268	// any_ok = range_ok;
	4269	// }
	4270	// }
	4271
	4272	// const new_condbr = try sema.arena.create(Inst.CondBr);
	4273	// new_condbr.* = .{
	4274	// .base = .{
	4275	// .tag = .condbr,
	4276	// .ty = Type.initTag(.noreturn),
	4277	// .src = src,
	4278	// },
	4279	// .condition = any_ok.?,
	4280	// .then_body = undefined,
	4281	// .else_body = undefined,
	4282	// };
	4283	// try case_block.instructions.append(gpa, &new_condbr.base);
	4284
	4285	// const cond_body: Body = .{
	4286	// .instructions = try sema.arena.dupe(Air.Inst.Index, case_block.instructions.items),
	4287	// };
	4288
	4289	// case_block.instructions.shrinkRetainingCapacity(0);
	4290	// const body = sema.code.extra[extra_index..][0..body_len];
	4291	// extra_index += body_len;
	4292	// _ = try sema.analyzeBody(&case_block, body);
	4293	// new_condbr.then_body = .{
	4294	// .instructions = try sema.arena.dupe(Air.Inst.Index, case_block.instructions.items),
	4295	// };
	4296	// if (prev_condbr) \|condbr\| {
	4297	// condbr.else_body = cond_body;
	4298	// } else {
	4299	// first_else_body = cond_body;
	4300	// }
	4301	// prev_condbr = new_condbr;
	4302	//}
	4303
	4304	//const final_else_body: Body = blk: {
	4305	// if (special.body.len != 0) {
	4306	// case_block.instructions.shrinkRetainingCapacity(0);
	4307	// _ = try sema.analyzeBody(&case_block, special.body);
	4308	// const else_body: Body = .{
	4309	// .instructions = try sema.arena.dupe(Air.Inst.Index, case_block.instructions.items),
	4310	// };
	4311	// if (prev_condbr) \|condbr\| {
	4312	// condbr.else_body = else_body;
	4313	// break :blk first_else_body;
	4314	// } else {
	4315	// break :blk else_body;
	4316	// }
	4317	// } else {
	4318	// break :blk .{ .instructions = &.{} };
	4319	// }
	4320	//};
	4321
	4322	//_ = try child_block.addSwitchBr(src, operand, cases, final_else_body);
	4323	//return sema.analyzeBlockBody(block, src, &child_block, merges);
4324	4324	}
4325	4325
4326	4326	fn resolveSwitchItemVal(
...	...	@@ -4332,16 +4332,17 @@ fn resolveSwitchItemVal(
4332	4332	range_expand: Module.SwitchProngSrc.RangeExpand,
4333	4333	) CompileError!TypedValue {
4334	4334	const item = sema.resolveInst(item_ref);
	4335	const item_ty = sema.typeOf(item);
4335	4336	// Constructing a LazySrcLoc is costly because we only have the switch AST node.
4336	4337	// Only if we know for sure we need to report a compile error do we resolve the
4337	4338	// full source locations.
4338	4339	if (sema.resolveConstValue(block, .unneeded, item)) \|val\| {
4339		return TypedValue{ .ty = item.ty, .val = val };
	4340	return TypedValue{ .ty = item_ty, .val = val };
4340	4341	} else \|err\| switch (err) {
4341	4342	error.NeededSourceLocation => {
4342	4343	const src = switch_prong_src.resolve(sema.gpa, block.src_decl, switch_node_offset, range_expand);
4343	4344	return TypedValue{
4344		.ty = item.ty,
	4345	.ty = item_ty,
4345	4346	.val = try sema.resolveConstValue(block, src, item),
4346	4347	};
4347	4348	},

src/codegen.zig+69-5

...	...	@@ -452,6 +452,43 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
452	452	},
453	453	};
454	454
	455	const BigTomb = struct {
	456	function: *Self,
	457	inst: Air.Inst.Index,
	458	tomb_bits: Liveness.Bpi,
	459	big_tomb_bits: u32,
	460	bit_index: usize,
	461
	462	fn feed(bt: *BigTomb, op_ref: Air.Inst.Ref) void {
	463	const this_bit_index = bt.bit_index;
	464	bt.bit_index += 1;
	465
	466	const op_int = @enumToInt(op_ref);
	467	if (op_int < Air.Inst.Ref.typed_value_map.len) return;
	468	const op_index = @intCast(Air.Inst.Index, op_int - Air.Inst.Ref.typed_value_map.len);
	469
	470	if (this_bit_index < Liveness.bpi - 1) {
	471	const dies = @truncate(u1, bt.tomb_bits >> @intCast(Liveness.OperandInt, this_bit_index)) != 0;
	472	if (!dies) return;
	473	} else {
	474	const big_bit_index = @intCast(u5, this_bit_index - (Liveness.bpi - 1));
	475	const dies = @truncate(u1, bt.big_tomb_bits >> big_bit_index) != 0;
	476	if (!dies) return;
	477	}
	478	bt.function.processDeath(op_index);
	479	}
	480
	481	fn finishAir(bt: *BigTomb, result: MCValue) void {
	482	const is_used = !bt.function.liveness.isUnused(bt.inst);
	483	if (is_used) {
	484	log.debug("{} => {}", .{ bt.inst, result });
	485	const branch = &bt.function.branch_stack.items[bt.function.branch_stack.items.len - 1];
	486	branch.inst_table.putAssumeCapacityNoClobber(bt.inst, result);
	487	}
	488	bt.function.finishAirBookkeeping();
	489	}
	490	};
	491
455	492	const Self = @This();
456	493
457	494	fn generate(
...	...	@@ -921,8 +958,8 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
921	958	if (!dies) continue;
922	959	const op_int = @enumToInt(op);
923	960	if (op_int < Air.Inst.Ref.typed_value_map.len) continue;
924		const operand: Air.Inst.Index = op_int - @intCast(u32, Air.Inst.Ref.typed_value_map.len);
925		self.processDeath(operand);
	961	const op_index = @intCast(Air.Inst.Index, op_int - Air.Inst.Ref.typed_value_map.len);
	962	self.processDeath(op_index);
926	963	}
927	964	const is_used = @truncate(u1, tomb_bits) == 0;
928	965	if (is_used) {
...	...	@@ -2739,7 +2776,12 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
2739	2776	std.mem.copy(Air.Inst.Ref, buf[1..], args);
2740	2777	return self.finishAir(inst, result, buf);
2741	2778	}
2742		@panic("TODO: codegen for function call with greater than 2 args");
	2779	var bt = try self.iterateBigTomb(inst, 1 + args.len);
	2780	bt.feed(callee);
	2781	for (args) \|arg\| {
	2782	bt.feed(arg);
	2783	}
	2784	return bt.finishAir(result);
2743	2785	}
2744	2786
2745	2787	fn airRef(self: *Self, inst: Air.Inst.Index) !void {
...	...	@@ -3651,7 +3693,25 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
3651	3693	std.mem.copy(Air.Inst.Ref, buf[outputs.len..], args);
3652	3694	return self.finishAir(inst, result, buf);
3653	3695	}
3654		@panic("TODO: codegen for asm with greater than 3 args");
	3696	var bt = try self.iterateBigTomb(inst, outputs.len + args.len);
	3697	for (outputs) \|output\| {
	3698	bt.feed(output);
	3699	}
	3700	for (args) \|arg\| {
	3701	bt.feed(arg);
	3702	}
	3703	return bt.finishAir(result);
	3704	}
	3705
	3706	fn iterateBigTomb(self: *Self, inst: Air.Inst.Index, operand_count: usize) !BigTomb {
	3707	try self.ensureProcessDeathCapacity(operand_count + 1);
	3708	return BigTomb{
	3709	.function = self,
	3710	.inst = inst,
	3711	.tomb_bits = self.liveness.getTombBits(inst),
	3712	.big_tomb_bits = self.liveness.special.get(inst) orelse 0,
	3713	.bit_index = 0,
	3714	};
3655	3715	}
3656	3716
3657	3717	/// Sets the value without any modifications to register allocation metadata or stack allocation metadata.
...	...	@@ -4492,7 +4552,11 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
4492	4552	// First section of indexes correspond to a set number of constant values.
4493	4553	const ref_int = @enumToInt(inst);
4494	4554	if (ref_int < Air.Inst.Ref.typed_value_map.len) {
4495		return self.genTypedValue(Air.Inst.Ref.typed_value_map[ref_int]);
	4555	const tv = Air.Inst.Ref.typed_value_map[ref_int];
	4556	if (!tv.ty.hasCodeGenBits()) {
	4557	return MCValue{ .none = {} };
	4558	}
	4559	return self.genTypedValue(tv);
4496	4560	}
4497	4561
4498	4562	// If the type has no codegen bits, no need to store it.

src/print_air.zig+1-1

...	...	@@ -89,7 +89,7 @@ const Writer = struct {
89	89	if (w.liveness.isUnused(inst)) {
90	90	try s.writeAll(") unused\n");
91	91	} else {
92		try s.writeAll("\n");
	92	try s.writeAll(")\n");
93	93	}
94	94	}
95	95	}