From d30609829eb744b28a26a5161c2788dfdef3618d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= <alex@alexrp.com>
Date: Sun, 6 Sep 2026 09:09:09 +0200
Subject: [PATCH] std.zig.system.openbsd: bail aarch64 detection if we don't
 get all registers

---
 lib/std/zig/system/openbsd.zig | 42 ++++++++++++++++++----------------
 1 file changed, 22 insertions(+), 20 deletions(-)

diff --git a/lib/std/zig/system/openbsd.zig b/lib/std/zig/system/openbsd.zig
index 211222d33ed376e90f70e9461c856cea61fe918f..4a6b064210db8af1ade69625d6769657f1042420 100644
--- a/lib/std/zig/system/openbsd.zig
+++ b/lib/std/zig/system/openbsd.zig
@@ -4,7 +4,7 @@ const std = @import("std");
 const native_arch = builtin.target.cpu.arch;
 
 const aarch64 = struct {
-    fn sysctlReg(key: c_int) u64 {
+    fn sysctlReg(key: c_int) ?u64 {
         const mib: [2]c_int = [_]c_int{
             std.c.CTL.MACHDEP,
             key,
@@ -17,33 +17,35 @@ const aarch64 = struct {
             error.PermissionDenied => unreachable,
             error.SystemResources => unreachable,
             error.UnknownName => unreachable,
-            error.Unexpected => return 0,
+            error.Unexpected => return null,
         };
 
         return value;
     }
+
+    fn detectNativeCpuAndFeatures(arch: std.Target.Cpu.Arch) ?std.Target.Cpu {
+        const registers = [12]u64{
+            0, // MIDR_EL1
+            sysctlReg(std.c.CPU.AA64PFR0) orelse return null,
+            sysctlReg(std.c.CPU.AA64PFR1) orelse return null,
+            0, // ID_AA64DFR0_EL1
+            0, // ID_AA64DFR1_EL1
+            0, // ID_AA64AFR0_EL1
+            0, // ID_AA64AFR1_EL1
+            sysctlReg(std.c.CPU.ID_AA64ISAR0) orelse return null,
+            sysctlReg(std.c.CPU.ID_AA64ISAR1) orelse return null,
+            sysctlReg(std.c.CPU.ID_AA64MMFR0) orelse return null,
+            sysctlReg(std.c.CPU.ID_AA64MMFR1) orelse return null,
+            sysctlReg(std.c.CPU.ID_AA64MMFR2) orelse return null,
+        };
+
+        return @import("arm.zig").aarch64.detectNativeCpuAndFeatures(arch, registers);
+    }
 };
 
 pub fn detectNativeCpuAndFeatures() ?std.Target.Cpu {
     return switch (native_arch) {
-        .aarch64, .aarch64_be => b: {
-            const registers = [12]u64{
-                0, // MIDR_EL1
-                aarch64.sysctlReg(std.c.CPU.AA64PFR0),
-                aarch64.sysctlReg(std.c.CPU.AA64PFR1),
-                0, // ID_AA64DFR0_EL1
-                0, // ID_AA64DFR1_EL1
-                0, // ID_AA64AFR0_EL1
-                0, // ID_AA64AFR1_EL1
-                aarch64.sysctlReg(std.c.CPU.ID_AA64ISAR0),
-                aarch64.sysctlReg(std.c.CPU.ID_AA64ISAR1),
-                aarch64.sysctlReg(std.c.CPU.ID_AA64MMFR0),
-                aarch64.sysctlReg(std.c.CPU.ID_AA64MMFR1),
-                aarch64.sysctlReg(std.c.CPU.ID_AA64MMFR2),
-            };
-
-            break :b @import("arm.zig").aarch64.detectNativeCpuAndFeatures(native_arch, registers);
-        },
+        .aarch64 => aarch64.detectNativeCpuAndFeatures(native_arch),
         else => null,
     };
 }
-- 
2.54.0