| ... | ... | @@ -966,7 +966,7 @@ fn airTrunc(self: *Self, inst: Air.Inst.Index) !void { |
| 966 | 966 | const reg: Register = blk: { |
| 967 | 967 | if (operand.isRegister()) { |
| 968 | 968 | if (self.reuseOperand(inst, ty_op.operand, 0, operand)) { |
| 969 | | break :blk operand.register; |
| 969 | break :blk operand.register.to64(); |
| 970 | 970 | } |
| 971 | 971 | } |
| 972 | 972 | const mcv = try self.copyToNewRegister(inst, src_ty, operand); |
| ... | ... | @@ -2300,7 +2300,6 @@ fn genBinMathOp(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs: |
| 2300 | 2300 | const mcvs = try self.mcvsForBinMathOp(inst, op_lhs, op_rhs); |
| 2301 | 2301 | const dst_mcv = mcvs.dst; |
| 2302 | 2302 | const src_mcv = mcvs.src; |
| 2303 | | log.warn("dst_mcv = {}, src_mcv = {}", .{ dst_mcv, src_mcv }); |
| 2304 | 2303 | const tag = self.air.instructions.items(.tag)[inst]; |
| 2305 | 2304 | switch (tag) { |
| 2306 | 2305 | .add, .addwrap => try self.genBinMathOpMir(.add, dst_ty, dst_mcv, src_mcv), |