From d70b56429c4f518c92f6419ce369d6098650ff96 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= <alex@alexrp.com>
Date: Fri, 22 May 2026 21:12:28 +0200
Subject: [PATCH] std.zig.system.linux: add detection for more RISC-V CPU
 models

---
 lib/std/zig/system/linux.zig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/lib/std/zig/system/linux.zig b/lib/std/zig/system/linux.zig
index 60f4d7bfec86233b578bca8a1a437d9207140b83..82f13bc7a411a65b7ad0ae6536b94824257d9038 100644
--- a/lib/std/zig/system/linux.zig
+++ b/lib/std/zig/system/linux.zig
@@ -70,12 +70,16 @@ const RiscvCpuinfoImpl = struct {
     model: ?*const Target.Cpu.Model = null,
 
     const cpu_names = .{
+        .{ "andestech,ax45mp", &Target.riscv.cpu.andes_ax45 },
+        .{ "sifive,p550", &Target.riscv.cpu.sifive_p550 },
         .{ "sifive,u54", &Target.riscv.cpu.sifive_u54 },
         .{ "sifive,u54-mc", &Target.riscv.cpu.sifive_u54 },
         .{ "sifive,u7", &Target.riscv.cpu.sifive_7_series },
         .{ "sifive,u74", &Target.riscv.cpu.sifive_u74 },
         .{ "sifive,u74-mc", &Target.riscv.cpu.sifive_u74 },
+        .{ "sifive,x280", &Target.riscv.cpu.sifive_x280 },
         .{ "spacemit,x60", &Target.riscv.cpu.spacemit_x60 },
+        .{ "spacemit,x100", &Target.riscv.cpu.spacemit_x100 },
     };
 
     fn line_hook(self: *RiscvCpuinfoImpl, key: []const u8, value: []const u8) !bool {
-- 
2.54.0