diff --git a/src/Air.zig b/src/Air.zig index 275857214ebb3638bedc3e785620cd18939f031d..e20dc0c9adc0c81b387ec536be60bf485d63a742 100644 --- a/src/Air.zig +++ b/src/Air.zig @@ -538,12 +538,6 @@ pub const Inst = struct { /// Result type is always bool. /// Uses the `un_op` field. is_non_err_ptr, - /// Result type is always bool. - /// Uses the `bin_op` field. - bool_and, - /// Result type is always bool. - /// Uses the `bin_op` field. - bool_or, /// Read a value from a pointer. /// Uses the `ty_op` field. load, @@ -1580,8 +1574,6 @@ pub fn typeOfIndex(air: *const Air, inst: Air.Inst.Index, ip: *const InternPool) .shl_sat, .min, .max, - .bool_and, - .bool_or, .add_optimized, .sub_optimized, .mul_optimized, @@ -2010,8 +2002,6 @@ pub fn mustLower(air: Air, inst: Air.Inst.Index, ip: *const InternPool) bool { .is_non_null, .is_err, .is_non_err, - .bool_and, - .bool_or, .fptrunc, .fpext, .intcast, diff --git a/src/Air/Legalize.zig b/src/Air/Legalize.zig index 1eeed71bd30ccedd59120056f3e1f395c185597b..b24dcfe6ac8a7eeb6c43dab7bb0ac8f4b720b4d1 100644 --- a/src/Air/Legalize.zig +++ b/src/Air/Legalize.zig @@ -713,8 +713,6 @@ fn legalizeBody(l: *Legalize, body_start: usize, body_len: usize) Error!void { .is_non_err, .is_err_ptr, .is_non_err_ptr, - .bool_and, - .bool_or, => {}, .load => if (l.features.has(.expand_packed_load)) { const ty_op = l.air_instructions.items(.data)[@intFromEnum(inst)].ty_op; @@ -2018,7 +2016,7 @@ fn safeIntcastBlockPayload(l: *Legalize, orig_inst: Air.Inst.Index) Error!Air.In } else undefined; const out_of_range_inst: Air.Inst.Index = inst: { if (have_min_check and have_max_check) break :inst cur_block.add(l, .{ - .tag = .bool_or, + .tag = .bit_or, .data = .{ .bin_op = .{ .lhs = below_min_inst.toRef(), .rhs = above_max_inst.toRef(), @@ -2156,7 +2154,7 @@ fn safeIntFromFloatBlockPayload(l: *Legalize, orig_inst: Air.Inst.Index, optimiz // Combine the conditions. const out_of_bounds_inst: Air.Inst.Index = main_block.add(l, .{ - .tag = .bool_or, + .tag = .bit_or, .data = .{ .bin_op = .{ .lhs = below_min_inst.toRef(), .rhs = above_max_inst.toRef(), diff --git a/src/Air/Liveness.zig b/src/Air/Liveness.zig index 402873227a738953ee6ce9546115e39b75c0331a..e353400340d4a06eb32916ccc18969c95ae96e5e 100644 --- a/src/Air/Liveness.zig +++ b/src/Air/Liveness.zig @@ -436,8 +436,6 @@ fn analyzeInst( .cmp_gt_optimized, .cmp_neq, .cmp_neq_optimized, - .bool_and, - .bool_or, .store, .store_safe, .array_elem_val, diff --git a/src/Air/Liveness/Verify.zig b/src/Air/Liveness/Verify.zig index fd8f735741bf905ce80d5dbbf69e54425b1e2e63..294a68fc4640072ce924a986e3a6ae0125bf04d4 100644 --- a/src/Air/Liveness/Verify.zig +++ b/src/Air/Liveness/Verify.zig @@ -249,8 +249,6 @@ fn verifyBody(self: *Verify, body: []const Air.Inst.Index) Error!void { .cmp_gt_optimized, .cmp_neq, .cmp_neq_optimized, - .bool_and, - .bool_or, .store, .store_safe, .array_elem_val, diff --git a/src/Air/print.zig b/src/Air/print.zig index b1114b39c3dfc154705b9e5c8324b200514a6a91..be328d86716cf56502dc209f35e36387c7de4c1a 100644 --- a/src/Air/print.zig +++ b/src/Air/print.zig @@ -148,8 +148,6 @@ const Writer = struct { .cmp_gte, .cmp_gt, .cmp_neq, - .bool_and, - .bool_or, .store, .store_safe, .array_elem_val, diff --git a/src/Sema.zig b/src/Sema.zig index 6c919c60eb11993387143848e014e50856126209..6c841e959c4f2325bfe73641e4a51d59f8725dc8 100644 --- a/src/Sema.zig +++ b/src/Sema.zig @@ -4109,7 +4109,7 @@ fn zirForLen(sema: *Sema, block: *Block, inst: Zir.Inst.Index) CompileError!Air. if (i == len_idx) continue; const eq = try block.addBinOp(.cmp_eq, len, arg_len); ok = if (ok != .none) - try block.addBinOp(.bool_and, ok, eq) + try block.addBinOp(.bit_and, ok, eq) else eq; } @@ -7699,7 +7699,7 @@ fn zirErrorFromInt(sema: *Sema, block: *Block, extended: Zir.Inst.Extended.InstD const is_lte_len = try block.addUnOp(.cmp_lte_errors_len, operand); const zero_val = Air.internedToRef((try pt.intValue(err_int_ty, 0)).toIntern()); const is_non_zero = try block.addBinOp(.cmp_neq, operand, zero_val); - const ok = try block.addBinOp(.bool_and, is_lte_len, is_non_zero); + const ok = try block.addBinOp(.bit_and, is_lte_len, is_non_zero); try sema.addSafetyCheck(block, src, ok, .invalid_error_code); } return block.addInst(.{ @@ -14561,7 +14561,7 @@ fn addDivIntOverflowSafety( break :ok try block.addCmpVector(casted_rhs, neg_one_ref, .neq); }; - const ok = try block.addReduce(try block.addBinOp(.bool_or, lhs_ok, rhs_ok), .And); + const ok = try block.addReduce(try block.addBinOp(.bit_or, lhs_ok, rhs_ok), .And); try sema.addSafetyCheck(block, src, ok, .integer_overflow); } else { const lhs_ok: Air.Inst.Ref = if (maybe_lhs_val == null) ok: { @@ -14574,7 +14574,7 @@ fn addDivIntOverflowSafety( } else .none; // means false const ok = if (lhs_ok != .none and rhs_ok != .none) - try block.addBinOp(.bool_or, lhs_ok, rhs_ok) + try block.addBinOp(.bit_or, lhs_ok, rhs_ok) else if (lhs_ok != .none) lhs_ok else if (rhs_ok != .none) @@ -21236,7 +21236,7 @@ fn zirErrorCast(sema: *Sema, block: *Block, extended: Zir.Inst.Extended.InstData } else { // Error must be in destination set or zero. const has_value = try block.addTyOp(.error_set_has_value, dest_err_ty, err_int_inst); - const ok = try block.addBinOp(.bool_or, has_value, is_zero); + const ok = try block.addBinOp(.bit_or, has_value, is_zero); try sema.addSafetyCheck(block, src, ok, .invalid_error_code); } } else { @@ -21794,7 +21794,7 @@ fn ptrCastFull( assert(operand_ptr_int != .none); const ptr_is_non_zero = try block.addBinOp(.cmp_neq, operand_ptr_int, .zero_usize); const ok = if (src_info.flags.size == .slice and dest_info.flags.size == .slice) ok: { - break :ok try block.addBinOp(.bool_or, operand_len_is_zero, ptr_is_non_zero); + break :ok try block.addBinOp(.bit_or, operand_len_is_zero, ptr_is_non_zero); } else ptr_is_non_zero; try sema.addSafetyCheck(block, src, ok, .cast_to_null); } @@ -21807,7 +21807,7 @@ fn ptrCastFull( const ptr_masked = try block.addBinOp(.bit_and, operand_ptr_int, align_mask); const is_aligned = try block.addBinOp(.cmp_eq, ptr_masked, .zero_usize); const ok = if (src_info.flags.size == .slice and dest_info.flags.size == .slice) ok: { - break :ok try block.addBinOp(.bool_or, operand_len_is_zero, is_aligned); + break :ok try block.addBinOp(.bit_or, operand_len_is_zero, is_aligned); } else is_aligned; try sema.addSafetyCheck(block, src, ok, .incorrect_alignment); } @@ -24317,7 +24317,7 @@ fn zirMemcpy( const dest_plus_len = try sema.analyzePtrArithmetic(block, src, raw_dest_ptr, len, .ptr_add, src); const ok1 = try block.addBinOp(.cmp_gte, raw_dest_ptr, src_plus_len); const ok2 = try block.addBinOp(.cmp_gte, new_src_ptr, dest_plus_len); - const ok = try block.addBinOp(.bool_or, ok1, ok2); + const ok = try block.addBinOp(.bit_or, ok1, ok2); try sema.addSafetyCheck(block, src, ok, .memcpy_alias); } @@ -29524,7 +29524,7 @@ fn coerceCompatiblePtrs( const ok = if (inst_ty.isSlice(zcu)) ok: { const len = try sema.analyzeSliceLen(block, inst_src, inst); const len_zero = try block.addBinOp(.cmp_eq, len, .zero_usize); - break :ok try block.addBinOp(.bool_or, len_zero, is_non_zero); + break :ok try block.addBinOp(.bit_or, len_zero, is_non_zero); } else is_non_zero; try sema.addSafetyCheck(block, inst_src, ok, .cast_to_null); } diff --git a/src/codegen/aarch64/Select.zig b/src/codegen/aarch64/Select.zig index 4c45bb966766d02d79f067c005bef3d046b3e8a7..2aaebdbb769b3bc3204b42b3fbda0aaa0363fc5b 100644 --- a/src/codegen/aarch64/Select.zig +++ b/src/codegen/aarch64/Select.zig @@ -203,8 +203,6 @@ pub fn analyze(isel: *Select, air_body: []const Air.Inst.Index) !void { .cmp_gt_optimized, .cmp_neq, .cmp_neq_optimized, - .bool_and, - .bool_or, .array_elem_val, .slice_elem_val, .ptr_elem_val, @@ -2883,7 +2881,7 @@ pub fn body(isel: *Select, air_body: []const Air.Inst.Index) error{ OutOfMemory, if (air.next()) |next_air_tag| continue :air_tag next_air_tag; }, - .bit_and, .bit_or, .xor, .bool_and, .bool_or => |air_tag| { + .bit_and, .bit_or, .xor => |air_tag| { if (isel.live_values.fetchRemove(air.inst_index)) |res_vi| { defer res_vi.value.deref(isel); @@ -2914,12 +2912,12 @@ pub fn body(isel: *Select, air_body: []const Air.Inst.Index) error{ OutOfMemory, const rhs_part_mat = try rhs_part_vi.?.matReg(isel); try isel.emit(switch (air_tag) { else => unreachable, - .bit_and, .bool_and => switch (size) { + .bit_and => switch (size) { else => unreachable, 1, 2, 4 => .@"and"(res_part_ra.w(), lhs_part_mat.ra.w(), .{ .register = rhs_part_mat.ra.w() }), 8 => .@"and"(res_part_ra.x(), lhs_part_mat.ra.x(), .{ .register = rhs_part_mat.ra.x() }), }, - .bit_or, .bool_or => switch (size) { + .bit_or => switch (size) { else => unreachable, 1, 2, 4 => .orr(res_part_ra.w(), lhs_part_mat.ra.w(), .{ .register = rhs_part_mat.ra.w() }), 8 => .orr(res_part_ra.x(), lhs_part_mat.ra.x(), .{ .register = rhs_part_mat.ra.x() }), diff --git a/src/codegen/c.zig b/src/codegen/c.zig index 519a4f0bb7653f350daa97d08172df271d546d0c..ee9e90ce8095e5ed537fe45cd44c83b9c02194c7 100644 --- a/src/codegen/c.zig +++ b/src/codegen/c.zig @@ -2728,9 +2728,8 @@ fn genBodyInner(f: *Function, body: []const Air.Inst.Index) Error!void { }, .cmp_lte_errors_len => try airCmpLteErrorsLen(f, inst), - // bool_and and bool_or are non-short-circuit operations - .bool_and, .bit_and => try airBinOp(f, inst, "&", "and", .none), - .bool_or, .bit_or => try airBinOp(f, inst, "|", "or", .none), + .bit_and => try airBinOp(f, inst, "&", "and", .none), + .bit_or => try airBinOp(f, inst, "|", "or", .none), .xor => try airBinOp(f, inst, "^", "xor", .none), .shr, .shr_exact => try airBinBuiltinCall(f, inst, "shr", .none), .shl, => try airBinBuiltinCall(f, inst, "shlw", .bits), diff --git a/src/codegen/llvm/FuncGen.zig b/src/codegen/llvm/FuncGen.zig index 37b0df3d85fc1e4e319e722b3c8441a4221b2294..b2f1d6211e2a0e30f3eb0f157b759d65ae53736b 100644 --- a/src/codegen/llvm/FuncGen.zig +++ b/src/codegen/llvm/FuncGen.zig @@ -258,11 +258,11 @@ pub fn genBody(self: *FuncGen, body: []const Air.Inst.Index, coverage_point: Air .mul_with_overflow => try self.airOverflow(inst, .@"smul.with.overflow", .@"umul.with.overflow"), .shl_with_overflow => try self.airShlWithOverflow(inst), - .bit_and, .bool_and => try self.airAnd(inst), - .bit_or, .bool_or => try self.airOr(inst), - .xor => try self.airXor(inst), - .shr => try self.airShr(inst, false), - .shr_exact => try self.airShr(inst, true), + .bit_and => try self.airAnd(inst), + .bit_or => try self.airOr(inst), + .xor => try self.airXor(inst), + .shr => try self.airShr(inst, false), + .shr_exact => try self.airShr(inst, true), .sqrt => try self.airUnaryOp(inst, .sqrt), .sin => try self.airUnaryOp(inst, .sin), diff --git a/src/codegen/riscv64/CodeGen.zig b/src/codegen/riscv64/CodeGen.zig index 6b65704a4bed0862fa1ea064449a9f0a2ca29ba9..b5427dc9bfedcbb682de788a2dbdc2247d57bc5c 100644 --- a/src/codegen/riscv64/CodeGen.zig +++ b/src/codegen/riscv64/CodeGen.zig @@ -1415,8 +1415,6 @@ fn genBody(func: *Func, body: []const Air.Inst.Index) InnerError!void { .shl, .shl_exact, .shr, .shr_exact, - .bool_and, - .bool_or, .bit_and, .bit_or, @@ -2702,13 +2700,11 @@ fn genBinOp( .bit_and, .bit_or, - .bool_and, - .bool_or, => { _ = try func.addInst(.{ .tag = switch (tag) { - .bit_and, .bool_and => .@"and", - .bit_or, .bool_or => .@"or", + .bit_and => .@"and", + .bit_or => .@"or", else => unreachable, }, .data = .{ @@ -2719,13 +2715,6 @@ fn genBinOp( }, }, }); - - switch (tag) { - .bool_and, - .bool_or, - => try func.truncateRegister(Type.bool, dst_reg), - else => {}, - } }, .shr, diff --git a/src/codegen/sparc64/CodeGen.zig b/src/codegen/sparc64/CodeGen.zig index 3116a1183fa65cbf185273e81ade65c6f221a6a7..07df51152dab5ac2931e60ef91c6914978d8ac35 100644 --- a/src/codegen/sparc64/CodeGen.zig +++ b/src/codegen/sparc64/CodeGen.zig @@ -499,8 +499,6 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void { .shl_exact => try self.airBinOp(inst, .shl_exact), .shr => try self.airBinOp(inst, .shr), .shr_exact => try self.airBinOp(inst, .shr_exact), - .bool_and => try self.airBinOp(inst, .bool_and), - .bool_or => try self.airBinOp(inst, .bool_or), .bit_and => try self.airBinOp(inst, .bit_and), .bit_or => try self.airBinOp(inst, .bit_or), .xor => try self.airBinOp(inst, .xor), @@ -2941,26 +2939,6 @@ fn binOp( } }, - .bool_and, - .bool_or, - => { - switch (lhs_ty.zigTypeTag(zcu)) { - .bool => { - assert(lhs != .immediate); // should have been handled by Sema - assert(rhs != .immediate); // should have been handled by Sema - - const mir_tag: Mir.Inst.Tag = switch (tag) { - .bool_and => .@"and", - .bool_or => .@"or", - else => unreachable, - }; - - return try self.binOpRegister(mir_tag, lhs, rhs, lhs_ty, rhs_ty, metadata); - }, - else => unreachable, - } - }, - .shl, .shr, => { diff --git a/src/codegen/spirv/CodeGen.zig b/src/codegen/spirv/CodeGen.zig index 4ce1681129568085499a611caea0d5f0c1b8eeef..aa0b43bada599e678dcd772ae8e2ccefdc31118f 100644 --- a/src/codegen/spirv/CodeGen.zig +++ b/src/codegen/spirv/CodeGen.zig @@ -2693,8 +2693,6 @@ fn genInst(cg: *CodeGen, inst: Air.Inst.Index) Error!void { .bit_and => try cg.airBinOpSimple(inst, .OpBitwiseAnd), .bit_or => try cg.airBinOpSimple(inst, .OpBitwiseOr), .xor => try cg.airBinOpSimple(inst, .OpBitwiseXor), - .bool_and => try cg.airBinOpSimple(inst, .OpLogicalAnd), - .bool_or => try cg.airBinOpSimple(inst, .OpLogicalOr), .shl, .shl_exact => try cg.airShift(inst, .OpShiftLeftLogical, .OpShiftLeftLogical), .shr, .shr_exact => try cg.airShift(inst, .OpShiftRightLogical, .OpShiftRightArithmetic), diff --git a/src/codegen/wasm/CodeGen.zig b/src/codegen/wasm/CodeGen.zig index 05181e22839d8d49d4b915c088d3f74fd49aca70..3a89f6bd596f5114915625893e06e288ce900528 100644 --- a/src/codegen/wasm/CodeGen.zig +++ b/src/codegen/wasm/CodeGen.zig @@ -1516,7 +1516,7 @@ fn genInst(cg: *CodeGen, inst: Air.Inst.Index) InnerError!void { try cg.finishAir(inst, result, &.{ bin_op.lhs, bin_op.rhs }); }, - .bit_and, .bit_or, .bool_and, .bool_or, .xor, .shl_exact, .shr, .shr_exact => |tag| { + .bit_and, .bit_or, .xor, .shl_exact, .shr, .shr_exact => |tag| { const bin_op = cg.air.instructions.items(.data)[@intFromEnum(inst)].bin_op; const lhs = try cg.resolveInst(bin_op.lhs); const rhs = try cg.resolveInst(bin_op.rhs); @@ -1528,8 +1528,8 @@ fn genInst(cg: *CodeGen, inst: Air.Inst.Index) InnerError!void { const int_ty: IntType = .fromType(cg, ty); const result = switch (tag) { - .bit_and, .bool_and => try cg.intAnd(int_ty, lhs, rhs), - .bit_or, .bool_or => try cg.intOr(int_ty, lhs, rhs), + .bit_and => try cg.intAnd(int_ty, lhs, rhs), + .bit_or => try cg.intOr(int_ty, lhs, rhs), .xor => try cg.intXor(int_ty, lhs, rhs), .shl_exact => try cg.intShl(int_ty, lhs, rhs), .shr, .shr_exact => try cg.intShr(int_ty, lhs, rhs), diff --git a/src/codegen/x86_64/CodeGen.zig b/src/codegen/x86_64/CodeGen.zig index d939047933b5607da22206318090002490dbfb88..fca1cbbd23df78ea68d203a67340d7a1b15447a0 100644 --- a/src/codegen/x86_64/CodeGen.zig +++ b/src/codegen/x86_64/CodeGen.zig @@ -60839,14 +60839,14 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void { try slot.finish(inst, &.{}, &.{}, cg); }, .assembly => try cg.airAsm(inst), - .bit_and, .bit_or, .xor, .bool_and, .bool_or => |air_tag| { + .bit_and, .bit_or, .xor => |air_tag| { const bin_op = air_datas[@intFromEnum(inst)].bin_op; var ops = try cg.tempsFromOperands(inst, .{ bin_op.lhs, bin_op.rhs }); var res: [1]Temp = undefined; cg.select(&res, &.{cg.typeOf(bin_op.lhs)}, &ops, switch (@as(Mir.Inst.Tag, switch (air_tag) { else => unreachable, - .bit_and, .bool_and => .@"and", - .bit_or, .bool_or => .@"or", + .bit_and => .@"and", + .bit_or => .@"or", .xor => .xor, })) { else => unreachable,