diff --git a/lib/std/zig/system/freebsd.zig b/lib/std/zig/system/freebsd.zig
index be7a09f6402b65832356e9865c42b74e9f7cdc40..d36600aaa1810b5f2c0c6d52cdfc387c44bd7bab 100644
--- a/lib/std/zig/system/freebsd.zig
+++ b/lib/std/zig/system/freebsd.zig
@@ -3,28 +3,30 @@ const std = @import("std");
 
 const native_arch = builtin.target.cpu.arch;
 
-inline fn getAArch64CpuFeature(comptime feat_reg: []const u8) u64 {
-    return asm ("mrs %[ret], " ++ feat_reg
-        : [ret] "=r" (-> u64),
-    );
-}
+const aarch64 = struct {
+    inline fn mrs(comptime feat_reg: []const u8) u64 {
+        return asm ("mrs %[ret], " ++ feat_reg
+            : [ret] "=r" (-> u64),
+        );
+    }
+};
 
 pub fn detectNativeCpuAndFeatures() ?std.Target.Cpu {
     return switch (native_arch) {
         .aarch64, .aarch64_be => b: {
             const registers = [12]u64{
-                getAArch64CpuFeature("MIDR_EL1"),
-                getAArch64CpuFeature("ID_AA64PFR0_EL1"),
-                getAArch64CpuFeature("ID_AA64PFR1_EL1"),
-                getAArch64CpuFeature("ID_AA64DFR0_EL1"),
-                getAArch64CpuFeature("ID_AA64DFR1_EL1"),
-                getAArch64CpuFeature("ID_AA64AFR0_EL1"),
-                getAArch64CpuFeature("ID_AA64AFR1_EL1"),
-                getAArch64CpuFeature("ID_AA64ISAR0_EL1"),
-                getAArch64CpuFeature("ID_AA64ISAR1_EL1"),
-                getAArch64CpuFeature("ID_AA64MMFR0_EL1"),
-                getAArch64CpuFeature("ID_AA64MMFR1_EL1"),
-                getAArch64CpuFeature("ID_AA64MMFR2_EL1"),
+                aarch64.mrs("MIDR_EL1"),
+                aarch64.mrs("ID_AA64PFR0_EL1"),
+                aarch64.mrs("ID_AA64PFR1_EL1"),
+                aarch64.mrs("ID_AA64DFR0_EL1"),
+                aarch64.mrs("ID_AA64DFR1_EL1"),
+                aarch64.mrs("ID_AA64AFR0_EL1"),
+                aarch64.mrs("ID_AA64AFR1_EL1"),
+                aarch64.mrs("ID_AA64ISAR0_EL1"),
+                aarch64.mrs("ID_AA64ISAR1_EL1"),
+                aarch64.mrs("ID_AA64MMFR0_EL1"),
+                aarch64.mrs("ID_AA64MMFR1_EL1"),
+                aarch64.mrs("ID_AA64MMFR2_EL1"),
             };
 
             break :b @import("arm.zig").aarch64.detectNativeCpuAndFeatures(native_arch, registers);
diff --git a/lib/std/zig/system/linux.zig b/lib/std/zig/system/linux.zig
index fa80dc6c382be4ac3004612dec9ab6ee130f5101..d712792bf1504d02dd1a22c6f5bcd6a1c2bd5e91 100644
--- a/lib/std/zig/system/linux.zig
+++ b/lib/std/zig/system/linux.zig
@@ -441,11 +441,13 @@ fn CpuinfoParser(comptime impl: anytype) type {
     };
 }
 
-inline fn getAArch64CpuFeature(comptime feat_reg: []const u8) u64 {
-    return asm ("mrs %[ret], " ++ feat_reg
-        : [ret] "=r" (-> u64),
-    );
-}
+const aarch64 = struct {
+    inline fn mrs(comptime feat_reg: []const u8) u64 {
+        return asm ("mrs %[ret], " ++ feat_reg
+            : [ret] "=r" (-> u64),
+        );
+    }
+};
 
 const riscv = struct {
     const linux = std.os.linux;
@@ -596,18 +598,18 @@ pub fn detectNativeCpuAndFeatures(io: Io) ?Target.Cpu {
     return switch (current_arch) {
         .aarch64, .aarch64_be => b: {
             const registers = [12]u64{
-                getAArch64CpuFeature("MIDR_EL1"),
-                getAArch64CpuFeature("ID_AA64PFR0_EL1"),
-                getAArch64CpuFeature("ID_AA64PFR1_EL1"),
-                getAArch64CpuFeature("ID_AA64DFR0_EL1"),
-                getAArch64CpuFeature("ID_AA64DFR1_EL1"),
-                getAArch64CpuFeature("ID_AA64AFR0_EL1"),
-                getAArch64CpuFeature("ID_AA64AFR1_EL1"),
-                getAArch64CpuFeature("ID_AA64ISAR0_EL1"),
-                getAArch64CpuFeature("ID_AA64ISAR1_EL1"),
-                getAArch64CpuFeature("ID_AA64MMFR0_EL1"),
-                getAArch64CpuFeature("ID_AA64MMFR1_EL1"),
-                getAArch64CpuFeature("ID_AA64MMFR2_EL1"),
+                aarch64.mrs("MIDR_EL1"),
+                aarch64.mrs("ID_AA64PFR0_EL1"),
+                aarch64.mrs("ID_AA64PFR1_EL1"),
+                aarch64.mrs("ID_AA64DFR0_EL1"),
+                aarch64.mrs("ID_AA64DFR1_EL1"),
+                aarch64.mrs("ID_AA64AFR0_EL1"),
+                aarch64.mrs("ID_AA64AFR1_EL1"),
+                aarch64.mrs("ID_AA64ISAR0_EL1"),
+                aarch64.mrs("ID_AA64ISAR1_EL1"),
+                aarch64.mrs("ID_AA64MMFR0_EL1"),
+                aarch64.mrs("ID_AA64MMFR1_EL1"),
+                aarch64.mrs("ID_AA64MMFR2_EL1"),
             };
 
             break :b @import("arm.zig").aarch64.detectNativeCpuAndFeatures(current_arch, registers);