authorgravatar for topolarity@tapscott.meCody Tapscott <topolarity@tapscott.me> 2022-10-08 11:32:32-07:00
committergravatar for topolarity@tapscott.meCody Tapscott <topolarity@tapscott.me> 2022-10-13 12:53:20-07:00
logdb9058e41a7b11fcf0c1742fc7eac8a67fab3bcf
tree6acf5ef25adc02a1528224cc9f7bbf668cd0bb80
parent6e6ae8886e6885a648918cdb006f899b40b378aa

Disable llvm.prefetch for PowerPC

This instruction is not supported on this backend, so should just be a noop.

2 files changed, 11 insertions(+), 1 deletions(-)

src/codegen/llvm.zig+7-1
...@@ -9168,7 +9168,13 @@ pub const FuncGen = struct {...@@ -9168,7 +9168,13 @@ pub const FuncGen = struct {
9168 const target = self.dg.module.getTarget();9168 const target = self.dg.module.getTarget();
9169 switch (prefetch.cache) {9169 switch (prefetch.cache) {
9170 .instruction => switch (target.cpu.arch) {9170 .instruction => switch (target.cpu.arch) {
9171 .x86_64, .i386 => return null,9171 .x86_64,
9172 .i386,
9173 .powerpc,
9174 .powerpcle,
9175 .powerpc64,
9176 .powerpc64le,
9177 => return null,
9172 .arm, .armeb, .thumb, .thumbeb => {9178 .arm, .armeb, .thumb, .thumbeb => {
9173 switch (prefetch.rw) {9179 switch (prefetch.rw) {
9174 .write => return null,9180 .write => return null,
src/stage1/codegen.cpp+4
...@@ -6742,6 +6742,10 @@ static LLVMValueRef ir_render_prefetch(CodeGen *g, Stage1Air *executable, Stage1...@@ -6742,6 +6742,10 @@ static LLVMValueRef ir_render_prefetch(CodeGen *g, Stage1Air *executable, Stage1
6742 switch (g->zig_target->arch) {6742 switch (g->zig_target->arch) {
6743 case ZigLLVM_x86:6743 case ZigLLVM_x86:
6744 case ZigLLVM_x86_64:6744 case ZigLLVM_x86_64:
6745 case ZigLLVM_ppc:
6746 case ZigLLVM_ppcle:
6747 case ZigLLVM_ppc64:
6748 case ZigLLVM_ppc64le:
6745 return nullptr;6749 return nullptr;
6746 default:6750 default:
6747 break;6751 break;