| ... | @@ -16683,36 +16683,44 @@ fn airAggregateInit(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -16683,36 +16683,44 @@ fn airAggregateInit(self: *Self, inst: Air.Inst.Index) !void { |
| 16683 | else => null, | 16683 | else => null, |
| 16684 | }; | 16684 | }; |
| 16685 | defer if (elem_lock) |lock| self.register_manager.unlockReg(lock); | 16685 | defer if (elem_lock) |lock| self.register_manager.unlockReg(lock); |
| 16686 | const elem_reg = registerAlias( | 16686 | |
| 16687 | try self.copyToTmpRegister(elem_ty, mat_elem_mcv), | | |
| 16688 | elem_abi_size, | | |
| 16689 | ); | | |
| 16690 | const elem_extra_bits = self.regExtraBits(elem_ty); | 16687 | const elem_extra_bits = self.regExtraBits(elem_ty); |
| 16691 | if (elem_bit_off < elem_extra_bits) { | 16688 | { |
| 16692 | try self.truncateRegister(elem_ty, elem_reg); | 16689 | const temp_reg = try self.copyToTmpRegister(elem_ty, mat_elem_mcv); |
| | 16690 | const temp_alias = registerAlias(temp_reg, elem_abi_size); |
| | 16691 | const temp_lock = self.register_manager.lockRegAssumeUnused(temp_reg); |
| | 16692 | defer self.register_manager.unlockReg(temp_lock); |
| | 16693 | |
| | 16694 | if (elem_bit_off < elem_extra_bits) { |
| | 16695 | try self.truncateRegister(elem_ty, temp_alias); |
| | 16696 | } |
| | 16697 | if (elem_bit_off > 0) try self.genShiftBinOpMir( |
| | 16698 | .{ ._l, .sh }, |
| | 16699 | elem_ty, |
| | 16700 | .{ .register = temp_alias }, |
| | 16701 | Type.u8, |
| | 16702 | .{ .immediate = elem_bit_off }, |
| | 16703 | ); |
| | 16704 | try self.genBinOpMir( |
| | 16705 | .{ ._, .@"or" }, |
| | 16706 | elem_ty, |
| | 16707 | .{ .load_frame = .{ .index = frame_index, .off = elem_byte_off } }, |
| | 16708 | .{ .register = temp_alias }, |
| | 16709 | ); |
| 16693 | } | 16710 | } |
| 16694 | if (elem_bit_off > 0) try self.genShiftBinOpMir( | | |
| 16695 | .{ ._l, .sh }, | | |
| 16696 | elem_ty, | | |
| 16697 | .{ .register = elem_reg }, | | |
| 16698 | Type.u8, | | |
| 16699 | .{ .immediate = elem_bit_off }, | | |
| 16700 | ); | | |
| 16701 | try self.genBinOpMir( | | |
| 16702 | .{ ._, .@"or" }, | | |
| 16703 | elem_ty, | | |
| 16704 | .{ .load_frame = .{ .index = frame_index, .off = elem_byte_off } }, | | |
| 16705 | .{ .register = elem_reg }, | | |
| 16706 | ); | | |
| 16707 | if (elem_bit_off > elem_extra_bits) { | 16711 | if (elem_bit_off > elem_extra_bits) { |
| 16708 | const reg = try self.copyToTmpRegister(elem_ty, mat_elem_mcv); | 16712 | const temp_reg = try self.copyToTmpRegister(elem_ty, mat_elem_mcv); |
| | 16713 | const temp_alias = registerAlias(temp_reg, elem_abi_size); |
| | 16714 | const temp_lock = self.register_manager.lockRegAssumeUnused(temp_reg); |
| | 16715 | defer self.register_manager.unlockReg(temp_lock); |
| | 16716 | |
| 16709 | if (elem_extra_bits > 0) { | 16717 | if (elem_extra_bits > 0) { |
| 16710 | try self.truncateRegister(elem_ty, registerAlias(reg, elem_abi_size)); | 16718 | try self.truncateRegister(elem_ty, temp_alias); |
| 16711 | } | 16719 | } |
| 16712 | try self.genShiftBinOpMir( | 16720 | try self.genShiftBinOpMir( |
| 16713 | .{ ._r, .sh }, | 16721 | .{ ._r, .sh }, |
| 16714 | elem_ty, | 16722 | elem_ty, |
| 16715 | .{ .register = reg }, | 16723 | .{ .register = temp_reg }, |
| 16716 | Type.u8, | 16724 | Type.u8, |
| 16717 | .{ .immediate = elem_abi_bits - elem_bit_off }, | 16725 | .{ .immediate = elem_abi_bits - elem_bit_off }, |
| 16718 | ); | 16726 | ); |
| ... | @@ -16723,7 +16731,7 @@ fn airAggregateInit(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -16723,7 +16731,7 @@ fn airAggregateInit(self: *Self, inst: Air.Inst.Index) !void { |
| 16723 | .index = frame_index, | 16731 | .index = frame_index, |
| 16724 | .off = elem_byte_off + @as(i32, @intCast(elem_abi_size)), | 16732 | .off = elem_byte_off + @as(i32, @intCast(elem_abi_size)), |
| 16725 | } }, | 16733 | } }, |
| 16726 | .{ .register = reg }, | 16734 | .{ .register = temp_alias }, |
| 16727 | ); | 16735 | ); |
| 16728 | } | 16736 | } |
| 16729 | } | 16737 | } |