authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-10-20 06:11:47+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-10-20 10:03:55+02:00
logde6afdc52428632c9a13b5ef14d4ba6719a2d55b
tree7f09f2d42c6cc9f2809ac5c3a871f495f67fc61c
parent50cce468cc3e98c3eef395927993e9c16f555be9
signature Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

test-c-abi: skip some vector cases on arm regardless of float ABI

These cases only worked by accident when neon was enabled. The change to the arm baseline model from neon to vfp3d16 exposed these failures.

1 files changed, 6 insertions(+), 6 deletions(-)

test/c_abi/main.zig+6-6
......@@ -5032,7 +5032,7 @@ extern fn c_vector_6_u8(@Vector(6, u8), usize) void;
50325032extern fn c_test_vector_6_u8() void;
50335033
50345034test "@Vector(6, u8)" {
5035 if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest;
5035 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
50365036 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
50375037 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
50385038 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
......@@ -5110,7 +5110,7 @@ extern fn c_vector_12_u8(@Vector(12, u8), usize) void;
51105110extern fn c_test_vector_12_u8() void;
51115111
51125112test "@Vector(12, u8)" {
5113 if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest;
5113 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
51145114 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
51155115 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
51165116
......@@ -9176,7 +9176,7 @@ extern fn c_vector_3_u16(@Vector(3, u16), usize) void;
91769176extern fn c_test_vector_3_u16() void;
91779177
91789178test "@Vector(3, u16)" {
9179 if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest;
9179 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
91809180 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
91819181 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
91829182 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
......@@ -9250,7 +9250,7 @@ extern fn c_vector_6_u16(@Vector(6, u16), usize) void;
92509250extern fn c_test_vector_6_u16() void;
92519251
92529252test "@Vector(6, u16)" {
9253 if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest;
9253 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
92549254 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
92559255 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
92569256
......@@ -11439,7 +11439,7 @@ extern fn c_vector_3_u32(@Vector(3, u32), usize) void;
1143911439extern fn c_test_vector_3_u32() void;
1144011440
1144111441test "@Vector(3, u32)" {
11442 if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest;
11442 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
1144311443 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
1144411444 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
1144511445
......@@ -13424,7 +13424,7 @@ extern fn c_vector_3_f32(@Vector(3, f32), usize) void;
1342413424extern fn c_test_vector_3_f32() void;
1342513425
1342613426test "@Vector(3, f32)" {
13427 if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest;
13427 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
1342813428 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
1342913429 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
1343013430