authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-10-17 01:59:53+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-10-26 21:59:59+02:00
loge26b64a87dd4170a46aec317e958ee617bc26e8d
treedb957d63cfbc3ed25a262c8048a3cf8a13af9c3b
parent385f586605aaf8abe303bf64f9c40209088e874e
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.Target: Use mips32r2/mips64r2 as the baseline CPU models for mips/mips64.

This matches Clang's defaults. That also means these CPU models tend to get more testing, so they're a safer baseline choice. Anecdotally, the oldest MIPS hardware that I've seen anyone run Zig on was also r2.

1 files changed, 2 insertions(+), 0 deletions(-)

lib/std/Target.zig+2
...@@ -1860,6 +1860,8 @@ pub const Cpu = struct {...@@ -1860,6 +1860,8 @@ pub const Cpu = struct {
1860 .hexagon => &hexagon.cpu.hexagonv60, // gcc/clang do not have a generic hexagon model.1860 .hexagon => &hexagon.cpu.hexagonv60, // gcc/clang do not have a generic hexagon model.
1861 .lanai => &lanai.cpu.v11, // clang does not have a generic lanai model.1861 .lanai => &lanai.cpu.v11, // clang does not have a generic lanai model.
1862 .loongarch64 => &loongarch.cpu.loongarch64,1862 .loongarch64 => &loongarch.cpu.loongarch64,
1863 .mips, .mipsel => &mips.cpu.mips32r2,
1864 .mips64, .mips64el => &mips.cpu.mips64r2,
1863 .nvptx, .nvptx64 => &nvptx.cpu.sm_52,1865 .nvptx, .nvptx64 => &nvptx.cpu.sm_52,
1864 .powerpc64le => &powerpc.cpu.ppc64le,1866 .powerpc64le => &powerpc.cpu.ppc64le,
1865 .riscv32 => &riscv.cpu.baseline_rv32,1867 .riscv32 => &riscv.cpu.baseline_rv32,