From e70584e2f87ae8daab18d9e28f72dac020d7702e Mon Sep 17 00:00:00 2001 From: David Rubin Date: Mon, 25 Mar 2024 03:52:13 -0700 Subject: [PATCH] riscv: change `load_symbol` psuedo instruction size to 8 --- src/arch/riscv64/Emit.zig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/arch/riscv64/Emit.zig b/src/arch/riscv64/Emit.zig index b2e97041cbdadaa2db83017db66a88d0710b87de..d85629ad4b59b18fcce6c2a140e99d29ac94cf41 100644 --- a/src/arch/riscv64/Emit.zig +++ b/src/arch/riscv64/Emit.zig @@ -517,6 +517,7 @@ fn instructionSize(emit: *Emit, inst: Mir.Inst.Index) usize { .cmp_eq, .cmp_imm_eq, .cmp_gte, + .load_symbol, => 8, else => 4, -- 2.54.0