diff --git a/lib/compiler_rt/atomics.zig b/lib/compiler_rt/atomics.zig index 83b978a11ca2fad3dc2e4f8483556751c2f6e3d1..8b7861537a06cc8c9c9075f3faba1bba9488a709 100644 --- a/lib/compiler_rt/atomics.zig +++ b/lib/compiler_rt/atomics.zig @@ -13,7 +13,7 @@ const symbol = compiler_rt.symbol; // detail to keep the export logic clean and because we need some kind of CAS to // implement the spinlocks. const supports_atomic_ops = switch (arch) { - .msp430, .avr, .bpfel, .bpfeb => false, + .msp430, .avr, .bpfel, .bpfeb, .lanai => false, .arm, .armeb, .thumb, .thumbeb => // The ARM v6m ISA has no ldrex/strex and so it's impossible to do CAS // operations (unless we're targeting Linux, the kernel provides a way to diff --git a/lib/std/Target.zig b/lib/std/Target.zig index 4eaa95613af97fe2c46bae86a70f5ac19ef2e5e5..0a5e00930a19e05f99654a34b4a7b3214b8f2c8f 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -2069,10 +2069,12 @@ pub const Cpu = struct { .riscv64, .riscv64be => &riscv.cpu.generic_rv64, .sparc => &sparc.cpu.v7, .sparc64 => &sparc.cpu.v9, // SPARC can only be 64-bit from v9 and up. + .ve => &ve.cpu.ve10, .wasm32, .wasm64 => &wasm.cpu.mvp, .x86_16 => &x86.cpu.i86, .x86 => &x86.cpu.i386, .x86_64 => &x86.cpu.x86_64, + .xcore => &xcore.cpu.xs1b, inline else => |a| &@field(Target, @tagName(a.family())).cpu.generic, }; } @@ -2087,16 +2089,16 @@ pub const Cpu = struct { /// `Os.Tag.freestanding`. pub fn baseline(arch: Arch, os: Os) *const Model { return switch (arch) { - .alpha => &alpha.cpu.ev6, + .alpha => &alpha.cpu.ev56, .amdgcn => &amdgcn.cpu.gfx906, .arm => switch (os.tag) { .@"3ds" => &arm.cpu.mpcore, - .vita => &arm.cpu.cortex_a9, + .vita => &arm.cpu.kermit, .gba => &arm.cpu.arm7tdmi, else => &arm.cpu.baseline, }, .thumb => switch (os.tag) { - .vita => &arm.cpu.cortex_a9, + .vita => &arm.cpu.kermit, .gba => &arm.cpu.arm7tdmi, else => &arm.cpu.baseline, }, @@ -2114,8 +2116,7 @@ pub const Cpu = struct { .bpfel, .bpfeb => &bpf.cpu.v3, .csky => &csky.cpu.ck810, // gcc/clang do not have a generic csky model. .hexagon => &hexagon.cpu.hexagonv68, // gcc/clang do not have a generic hexagon model. - .hppa => &hppa.cpu.pa_7300lc, - .kvx => &kvx.cpu.coolidge_v2, + .hppa => &hppa.cpu.pa_7000, .lanai => &lanai.cpu.v11, // clang does not have a generic lanai model. .loongarch32 => &loongarch.cpu.la32v1_0, .loongarch64 => &loongarch.cpu.la64v1_0, @@ -2160,7 +2161,6 @@ pub const Cpu = struct { .ps5 => &x86.cpu.znver2, else => generic(arch), }, - .xcore => &xcore.cpu.xs1b_generic, .xtensa => &xtensa.cpu.esp32, .wasm32, .wasm64 => &wasm.cpu.lime1, @@ -2599,6 +2599,16 @@ pub const DynamicLinker = struct { if (ptrBitWidth_cpu_abi(cpu, abi) == 64) "64" else "", }) else none, + else => none, + } + else if (abi.isOpenHarmony()) + switch (cpu.arch) { + .aarch64, + .x86_64, + => |arch| if (abi == .ohos) initFmt("/lib/ld-musl-{s}.so.1", .{@tagName(arch)}) else none, + + .arm => if (abi == .ohoseabi) init("/lib/ld-musl-arm.so.1") else none, + else => none, } else if (abi.isMusl()) @@ -2750,7 +2760,6 @@ pub const DynamicLinker = struct { }, }), - .hppa, .m68k, .microblaze, .microblazeel, @@ -2780,7 +2789,9 @@ pub const DynamicLinker = struct { if (cpu.has(.mips, .nan2008)) "-linux-mipsn8" else "", }), - .powerpc => switch (abi) { + .hppa, + .powerpc, + => switch (abi) { .gnueabi, .gnueabihf, => init("/lib/ld.so.1"), @@ -3058,14 +3069,17 @@ pub fn ptrBitWidth(target: *const Target) u16 { pub fn stackAlignment(target: *const Target) u16 { // Overrides for when the stack alignment is not equal to the pointer width. switch (target.cpu.arch) { - .ez80 => return 1, + .avr, + .ez80, + => return 1, - .m68k => return 2, + .m68k => if (target.os.tag != .netbsd) return 2, .amdgcn => return 4, .arm, .armeb, + .hexagon, .hppa, .lanai, .mips, @@ -3083,28 +3097,34 @@ pub fn stackAlignment(target: *const Target) u16 { .hppa64, .loongarch32, .loongarch64, + .m88k, .mips64, .mips64el, + .powerpc, + .powerpcle, + .powerpc64, + .powerpc64le, .sparc64, .ve, .wasm32, .wasm64, .x86_64, + .xtensa, + .xtensaeb, => return 16, - // Some of the following prongs should really be testing the ABI, but our current `Abi` enum - // can't handle that level of nuance yet. - .powerpc64, - .powerpc64le, - => if (target.os.tag == .linux) return 16, - .riscv32, .riscv32be, .riscv64, .riscv64be, => if (!target.cpu.has(.riscv, .e)) return 16, - .x86 => if (target.os.tag != .windows and target.os.tag != .uefi) return 16, + .x86 => switch (target.os.tag) { + .hurd, + .linux, + => return 16, + else => {}, + }, .kvx => return 32, @@ -3160,6 +3180,7 @@ pub fn cCharSignedness(target: *const Target) ?std.builtin.Signedness { .powerpcle, .powerpc64, .powerpc64le, + .propeller, .s390x, .riscv32, .riscv32be, @@ -3223,6 +3244,7 @@ pub fn cTypeBitSize(target: *const Target, c_type: CType) ?u16 { .freestanding, .other, .ashetos, + .tios, => switch (target.cpu.arch) { .msp430, .x86_16, @@ -3245,6 +3267,13 @@ pub fn cTypeBitSize(target: *const Target, c_type: CType) ?u16 { .long, .ulong, .float => 32, .double, .longdouble, .longlong, .ulonglong => 64, }, + .ez80 => switch (c_type) { + .char => 8, + .short, .ushort => 16, + .int, .uint => 24, + .long, .ulong, .float, .double => 32, + .longlong, .ulonglong, .longdouble => 64, + }, else => switch (c_type) { .char => 8, .short, .ushort => 16, @@ -3302,88 +3331,73 @@ pub fn cTypeBitSize(target: *const Target, c_type: CType) ?u16 { .wasi, .emscripten, - => switch (target.cpu.arch) { - .mips64, - .mips64el, - => switch (c_type) { - .char => 8, - .short, .ushort => 16, - .int, .uint, .float => 32, - .long, .ulong => switch (target.abi) { - .gnuabin32, .muslabin32, .abin32 => 32, - else => 64, - }, - .longlong, .ulonglong, .double => 64, - .longdouble => 128, + => switch (c_type) { + .char => 8, + .short, .ushort => 16, + .int, .uint, .float => 32, + .long, .ulong => switch (target.os.tag) { + .plan9 => 32, // This is certainly A Choice. + else => target.ptrBitWidth(), }, - .x86_64 => switch (c_type) { - .char => 8, - .short, .ushort => 16, - .int, .uint, .float => 32, - .long, .ulong => switch (target.abi) { - .gnux32, .muslx32, .x32 => 32, - else => 64, + .longlong, .ulonglong, .double => 64, + .longdouble => switch (target.cpu.arch) { + .x86, + .x86_64, + => switch (target.abi) { + .android, .ohos => 64, + else => 80, }, - .longlong, .ulonglong, .double => 64, - .longdouble => 80, - }, - else => switch (c_type) { - .char => 8, - .short, .ushort => 16, - .int, .uint, .float => 32, - .long, .ulong => target.ptrBitWidth(), - .longlong, .ulonglong, .double => 64, - .longdouble => switch (target.cpu.arch) { - .x86 => switch (target.abi) { - .android => 64, - else => 80, - }, - .powerpc, - .powerpcle, - => switch (target.abi) { - .musleabi, .musleabihf => 64, - else => switch (target.os.tag) { - .netbsd, - .openbsd, - => 64, - else => 128, - }, + .powerpc, + .powerpcle, + => switch (target.abi) { + .musleabi, .musleabihf => 64, + else => switch (target.os.tag) { + .netbsd, + .openbsd, + => 64, + else => 128, }, + }, - .powerpc64, - .powerpc64le, - => switch (target.abi) { - .musl => 64, - else => switch (target.os.tag) { - .freebsd, - .openbsd, - => 64, - else => 128, - }, + .powerpc64, + .powerpc64le, + => switch (target.abi) { + .musl => 64, + else => switch (target.os.tag) { + .freebsd, + .openbsd, + => 64, + else => 128, }, + }, - .alpha, - .riscv32, - .riscv32be, - .riscv64, - .riscv64be, - .aarch64, - .aarch64_be, - .s390x, - .mips64, - .mips64el, - .sparc, - .sparc64, - .wasm32, - .wasm64, - .loongarch32, - .loongarch64, - .ve, - => 128, - - else => 64, + .alpha => switch (target.os.tag) { + .netbsd, + .openbsd, + => 64, + else => 128, }, + + .riscv32, + .riscv32be, + .riscv64, + .riscv64be, + .aarch64, + .aarch64_be, + .s390x, + .mips64, + .mips64el, + .sparc, + .sparc64, + .wasm32, + .wasm64, + .loongarch32, + .loongarch64, + .ve, + => 128, + + else => 64, }, }, @@ -3481,14 +3495,6 @@ pub fn cTypeBitSize(target: *const Target, c_type: CType) ?u16 { .longdouble => 80, }, - .tios => switch (c_type) { - .char => 8, - .short, .ushort => 16, - .int, .uint => 24, - .long, .ulong, .float, .double => 32, - .longlong, .ulonglong, .longdouble => 64, - }, - .opengl => null, }; } @@ -3739,7 +3745,10 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention .lanai => .{ .lanai_sysv = .{} }, .loongarch64 => .{ .loongarch64_lp64 = .{} }, .loongarch32 => .{ .loongarch32_ilp32 = .{} }, - .m68k => .{ .m68k_gnu = .{} }, + .m68k => switch (target.os.tag) { + .netbsd => .{ .m68k_sysv = .{} }, + else => .{ .m68k_gnu = .{} }, + }, .m88k => .{ .m88k_sysv = .{} }, .microblaze, .microblazeel => .{ .microblaze_std = .{} }, .msp430 => .{ .msp430_eabi = .{} }, @@ -3749,7 +3758,10 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention .sh, .sheb => .{ .sh_gnu = .{} }, .ve => .{ .ve_sysv = .{} }, .xcore => .{ .xcore_xs1 = .{} }, - .xtensa, .xtensaeb => .{ .xtensa_call0 = .{} }, + .xtensa, .xtensaeb => switch (target.abi) { + .call0 => .{ .xtensa_call0 = .{} }, + else => .{ .xtensa_windowed = .{} }, + }, .amdgcn => .{ .amdgcn_device = .{} }, .nvptx, .nvptx64 => .nvptx_device, .spirv32, .spirv64 => .spirv_device, diff --git a/lib/std/Target/alpha.zig b/lib/std/Target/alpha.zig index 77ae33b0c419342d5d7645a850691f02f49db991..29153424e93d815325af3b6ee3d1d2b72db0a690 100644 --- a/lib/std/Target/alpha.zig +++ b/lib/std/Target/alpha.zig @@ -32,7 +32,7 @@ pub const all_features = blk: { }; result[@backingInt(Feature.fix)] = .{ .llvm_name = null, - .description = "Enable floating point move and square root extensions", + .description = "Enable FPR-to-GPR move and square root extensions", .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.max)] = .{ diff --git a/lib/std/Target/arm.zig b/lib/std/Target/arm.zig index bcad2d76384d46138448d6e2616cc2d331a3d965..9d7810b7dbbcd9527868ecacb82a7f89040ef260 100644 --- a/lib/std/Target/arm.zig +++ b/lib/std/Target/arm.zig @@ -1200,7 +1200,6 @@ pub const all_features = blk: { .db, .dsp, .has_v7, - .neon, .perfmon, }), }; @@ -1250,7 +1249,6 @@ pub const all_features = blk: { .dsp, .has_v7, .mp, - .neon, .perfmon, .trustzone, .virtualization, @@ -1262,12 +1260,12 @@ pub const all_features = blk: { .dependencies = featureSet(&[_]Feature{ .aclass, .crc, - .crypto, .db, .dsp, .fp_armv8, .has_v8_1a, .mp, + .neon, .trustzone, .virtualization, }), @@ -1276,7 +1274,6 @@ pub const all_features = blk: { .llvm_name = "armv8.1-m.main", .description = "ARMv81mMainline architecture", .dependencies = featureSet(&[_]Feature{ - .@"8msecext", .acquire_release, .db, .has_v8_1m_main, @@ -1294,12 +1291,12 @@ pub const all_features = blk: { .dependencies = featureSet(&[_]Feature{ .aclass, .crc, - .crypto, .db, .dsp, .fp_armv8, .has_v8_2a, .mp, + .neon, .ras, .trustzone, .virtualization, @@ -1311,12 +1308,12 @@ pub const all_features = blk: { .dependencies = featureSet(&[_]Feature{ .aclass, .crc, - .crypto, .db, .dsp, .fp_armv8, .has_v8_3a, .mp, + .neon, .ras, .trustzone, .virtualization, @@ -1328,7 +1325,6 @@ pub const all_features = blk: { .dependencies = featureSet(&[_]Feature{ .aclass, .crc, - .crypto, .db, .dsp, .fp_armv8, @@ -1345,7 +1341,6 @@ pub const all_features = blk: { .dependencies = featureSet(&[_]Feature{ .aclass, .crc, - .crypto, .db, .dsp, .fp_armv8, @@ -1362,7 +1357,6 @@ pub const all_features = blk: { .dependencies = featureSet(&[_]Feature{ .aclass, .crc, - .crypto, .db, .dsp, .fp_armv8, @@ -1379,7 +1373,6 @@ pub const all_features = blk: { .dependencies = featureSet(&[_]Feature{ .aclass, .crc, - .crypto, .db, .dsp, .fp_armv8, @@ -1396,7 +1389,6 @@ pub const all_features = blk: { .dependencies = featureSet(&[_]Feature{ .aclass, .crc, - .crypto, .db, .dsp, .fp_armv8, @@ -1413,7 +1405,6 @@ pub const all_features = blk: { .dependencies = featureSet(&[_]Feature{ .aclass, .crc, - .crypto, .db, .dsp, .fp_armv8, @@ -1430,12 +1421,12 @@ pub const all_features = blk: { .dependencies = featureSet(&[_]Feature{ .aclass, .crc, - .crypto, .db, .dsp, .fp_armv8, .has_v8, .mp, + .neon, .trustzone, .virtualization, }), @@ -1444,7 +1435,6 @@ pub const all_features = blk: { .llvm_name = "armv8-m.base", .description = "ARMv8mBaseline architecture", .dependencies = featureSet(&[_]Feature{ - .@"8msecext", .acquire_release, .db, .has_v7clrex, @@ -1460,7 +1450,6 @@ pub const all_features = blk: { .llvm_name = "armv8-m.main", .description = "ARMv8mMainline architecture", .dependencies = featureSet(&[_]Feature{ - .@"8msecext", .acquire_release, .db, .has_v8m_main, @@ -1523,7 +1512,6 @@ pub const all_features = blk: { .dependencies = featureSet(&[_]Feature{ .aclass, .crc, - .crypto, .db, .dsp, .fp_armv8, @@ -1949,6 +1937,7 @@ pub const cpu = struct { .llvm_name = "generic", .features = featureSet(&[_]Feature{ .v7a, + .vfp3d16, }), }; pub const cortex_a12: CpuModel = .{ @@ -1960,7 +1949,6 @@ pub const cpu = struct { .ret_addr_stack, .trustzone, .v7a, - .vfp4, .virtualization, .vmlx_forwarding, }), @@ -1976,7 +1964,6 @@ pub const cpu = struct { .splat_vfp_neon, .trustzone, .v7a, - .vfp4, .virtualization, .vldn_align, }), @@ -1990,7 +1977,6 @@ pub const cpu = struct { .ret_addr_stack, .trustzone, .v7a, - .vfp4, .virtualization, .vmlx_forwarding, }), @@ -2020,7 +2006,6 @@ pub const cpu = struct { .slowfpvmlx, .trustzone, .v7a, - .vfp4, .vmlx_forwarding, }), }; @@ -2072,7 +2057,6 @@ pub const cpu = struct { .slowfpvmlx, .trustzone, .v7a, - .vfp4, .virtualization, .vmlx_forwarding, .vmlx_hazards, @@ -2186,7 +2170,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .avoid_partial_cpsr, .expand_fp_mlx, - .fp16, .mp, .muxed_units, .neon_fpmovs, @@ -2285,12 +2268,10 @@ pub const cpu = struct { .name = "cortex_m52", .llvm_name = "cortex-m52", .features = featureSet(&[_]Feature{ - .fp_armv8d16, + .dsp, .loop_align, .mve1beat, - .mve_fp, .no_branch_predictor, - .pacbti, .slowfpvmlx, .use_misched, .v8_1m_main, @@ -2324,6 +2305,7 @@ pub const cpu = struct { .name = "cortex_m85", .llvm_name = "cortex-m85", .features = featureSet(&[_]Feature{ + .@"8msecext", .branch_align_64, .dsp, .m85, @@ -2364,16 +2346,13 @@ pub const cpu = struct { .slowfpvfmx, .slowfpvmlx, .v7r, - .vfp3d16, }), }; pub const cortex_r52: CpuModel = .{ .name = "cortex_r52", .llvm_name = "cortex-r52", .features = featureSet(&[_]Feature{ - .fp_armv8, .fpao, - .neon, .use_misched, .v8r, }), @@ -2382,9 +2361,7 @@ pub const cpu = struct { .name = "cortex_r52plus", .llvm_name = "cortex-r52plus", .features = featureSet(&[_]Feature{ - .fp_armv8, .fpao, - .neon, .use_misched, .v8r, }), @@ -2394,7 +2371,6 @@ pub const cpu = struct { .llvm_name = "cortex-r7", .features = featureSet(&[_]Feature{ .avoid_partial_cpsr, - .fp16, .hwdiv_arm, .mp, .ret_addr_stack, @@ -2402,7 +2378,6 @@ pub const cpu = struct { .slowfpvfmx, .slowfpvmlx, .v7r, - .vfp3d16, }), }; pub const cortex_r8: CpuModel = .{ @@ -2410,7 +2385,6 @@ pub const cpu = struct { .llvm_name = "cortex-r8", .features = featureSet(&[_]Feature{ .avoid_partial_cpsr, - .fp16, .hwdiv_arm, .mp, .ret_addr_stack, @@ -2418,7 +2392,6 @@ pub const cpu = struct { .slowfpvfmx, .slowfpvmlx, .v7r, - .vfp3d16, }), }; pub const cortex_x1: CpuModel = .{ @@ -2445,6 +2418,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .avoid_movs_shop, .avoid_partial_cpsr, + .crypto, .disable_postra_scheduler, .neonfp, .ret_addr_stack, @@ -2466,6 +2440,7 @@ pub const cpu = struct { .name = "exynos_m1", .llvm_name = null, .features = featureSet(&[_]Feature{ + .crypto, .expand_fp_mlx, .fuse_aes, .fuse_literals, @@ -2486,6 +2461,7 @@ pub const cpu = struct { .name = "exynos_m2", .llvm_name = null, .features = featureSet(&[_]Feature{ + .crypto, .expand_fp_mlx, .fuse_aes, .fuse_literals, @@ -2506,6 +2482,7 @@ pub const cpu = struct { .name = "exynos_m3", .llvm_name = "exynos-m3", .features = featureSet(&[_]Feature{ + .crypto, .expand_fp_mlx, .fuse_aes, .fuse_literals, @@ -2526,6 +2503,7 @@ pub const cpu = struct { .name = "exynos_m4", .llvm_name = "exynos-m4", .features = featureSet(&[_]Feature{ + .crypto, .dotprod, .expand_fp_mlx, .fullfp16, @@ -2548,6 +2526,7 @@ pub const cpu = struct { .name = "exynos_m5", .llvm_name = "exynos-m5", .features = featureSet(&[_]Feature{ + .crypto, .dotprod, .expand_fp_mlx, .fullfp16, @@ -2578,6 +2557,26 @@ pub const cpu = struct { .v5te, }), }; + pub const kermit: CpuModel = .{ + .name = "kermit", + .llvm_name = "cortex-a9", + .features = featureSet(&[_]Feature{ + .avoid_partial_cpsr, + .expand_fp_mlx, + .fp16, + .mp, + .muxed_units, + .neon, + .neon_fpmovs, + .prefer_vmovsr, + .ret_addr_stack, + .trustzone, + .v7a, + .vldn_align, + .vmlx_forwarding, + .vmlx_hazards, + }), + }; pub const krait: CpuModel = .{ .name = "krait", .llvm_name = "krait", @@ -2586,6 +2585,7 @@ pub const cpu = struct { .hwdiv, .hwdiv_arm, .muxed_units, + .neon, .ret_addr_stack, .v7a, .vfp4, @@ -2597,6 +2597,7 @@ pub const cpu = struct { .name = "kryo", .llvm_name = "kryo", .features = featureSet(&[_]Feature{ + .crypto, .v8a, }), }; @@ -2666,9 +2667,7 @@ pub const cpu = struct { .llvm_name = "star-mc1", .features = featureSet(&[_]Feature{ .avoid_muls, - .dsp, .fix_cmse_cve_2021_35465, - .fp_armv8d16sp, .loop_align, .no_branch_predictor, .slowfpvfmx, @@ -2681,12 +2680,10 @@ pub const cpu = struct { .name = "star_mc3", .llvm_name = "star-mc3", .features = featureSet(&[_]Feature{ - .fp_armv8d16, + .dsp, .loop_align, .mve1beat, - .mve_fp, .no_branch_predictor, - .pacbti, .slowfpvmlx, .use_misched, .v8_1m_main, @@ -2730,6 +2727,7 @@ pub const cpu = struct { .hwdiv, .hwdiv_arm, .mp, + .neon, .neonfp, .prefer_ishst, .prof_unpr, diff --git a/lib/std/Target/bpf.zig b/lib/std/Target/bpf.zig index f55ebf8b01ef0ae8947914c8ee53c47847bcfd49..9251304a312f2158f4b2cb5955c07ebc853af3ac 100644 --- a/lib/std/Target/bpf.zig +++ b/lib/std/Target/bpf.zig @@ -7,8 +7,6 @@ const CpuModel = std.Target.Cpu.Model; pub const Feature = enum { allows_misaligned_mem_access, alu32, - dummy, - dwarfris, }; pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet; @@ -30,16 +28,6 @@ pub const all_features = blk: { .description = "Enable ALU32 instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.dummy)] = .{ - .llvm_name = "dummy", - .description = "unused feature", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.dwarfris)] = .{ - .llvm_name = "dwarfris", - .description = "Disable MCAsmInfo DwarfUsesRelocationsAcrossSections", - .dependencies = featureSet(&[_]Feature{}), - }; const ti = @typeInfo(Feature); for (&result, 0..) |*elem, i| { elem.index = i; diff --git a/lib/std/Target/csky.zig b/lib/std/Target/csky.zig index 913d22c06df9c93a755fd9d4ecf6984370933fbd..505707887869b7eb9d7fe0fdae81e42804d879e4 100644 --- a/lib/std/Target/csky.zig +++ b/lib/std/Target/csky.zig @@ -14,19 +14,6 @@ pub const Feature = enum { @"7e10", btst16, cache, - ccrt, - ck801, - ck802, - ck803, - ck803s, - ck804, - ck805, - ck807, - ck810, - ck810v, - ck860, - ck860v, - constpool, doloop, dsp1e2, dsp_silan, @@ -57,10 +44,6 @@ pub const Feature = enum { java, mp, mp1e2, - multiple_stld, - nvic, - pushpop, - smart, soft_tp, stack_size, trust, @@ -137,71 +120,6 @@ pub const all_features = blk: { .description = "Enable cache", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.ccrt)] = .{ - .llvm_name = "ccrt", - .description = "Use CSKY compiler runtime", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.ck801)] = .{ - .llvm_name = "ck801", - .description = "CSKY ck801 processors", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.ck802)] = .{ - .llvm_name = "ck802", - .description = "CSKY ck802 processors", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.ck803)] = .{ - .llvm_name = "ck803", - .description = "CSKY ck803 processors", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.ck803s)] = .{ - .llvm_name = "ck803s", - .description = "CSKY ck803s processors", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.ck804)] = .{ - .llvm_name = "ck804", - .description = "CSKY ck804 processors", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.ck805)] = .{ - .llvm_name = "ck805", - .description = "CSKY ck805 processors", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.ck807)] = .{ - .llvm_name = "ck807", - .description = "CSKY ck807 processors", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.ck810)] = .{ - .llvm_name = "ck810", - .description = "CSKY ck810 processors", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.ck810v)] = .{ - .llvm_name = "ck810v", - .description = "CSKY ck810v processors", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.ck860)] = .{ - .llvm_name = "ck860", - .description = "CSKY ck860 processors", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.ck860v)] = .{ - .llvm_name = "ck860v", - .description = "CSKY ck860v processors", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.constpool)] = .{ - .llvm_name = "constpool", - .description = "Dump the constant pool by compiler", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.doloop)] = .{ .llvm_name = "doloop", .description = "Enable doloop instructions", @@ -360,26 +278,6 @@ pub const all_features = blk: { .@"3e7", }), }; - result[@backingInt(Feature.multiple_stld)] = .{ - .llvm_name = "multiple_stld", - .description = "Enable multiple load/store instructions", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.nvic)] = .{ - .llvm_name = "nvic", - .description = "Enable NVIC", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.pushpop)] = .{ - .llvm_name = "pushpop", - .description = "Enable push/pop instructions", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.smart)] = .{ - .llvm_name = "smart", - .description = "Let CPU work in Smart Mode", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.soft_tp)] = .{ .llvm_name = "soft-tp", .description = "Disable TLS Pointer register", @@ -429,7 +327,6 @@ pub const cpu = struct { .llvm_name = "c807", .features = featureSet(&[_]Feature{ .cache, - .ck807, .dsp1e2, .dspe60, .edsp, @@ -438,7 +335,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, }), }; @@ -447,7 +343,6 @@ pub const cpu = struct { .llvm_name = "c807f", .features = featureSet(&[_]Feature{ .cache, - .ck807, .dsp1e2, .dspe60, .edsp, @@ -463,7 +358,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, }), }; @@ -473,7 +367,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"7e10", .cache, - .ck810, .dsp1e2, .dspe60, .edsp, @@ -487,7 +380,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, }), }; @@ -497,7 +389,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"7e10", .cache, - .ck810, .dsp1e2, .dspe60, .edsp, @@ -511,7 +402,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, }), }; @@ -521,8 +411,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"7e10", .cache, - .ck810, - .ck810v, .dsp1e2, .dspe60, .edsp, @@ -536,7 +424,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, .vdspv1, }), @@ -547,8 +434,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"7e10", .cache, - .ck810, - .ck810v, .dsp1e2, .dspe60, .edsp, @@ -562,7 +447,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, .vdspv1, }), @@ -576,7 +460,6 @@ pub const cpu = struct { .@"3e3r3", .btst16, .cache, - .ck860, .dspe60, .float7e60, .fpuv3_df, @@ -588,7 +471,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, }), }; @@ -601,8 +483,6 @@ pub const cpu = struct { .@"3e3r3", .btst16, .cache, - .ck860, - .ck860v, .dspe60, .float7e60, .fpuv3_df, @@ -614,7 +494,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, .vdsp2e60f, .vdspv2, @@ -625,7 +504,6 @@ pub const cpu = struct { .llvm_name = "ck801", .features = featureSet(&[_]Feature{ .btst16, - .ck801, .e1, .trust, }), @@ -635,7 +513,6 @@ pub const cpu = struct { .llvm_name = "ck801t", .features = featureSet(&[_]Feature{ .btst16, - .ck801, .e1, .trust, }), @@ -645,9 +522,7 @@ pub const cpu = struct { .llvm_name = "ck802", .features = featureSet(&[_]Feature{ .btst16, - .ck802, .e2, - .nvic, .trust, }), }; @@ -656,10 +531,8 @@ pub const cpu = struct { .llvm_name = "ck802j", .features = featureSet(&[_]Feature{ .btst16, - .ck802, .e2, .java, - .nvic, .trust, }), }; @@ -668,9 +541,7 @@ pub const cpu = struct { .llvm_name = "ck802t", .features = featureSet(&[_]Feature{ .btst16, - .ck802, .e2, - .nvic, .trust, }), }; @@ -679,10 +550,8 @@ pub const cpu = struct { .llvm_name = "ck803", .features = featureSet(&[_]Feature{ .btst16, - .ck803, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -691,13 +560,11 @@ pub const cpu = struct { .llvm_name = "ck803e", .features = featureSet(&[_]Feature{ .btst16, - .ck803, .dsp1e2, .dspe60, .edsp, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -706,7 +573,6 @@ pub const cpu = struct { .llvm_name = "ck803ef", .features = featureSet(&[_]Feature{ .btst16, - .ck803, .dsp1e2, .dspe60, .edsp, @@ -715,7 +581,6 @@ pub const cpu = struct { .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -724,7 +589,6 @@ pub const cpu = struct { .llvm_name = "ck803efh", .features = featureSet(&[_]Feature{ .btst16, - .ck803, .dsp1e2, .dspe60, .edsp, @@ -733,7 +597,6 @@ pub const cpu = struct { .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -743,7 +606,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"3e3r1", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -754,7 +616,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -765,7 +626,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -776,7 +636,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -787,7 +646,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -798,7 +656,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -807,7 +664,6 @@ pub const cpu = struct { .llvm_name = "ck803efht", .features = featureSet(&[_]Feature{ .btst16, - .ck803, .dsp1e2, .dspe60, .edsp, @@ -816,7 +672,6 @@ pub const cpu = struct { .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -826,7 +681,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"3e3r1", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -837,7 +691,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -848,7 +701,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -859,7 +711,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -870,7 +721,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -881,7 +731,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -891,7 +740,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"3e3r1", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -902,7 +750,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -913,7 +760,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -924,7 +770,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -935,7 +780,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -946,7 +790,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -955,7 +798,6 @@ pub const cpu = struct { .llvm_name = "ck803eft", .features = featureSet(&[_]Feature{ .btst16, - .ck803, .dsp1e2, .dspe60, .edsp, @@ -964,7 +806,6 @@ pub const cpu = struct { .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -974,7 +815,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"3e3r1", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -985,7 +825,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -996,7 +835,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -1007,7 +845,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1018,7 +855,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -1029,7 +865,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1038,13 +873,11 @@ pub const cpu = struct { .llvm_name = "ck803eh", .features = featureSet(&[_]Feature{ .btst16, - .ck803, .dsp1e2, .dspe60, .edsp, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1055,7 +888,6 @@ pub const cpu = struct { .@"3e3r1", .@"3e3r3", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -1063,7 +895,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1074,7 +905,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -1082,7 +912,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1093,7 +922,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -1101,7 +929,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1110,13 +937,11 @@ pub const cpu = struct { .llvm_name = "ck803eht", .features = featureSet(&[_]Feature{ .btst16, - .ck803, .dsp1e2, .dspe60, .edsp, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1127,7 +952,6 @@ pub const cpu = struct { .@"3e3r1", .@"3e3r3", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -1135,7 +959,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1146,7 +969,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -1154,7 +976,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1165,7 +986,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -1173,7 +993,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1184,7 +1003,6 @@ pub const cpu = struct { .@"3e3r1", .@"3e3r3", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -1192,7 +1010,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1203,7 +1020,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -1211,7 +1027,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1222,7 +1037,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -1230,7 +1044,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1239,13 +1052,11 @@ pub const cpu = struct { .llvm_name = "ck803et", .features = featureSet(&[_]Feature{ .btst16, - .ck803, .dsp1e2, .dspe60, .edsp, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1256,7 +1067,6 @@ pub const cpu = struct { .@"3e3r1", .@"3e3r3", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -1264,7 +1074,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1275,7 +1084,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -1283,7 +1091,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1294,7 +1101,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dsp1e2, .dspe60, .dspv2, @@ -1302,7 +1108,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1311,13 +1116,11 @@ pub const cpu = struct { .llvm_name = "ck803f", .features = featureSet(&[_]Feature{ .btst16, - .ck803, .float1e3, .floate1, .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1326,13 +1129,11 @@ pub const cpu = struct { .llvm_name = "ck803fh", .features = featureSet(&[_]Feature{ .btst16, - .ck803, .float1e3, .floate1, .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1343,14 +1144,12 @@ pub const cpu = struct { .@"3e3r1", .@"3e3r3", .btst16, - .ck803, .dspv2, .float1e3, .floate1, .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1361,14 +1160,12 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dspv2, .float1e3, .floate1, .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1379,14 +1176,12 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dspv2, .float1e3, .floate1, .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1397,14 +1192,12 @@ pub const cpu = struct { .@"3e3r1", .@"3e3r3", .btst16, - .ck803, .dspv2, .float1e3, .floate1, .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1415,14 +1208,12 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dspv2, .float1e3, .floate1, .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1433,14 +1224,12 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dspv2, .float1e3, .floate1, .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1449,13 +1238,11 @@ pub const cpu = struct { .llvm_name = "ck803ft", .features = featureSet(&[_]Feature{ .btst16, - .ck803, .float1e3, .floate1, .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1465,14 +1252,12 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"3e3r1", .btst16, - .ck803, .dspv2, .float1e3, .floate1, .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1483,14 +1268,12 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dspv2, .float1e3, .floate1, .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1501,14 +1284,12 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dspv2, .float1e3, .floate1, .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1517,10 +1298,8 @@ pub const cpu = struct { .llvm_name = "ck803h", .features = featureSet(&[_]Feature{ .btst16, - .ck803, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1531,11 +1310,9 @@ pub const cpu = struct { .@"3e3r1", .@"3e3r3", .btst16, - .ck803, .dspv2, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1546,11 +1323,9 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dspv2, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1561,11 +1336,9 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dspv2, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1574,10 +1347,8 @@ pub const cpu = struct { .llvm_name = "ck803ht", .features = featureSet(&[_]Feature{ .btst16, - .ck803, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1588,11 +1359,9 @@ pub const cpu = struct { .@"3e3r1", .@"3e3r3", .btst16, - .ck803, .dspv2, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1603,11 +1372,9 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dspv2, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1618,11 +1385,9 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dspv2, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1633,11 +1398,9 @@ pub const cpu = struct { .@"3e3r1", .@"3e3r3", .btst16, - .ck803, .dspv2, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1648,11 +1411,9 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dspv2, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1663,11 +1424,9 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dspv2, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1677,11 +1436,8 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"3e3r1", .btst16, - .ck803, - .ck803s, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1691,14 +1447,11 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"3e3r1", .btst16, - .ck803, - .ck803s, .dsp1e2, .dspe60, .edsp, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1708,8 +1461,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"3e3r1", .btst16, - .ck803, - .ck803s, .dsp1e2, .dspe60, .edsp, @@ -1718,7 +1469,6 @@ pub const cpu = struct { .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1728,8 +1478,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"3e3r1", .btst16, - .ck803, - .ck803s, .dsp1e2, .dsp_silan, .dspe60, @@ -1739,7 +1487,6 @@ pub const cpu = struct { .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1749,8 +1496,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"3e3r1", .btst16, - .ck803, - .ck803s, .dsp1e2, .dsp_silan, .dspe60, @@ -1760,7 +1505,6 @@ pub const cpu = struct { .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1770,8 +1514,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"3e3r1", .btst16, - .ck803, - .ck803s, .dsp1e2, .dspe60, .edsp, @@ -1780,7 +1522,6 @@ pub const cpu = struct { .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1790,15 +1531,12 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"3e3r1", .btst16, - .ck803, - .ck803s, .dsp1e2, .dsp_silan, .dspe60, .edsp, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1808,14 +1546,11 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"3e3r1", .btst16, - .ck803, - .ck803s, .float1e3, .floate1, .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1825,15 +1560,12 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"3e3r1", .btst16, - .ck803, - .ck803s, .dsp_silan, .float1e3, .floate1, .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1843,12 +1575,9 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"3e3r1", .btst16, - .ck803, - .ck803s, .dsp_silan, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1858,12 +1587,9 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"3e3r1", .btst16, - .ck803, - .ck803s, .dsp_silan, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1873,11 +1599,8 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"3e3r1", .btst16, - .ck803, - .ck803s, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1886,10 +1609,8 @@ pub const cpu = struct { .llvm_name = "ck803t", .features = featureSet(&[_]Feature{ .btst16, - .ck803, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1900,11 +1621,9 @@ pub const cpu = struct { .@"3e3r1", .@"3e3r3", .btst16, - .ck803, .dspv2, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1915,11 +1634,9 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dspv2, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1930,11 +1647,9 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .dspv2, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1945,11 +1660,8 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck804, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1960,13 +1672,10 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck804, .dspv2, .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1977,8 +1686,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck804, .dspv2, .float1e3, .floate1, @@ -1986,7 +1693,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -1997,8 +1703,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck804, .dspv2, .float1e3, .floate1, @@ -2006,7 +1710,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -2017,8 +1720,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck804, .dspv2, .float1e3, .floate1, @@ -2026,7 +1727,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -2037,8 +1737,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck804, .dspv2, .float1e3, .floate1, @@ -2046,7 +1744,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -2057,13 +1754,10 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck804, .dspv2, .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -2074,13 +1768,10 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck804, .dspv2, .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -2091,13 +1782,10 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck804, .dspv2, .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -2108,14 +1796,11 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck804, .float1e3, .floate1, .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -2126,14 +1811,11 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck804, .float1e3, .floate1, .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -2144,14 +1826,11 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck804, .float1e3, .floate1, .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -2162,11 +1841,8 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck804, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -2177,11 +1853,8 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck804, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -2192,11 +1865,8 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck804, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -2207,12 +1877,9 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck805, .high_registers, .hwdiv, .mp, - .nvic, .trust, .vdsp2e3, .vdspv2, @@ -2225,13 +1892,10 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck805, .dspv2, .high_registers, .hwdiv, .mp, - .nvic, .trust, .vdsp2e3, .vdspv2, @@ -2244,8 +1908,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck805, .dspv2, .float1e3, .floate1, @@ -2253,7 +1915,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, .vdsp2e3, .vdspv2, @@ -2266,8 +1927,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck805, .dspv2, .float1e3, .floate1, @@ -2275,7 +1934,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, .vdsp2e3, .vdspv2, @@ -2288,13 +1946,10 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck805, .dspv2, .high_registers, .hwdiv, .mp, - .nvic, .trust, .vdsp2e3, .vdspv2, @@ -2307,15 +1962,12 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck805, .float1e3, .floate1, .fpuv2_sf, .high_registers, .hwdiv, .mp, - .nvic, .trust, .vdsp2e3, .vdspv2, @@ -2328,15 +1980,12 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck805, .float1e3, .floate1, .fpuv2_sf, .high_registers, .hwdiv, .mp, - .nvic, .trust, .vdsp2e3, .vdspv2, @@ -2349,12 +1998,9 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck805, .high_registers, .hwdiv, .mp, - .nvic, .trust, .vdsp2e3, .vdspv2, @@ -2365,7 +2011,6 @@ pub const cpu = struct { .llvm_name = "ck807", .features = featureSet(&[_]Feature{ .cache, - .ck807, .dsp1e2, .dspe60, .edsp, @@ -2374,7 +2019,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, }), }; @@ -2383,7 +2027,6 @@ pub const cpu = struct { .llvm_name = "ck807e", .features = featureSet(&[_]Feature{ .cache, - .ck807, .dsp1e2, .dspe60, .edsp, @@ -2392,7 +2035,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, }), }; @@ -2401,7 +2043,6 @@ pub const cpu = struct { .llvm_name = "ck807ef", .features = featureSet(&[_]Feature{ .cache, - .ck807, .dsp1e2, .dspe60, .edsp, @@ -2417,7 +2058,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, }), }; @@ -2426,7 +2066,6 @@ pub const cpu = struct { .llvm_name = "ck807f", .features = featureSet(&[_]Feature{ .cache, - .ck807, .dsp1e2, .dspe60, .edsp, @@ -2442,7 +2081,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, }), }; @@ -2452,7 +2090,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"7e10", .cache, - .ck810, .dsp1e2, .dspe60, .edsp, @@ -2461,7 +2098,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, }), }; @@ -2471,7 +2107,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"7e10", .cache, - .ck810, .dsp1e2, .dspe60, .edsp, @@ -2480,7 +2115,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, }), }; @@ -2490,7 +2124,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"7e10", .cache, - .ck810, .dsp1e2, .dspe60, .edsp, @@ -2504,7 +2137,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, }), }; @@ -2514,7 +2146,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"7e10", .cache, - .ck810, .dsp1e2, .dspe60, .edsp, @@ -2528,7 +2159,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, }), }; @@ -2538,8 +2168,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"7e10", .cache, - .ck810, - .ck810v, .dsp1e2, .dspe60, .edsp, @@ -2553,7 +2181,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, .vdspv1, }), @@ -2564,8 +2191,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"7e10", .cache, - .ck810, - .ck810v, .dsp1e2, .dspe60, .edsp, @@ -2579,7 +2204,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, .vdspv1, }), @@ -2590,7 +2214,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"7e10", .cache, - .ck810, .dsp1e2, .dspe60, .edsp, @@ -2599,7 +2222,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, }), }; @@ -2609,8 +2231,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"7e10", .cache, - .ck810, - .ck810v, .dsp1e2, .dspe60, .edsp, @@ -2619,7 +2239,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, .vdspv1, }), @@ -2630,8 +2249,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"7e10", .cache, - .ck810, - .ck810v, .dsp1e2, .dspe60, .edsp, @@ -2640,7 +2257,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, .vdspv1, }), @@ -2651,7 +2267,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"7e10", .cache, - .ck810, .dsp1e2, .dspe60, .edsp, @@ -2665,7 +2280,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, }), }; @@ -2675,7 +2289,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"7e10", .cache, - .ck810, .dsp1e2, .dspe60, .edsp, @@ -2689,7 +2302,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, }), }; @@ -2699,8 +2311,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"7e10", .cache, - .ck810, - .ck810v, .dsp1e2, .dspe60, .edsp, @@ -2714,7 +2324,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, .vdspv1, }), @@ -2725,8 +2334,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"7e10", .cache, - .ck810, - .ck810v, .dsp1e2, .dspe60, .edsp, @@ -2740,7 +2347,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, .vdspv1, }), @@ -2751,7 +2357,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"7e10", .cache, - .ck810, .dsp1e2, .dspe60, .edsp, @@ -2760,7 +2365,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, }), }; @@ -2770,8 +2374,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"7e10", .cache, - .ck810, - .ck810v, .dsp1e2, .dspe60, .edsp, @@ -2780,7 +2382,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, .vdspv1, }), @@ -2791,8 +2392,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"7e10", .cache, - .ck810, - .ck810v, .dsp1e2, .dspe60, .edsp, @@ -2801,7 +2400,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, .vdspv1, }), @@ -2815,14 +2413,12 @@ pub const cpu = struct { .@"3e3r3", .btst16, .cache, - .ck860, .dspe60, .hard_tp, .high_registers, .hwdiv, .mp, .mp1e2, - .nvic, .trust, }), }; @@ -2835,7 +2431,6 @@ pub const cpu = struct { .@"3e3r3", .btst16, .cache, - .ck860, .dspe60, .float7e60, .fpuv3_df, @@ -2847,7 +2442,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, }), }; @@ -2860,8 +2454,6 @@ pub const cpu = struct { .@"3e3r3", .btst16, .cache, - .ck860, - .ck860v, .dspe60, .float7e60, .fpuv3_df, @@ -2873,7 +2465,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, .vdsp2e60f, .vdspv2, @@ -2888,15 +2479,12 @@ pub const cpu = struct { .@"3e3r3", .btst16, .cache, - .ck860, - .ck860v, .dspe60, .hard_tp, .high_registers, .hwdiv, .mp, .mp1e2, - .nvic, .trust, .vdsp2e60f, .vdspv2, @@ -2907,7 +2495,6 @@ pub const cpu = struct { .llvm_name = "e801", .features = featureSet(&[_]Feature{ .btst16, - .ck801, .e1, .trust, }), @@ -2917,9 +2504,7 @@ pub const cpu = struct { .llvm_name = "e802", .features = featureSet(&[_]Feature{ .btst16, - .ck802, .e2, - .nvic, .trust, }), }; @@ -2928,9 +2513,7 @@ pub const cpu = struct { .llvm_name = "e802t", .features = featureSet(&[_]Feature{ .btst16, - .ck802, .e2, - .nvic, .trust, }), }; @@ -2941,10 +2524,8 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -2955,10 +2536,8 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -2969,13 +2548,10 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck804, .dspv2, .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -2986,8 +2562,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck804, .dspv2, .float1e3, .floate1, @@ -2995,7 +2569,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -3006,8 +2579,6 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck804, .dspv2, .float1e3, .floate1, @@ -3015,7 +2586,6 @@ pub const cpu = struct { .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -3026,13 +2596,10 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck804, .dspv2, .high_registers, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -3043,14 +2610,11 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck804, .float1e3, .floate1, .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -3061,14 +2625,11 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck804, .float1e3, .floate1, .fpuv2_sf, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -3086,12 +2647,9 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck805, .high_registers, .hwdiv, .mp, - .nvic, .trust, .vdsp2e3, .vdspv2, @@ -3104,15 +2662,12 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, - .ck805, .float1e3, .floate1, .fpuv2_sf, .high_registers, .hwdiv, .mp, - .nvic, .trust, .vdsp2e3, .vdspv2, @@ -3123,7 +2678,6 @@ pub const cpu = struct { .llvm_name = "r807", .features = featureSet(&[_]Feature{ .cache, - .ck807, .dsp1e2, .dspe60, .edsp, @@ -3132,7 +2686,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, }), }; @@ -3141,7 +2694,6 @@ pub const cpu = struct { .llvm_name = "r807f", .features = featureSet(&[_]Feature{ .cache, - .ck807, .dsp1e2, .dspe60, .edsp, @@ -3157,7 +2709,6 @@ pub const cpu = struct { .hwdiv, .mp, .mp1e2, - .nvic, .trust, }), }; @@ -3166,9 +2717,7 @@ pub const cpu = struct { .llvm_name = "s802", .features = featureSet(&[_]Feature{ .btst16, - .ck802, .e2, - .nvic, .trust, }), }; @@ -3177,9 +2726,7 @@ pub const cpu = struct { .llvm_name = "s802t", .features = featureSet(&[_]Feature{ .btst16, - .ck802, .e2, - .nvic, .trust, }), }; @@ -3190,10 +2737,8 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .hwdiv, .mp, - .nvic, .trust, }), }; @@ -3204,10 +2749,8 @@ pub const cpu = struct { .@"3e3r2", .@"3e3r3", .btst16, - .ck803, .hwdiv, .mp, - .nvic, .trust, }), }; diff --git a/lib/std/Target/hppa.zig b/lib/std/Target/hppa.zig index 306ceb5c9a4ea2a7474221482b906fcf40114826..a28269e0625d40fcfa207826956fa67fe458fd66 100644 --- a/lib/std/Target/hppa.zig +++ b/lib/std/Target/hppa.zig @@ -5,7 +5,6 @@ const CpuFeature = std.Target.Cpu.Feature; const CpuModel = std.Target.Cpu.Model; pub const Feature = enum { - @"64bit", max_1, max_2, v1_1, @@ -21,13 +20,6 @@ pub const all_features = blk: { const len = @typeInfo(Feature).@"enum".field_names.len; std.debug.assert(len <= CpuFeature.Set.needed_bit_count); var result: [len]CpuFeature = undefined; - result[@backingInt(Feature.@"64bit")] = .{ - .llvm_name = null, - .description = "Enable 64-bit PA-RISC 2.0", - .dependencies = featureSet(&[_]Feature{ - .v2_0, - }), - }; result[@backingInt(Feature.max_1)] = .{ .llvm_name = null, .description = "Enable MAX-1 multimedia acceleration extensions", @@ -120,49 +112,49 @@ pub const cpu = struct { .name = "pa_8000", .llvm_name = null, .features = featureSet(&[_]Feature{ - .@"64bit", + .v2_0, }), }; pub const pa_8200: CpuModel = .{ .name = "pa_8200", .llvm_name = null, .features = featureSet(&[_]Feature{ - .@"64bit", + .v2_0, }), }; pub const pa_8500: CpuModel = .{ .name = "pa_8500", .llvm_name = null, .features = featureSet(&[_]Feature{ - .@"64bit", + .v2_0, }), }; pub const pa_8600: CpuModel = .{ .name = "pa_8600", .llvm_name = null, .features = featureSet(&[_]Feature{ - .@"64bit", + .v2_0, }), }; pub const pa_8700: CpuModel = .{ .name = "pa_8700", .llvm_name = null, .features = featureSet(&[_]Feature{ - .@"64bit", + .v2_0, }), }; pub const pa_8800: CpuModel = .{ .name = "pa_8800", .llvm_name = null, .features = featureSet(&[_]Feature{ - .@"64bit", + .v2_0, }), }; pub const pa_8900: CpuModel = .{ .name = "pa_8900", .llvm_name = null, .features = featureSet(&[_]Feature{ - .@"64bit", + .v2_0, }), }; pub const pcx: CpuModel = .{ diff --git a/lib/std/Target/kvx.zig b/lib/std/Target/kvx.zig index e0cff92996388458b82f572f8905836eda039d6c..22649e6c29d501e9f48ececbded69ac4dd65b601 100644 --- a/lib/std/Target/kvx.zig +++ b/lib/std/Target/kvx.zig @@ -27,9 +27,7 @@ pub const all_features = blk: { result[@backingInt(Feature.v3_2)] = .{ .llvm_name = null, .description = "Enable ISA v3.2", - .dependencies = featureSet(&[_]Feature{ - .v3_1, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.v4_1)] = .{ .llvm_name = null, diff --git a/lib/std/Target/ve.zig b/lib/std/Target/ve.zig index 3be114eef3329afc1e263d5a42a8ee0b256a0ae9..12defa85e498765fd6317926ceb176d3cc6a2c2f 100644 --- a/lib/std/Target/ve.zig +++ b/lib/std/Target/ve.zig @@ -5,6 +5,7 @@ const CpuFeature = std.Target.Cpu.Feature; const CpuModel = std.Target.Cpu.Model; pub const Feature = enum { + ve3, vpu, }; @@ -17,6 +18,11 @@ pub const all_features = blk: { const len = @typeInfo(Feature).@"enum".field_names.len; std.debug.assert(len <= CpuFeature.Set.needed_bit_count); var result: [len]CpuFeature = undefined; + result[@backingInt(Feature.ve3)] = .{ + .llvm_name = null, + .description = "Enable VE3 instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.vpu)] = .{ .llvm_name = "vpu", .description = "Enable the VPU", @@ -31,11 +37,26 @@ pub const all_features = blk: { }; pub const cpu = struct { - pub const generic: CpuModel = .{ - .name = "generic", - .llvm_name = "generic", + pub const ve10: CpuModel = .{ + .name = "ve10", + .llvm_name = null, .features = featureSet(&[_]Feature{ .vpu, }), }; + pub const ve20: CpuModel = .{ + .name = "ve20", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .vpu, + }), + }; + pub const ve30: CpuModel = .{ + .name = "ve30", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .ve3, + .vpu, + }), + }; }; diff --git a/lib/std/Target/wasm.zig b/lib/std/Target/wasm.zig index 8e8eb370c4a5a3b6e79e4d0c254046f0f9e4b659..609a1ef93eaa9dd475fe391e1755c4241125acbc 100644 --- a/lib/std/Target/wasm.zig +++ b/lib/std/Target/wasm.zig @@ -114,6 +114,7 @@ pub const all_features = blk: { .llvm_name = "reference-types", .description = "Enable reference types", .dependencies = featureSet(&[_]Feature{ + .bulk_memory, .call_indirect_overlong, }), }; @@ -125,7 +126,9 @@ pub const all_features = blk: { result[@backingInt(Feature.relaxed_simd)] = .{ .llvm_name = "relaxed-simd", .description = "Enable relaxed-simd instructions", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .simd128, + }), }; result[@backingInt(Feature.sign_ext)] = .{ .llvm_name = "sign-ext", @@ -156,37 +159,6 @@ pub const all_features = blk: { }; pub const cpu = struct { - pub const bleeding_edge: CpuModel = .{ - .name = "bleeding_edge", - .llvm_name = "bleeding-edge", - .features = featureSet(&[_]Feature{ - .atomics, - .bulk_memory, - .exception_handling, - .extended_const, - .fp16, - .gc, - .multimemory, - .mutable_globals, - .nontrapping_fptoint, - .relaxed_simd, - .sign_ext, - .simd128, - .tail_call, - }), - }; - pub const generic: CpuModel = .{ - .name = "generic", - .llvm_name = "generic", - .features = featureSet(&[_]Feature{ - .bulk_memory, - .multivalue, - .mutable_globals, - .nontrapping_fptoint, - .reference_types, - .sign_ext, - }), - }; pub const lime1: CpuModel = .{ .name = "lime1", .llvm_name = "lime1", @@ -205,4 +177,40 @@ pub const cpu = struct { .llvm_name = "mvp", .features = featureSet(&[_]Feature{}), }; + pub const wasm_v1_0: CpuModel = .{ + .name = "wasm_v1_0", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .mutable_globals, + }), + }; + pub const wasm_v2_0: CpuModel = .{ + .name = "wasm_v2_0", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .multivalue, + .mutable_globals, + .nontrapping_fptoint, + .reference_types, + .sign_ext, + .simd128, + }), + }; + pub const wasm_v3_0: CpuModel = .{ + .name = "wasm_v3_0", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .atomics, + .exception_handling, + .extended_const, + .fp16, + .gc, + .multimemory, + .mutable_globals, + .nontrapping_fptoint, + .relaxed_simd, + .sign_ext, + .tail_call, + }), + }; }; diff --git a/lib/std/Target/x86.zig b/lib/std/Target/x86.zig index 0bcc2638f16f0bb4cb553d35d3b94a3f7962b7ed..418ae155b721ddd87a550580dcb669247f7cbe58 100644 --- a/lib/std/Target/x86.zig +++ b/lib/std/Target/x86.zig @@ -3136,7 +3136,7 @@ pub const cpu = struct { }; pub const goldmont_plus: CpuModel = .{ .name = "goldmont_plus", - .llvm_name = "goldmont-plus", + .llvm_name = "goldmont_plus", .features = featureSet(&[_]Feature{ .@"64bit", .aes, @@ -3163,6 +3163,8 @@ pub const cpu = struct { .slow_incdec, .slow_lea, .slow_two_mem_ops, + .smap, + .smep, .sse4_2, .use_glm_div_sqrt_costs, .vzeroupper, @@ -3564,7 +3566,7 @@ pub const cpu = struct { }; pub const icelake_client: CpuModel = .{ .name = "icelake_client", - .llvm_name = "icelake-client", + .llvm_name = "icelake_client", .features = featureSet(&[_]Feature{ .@"64bit", .adx, @@ -3615,6 +3617,8 @@ pub const cpu = struct { .sahf, .sha, .slow_pmullq, + .smap, + .smep, .tuning_fast_imm_vector_shift, .vaes, .vpclmulqdq, @@ -3627,7 +3631,7 @@ pub const cpu = struct { }; pub const icelake_server: CpuModel = .{ .name = "icelake_server", - .llvm_name = "icelake-server", + .llvm_name = "icelake_server", .features = featureSet(&[_]Feature{ .@"64bit", .adx, @@ -3680,6 +3684,8 @@ pub const cpu = struct { .sahf, .sha, .slow_pmullq, + .smap, + .smep, .tuning_fast_imm_vector_shift, .vaes, .vpclmulqdq, @@ -4872,7 +4878,7 @@ pub const cpu = struct { }; pub const skylake_avx512: CpuModel = .{ .name = "skylake_avx512", - .llvm_name = "skylake-avx512", + .llvm_name = "skylake_avx512", .features = featureSet(&[_]Feature{ .@"64bit", .adx, @@ -4919,6 +4925,8 @@ pub const cpu = struct { .rdseed, .sahf, .slow_3ops_lea, + .smap, + .smep, .tuning_fast_imm_vector_shift, .vzeroupper, .x87, diff --git a/lib/std/Target/xcore.zig b/lib/std/Target/xcore.zig index e30381131e8a1ab33318588c72d380184b3352e4..b2580b5a7db89527e7926e903e98a64bde150690 100644 --- a/lib/std/Target/xcore.zig +++ b/lib/std/Target/xcore.zig @@ -4,7 +4,12 @@ const std = @import("../std.zig"); const CpuFeature = std.Target.Cpu.Feature; const CpuModel = std.Target.Cpu.Model; -pub const Feature = enum {}; +pub const Feature = enum { + fpu, + vpu, + xs2, + xs3, +}; pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet; pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas; @@ -15,6 +20,32 @@ pub const all_features = blk: { const len = @typeInfo(Feature).@"enum".field_names.len; std.debug.assert(len <= CpuFeature.Set.needed_bit_count); var result: [len]CpuFeature = undefined; + result[@backingInt(Feature.fpu)] = .{ + .llvm_name = null, + .description = "Enable single-precision floating point unit", + .dependencies = featureSet(&[_]Feature{ + .xs3, + }), + }; + result[@backingInt(Feature.vpu)] = .{ + .llvm_name = null, + .description = "Enable vector processing unit", + .dependencies = featureSet(&[_]Feature{ + .xs3, + }), + }; + result[@backingInt(Feature.xs2)] = .{ + .llvm_name = null, + .description = "Enable XS2 architecture", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.xs3)] = .{ + .llvm_name = null, + .description = "Enable XS3 architecture", + .dependencies = featureSet(&[_]Feature{ + .xs2, + }), + }; const ti = @typeInfo(Feature); for (&result, 0..) |*elem, i| { elem.index = i; @@ -24,14 +55,24 @@ pub const all_features = blk: { }; pub const cpu = struct { - pub const generic: CpuModel = .{ - .name = "generic", - .llvm_name = "generic", + pub const xs1b: CpuModel = .{ + .name = "xs1b", + .llvm_name = null, .features = featureSet(&[_]Feature{}), }; - pub const xs1b_generic: CpuModel = .{ - .name = "xs1b_generic", - .llvm_name = "xs1b-generic", - .features = featureSet(&[_]Feature{}), + pub const xs2a: CpuModel = .{ + .name = "xs2a", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .xs2, + }), + }; + pub const xs3a: CpuModel = .{ + .name = "xs3a", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .fpu, + .vpu, + }), }; }; diff --git a/src/Type.zig b/src/Type.zig index 2c207738b8f55cae37a5a120b68d968fa51e1f66..7a4256263882de8fe68ec8331e256b3dabd53db8 100644 --- a/src/Type.zig +++ b/src/Type.zig @@ -1302,10 +1302,7 @@ pub fn abiSize(ty: Type, zcu: *const Zcu) u64 { } pub fn ptrAbiAlignment(target: *const Target) Alignment { - // The eZ80 has 24-bit pointers, which aren't exact powers of two, tripping - // the assert. The alignment of eZ80 pointers is 1, so we bypass the check. - if (target.cpu.arch == .ez80) return .@"1"; - return .fromNonzeroByteUnits(@divExact(target.ptrBitWidth(), 8)); + return .fromNonzeroByteUnits(std.zig.target.intAlignment(target, target.ptrBitWidth())); } pub fn ptrAbiSize(target: *const Target) u64 { return @divExact(target.ptrBitWidth(), 8); diff --git a/test/c_abi/main.zig b/test/c_abi/main.zig index 2dee44a4501504302f53b7c5b16af0926fc9b742..3eedf398ca75e3412d5156f128ae1b40028958d0 100644 --- a/test/c_abi/main.zig +++ b/test/c_abi/main.zig @@ -5032,7 +5032,7 @@ extern fn c_vector_6_u8(@Vector(6, u8), usize) void; extern fn c_test_vector_6_u8() void; test "@Vector(6, u8)" { - if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest; + if (builtin.cpu.arch.isArm()) return error.SkipZigTest; if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest; if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; @@ -5110,7 +5110,7 @@ extern fn c_vector_12_u8(@Vector(12, u8), usize) void; extern fn c_test_vector_12_u8() void; test "@Vector(12, u8)" { - if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest; + if (builtin.cpu.arch.isArm()) return error.SkipZigTest; if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest; if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; @@ -9176,7 +9176,7 @@ extern fn c_vector_3_u16(@Vector(3, u16), usize) void; extern fn c_test_vector_3_u16() void; test "@Vector(3, u16)" { - if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest; + if (builtin.cpu.arch.isArm()) return error.SkipZigTest; if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest; if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; @@ -9250,7 +9250,7 @@ extern fn c_vector_6_u16(@Vector(6, u16), usize) void; extern fn c_test_vector_6_u16() void; test "@Vector(6, u16)" { - if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest; + if (builtin.cpu.arch.isArm()) return error.SkipZigTest; if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest; if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; @@ -11439,7 +11439,7 @@ extern fn c_vector_3_u32(@Vector(3, u32), usize) void; extern fn c_test_vector_3_u32() void; test "@Vector(3, u32)" { - if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest; + if (builtin.cpu.arch.isArm()) return error.SkipZigTest; if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest; if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; @@ -13424,7 +13424,7 @@ extern fn c_vector_3_f32(@Vector(3, f32), usize) void; extern fn c_test_vector_3_f32() void; test "@Vector(3, f32)" { - if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest; + if (builtin.cpu.arch.isArm()) return error.SkipZigTest; if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest; if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest; diff --git a/tools/update_cpu_features.zig b/tools/update_cpu_features.zig index 10200ae1ebbcdf20c63a5614328b874d0ea7fe4a..5c9df210ea899609d956acc8ac0ae93c3076ff3a 100644 --- a/tools/update_cpu_features.zig +++ b/tools/update_cpu_features.zig @@ -23,7 +23,17 @@ const FeatureOverride = struct { extra_deps: []const []const u8 = &.{}, }; -const Cpu = struct { +const ModelOverride = struct { + llvm_name: []const u8, + /// If true, completely omit the CPU; as if it does not exist. + omit: bool = false, + zig_name: ?[]const u8 = null, + desc: ?[]const u8 = null, + omit_deps: []const []const u8 = &.{}, + extra_deps: []const []const u8 = &.{}, +}; + +const Model = struct { llvm_name: ?[]const u8, zig_name: []const u8, features: []const []const u8, @@ -44,9 +54,9 @@ const ArchTarget = struct { td_name: []const u8, }, feature_overrides: []const FeatureOverride = &.{}, - extra_cpus: []const Cpu = &.{}, extra_features: []const Feature = &.{}, - omit_cpus: []const []const u8 = &.{}, + model_overrides: []const ModelOverride = &.{}, + extra_models: []const Model = &.{}, branch_quota: ?usize = null, }; @@ -432,7 +442,15 @@ const targets = [_]ArchTarget{ .flatten = true, }, }, - .extra_cpus = &.{ + .model_overrides = &.{ + .{ + // Who thought this alias was a good idea? Upgrade your compiler and suddenly your + // programs SIGILL because this changed meaning. Brilliant. + .llvm_name = "apple-latest", + .omit = true, + }, + }, + .extra_models = &.{ .{ .llvm_name = null, .zig_name = "exynos_m1", @@ -485,11 +503,6 @@ const targets = [_]ArchTarget{ }, }, }, - .omit_cpus = &.{ - // Who thought this alias was a good idea? Upgrade your compiler and suddenly your - // programs SIGILL because this changed meaning. Brilliant. - "apple-latest", - }, }, .{ .zig_name = "alpha", @@ -507,7 +520,7 @@ const targets = [_]ArchTarget{ }, .{ .zig_name = "fix", - .desc = "Enable floating point move and square root extensions", + .desc = "Enable FPR-to-GPR move and square root extensions", .deps = &.{}, }, .{ @@ -516,7 +529,7 @@ const targets = [_]ArchTarget{ .deps = &.{}, }, }, - .extra_cpus = &.{ + .extra_models = &.{ .{ .llvm_name = null, .zig_name = "ev4", @@ -613,98 +626,6 @@ const targets = [_]ArchTarget{ }, .branch_quota = 10000, .feature_overrides = &.{ - .{ - .llvm_name = "exynos", - .flatten = true, - }, - .{ - .llvm_name = "cortex-a78", - .flatten = true, - }, - .{ - .llvm_name = "cortex-a78ae", - .flatten = true, - }, - .{ - .llvm_name = "cortex-a710", - .flatten = true, - }, - .{ - .llvm_name = "cortex-m4", - .omit_deps = &.{"vfp4d16sp"}, - }, - .{ - .llvm_name = "cortex-m7", - .omit_deps = &.{"fp_armv8d16"}, - }, - .{ - .llvm_name = "cortex-m33", - .omit_deps = &.{ "fp_armv8d16sp", "dsp" }, - }, - .{ - .llvm_name = "cortex-m35p", - .omit_deps = &.{ "fp_armv8d16sp", "dsp" }, - }, - .{ - .llvm_name = "cortex-m55", - .omit_deps = &.{ "mve_fp", "fp_armv8d16" }, - }, - .{ - .llvm_name = "cortex-m85", - .omit_deps = &.{ "mve_fp", "pacbti", "fp_armv8d16" }, - }, - .{ - .llvm_name = "cortex-x1c", - .flatten = true, - }, - .{ - .llvm_name = "r4", - .flatten = true, - }, - .{ - .llvm_name = "r52plus", - .flatten = true, - }, - .{ - .llvm_name = "r5", - .flatten = true, - }, - .{ - .llvm_name = "r52", - .flatten = true, - }, - .{ - .llvm_name = "r7", - .flatten = true, - }, - .{ - .llvm_name = "m3", - .flatten = true, - }, - .{ - .llvm_name = "m7", - .flatten = true, - }, - .{ - .llvm_name = "krait", - .flatten = true, - }, - .{ - .llvm_name = "kryo", - .flatten = true, - }, - .{ - .llvm_name = "swift", - .flatten = true, - }, - .{ - .llvm_name = "cortex-x1", - .flatten = true, - }, - .{ - .llvm_name = "neoverse-v1", - .flatten = true, - }, .{ .llvm_name = "a5", .flatten = true, @@ -777,6 +698,75 @@ const targets = [_]ArchTarget{ .llvm_name = "a78c", .flatten = true, }, + .{ + .llvm_name = "cortex-a78", + .flatten = true, + }, + .{ + .llvm_name = "cortex-a78ae", + .flatten = true, + }, + .{ + .llvm_name = "cortex-a710", + .flatten = true, + }, + .{ + .llvm_name = "cortex-x1", + .flatten = true, + }, + .{ + .llvm_name = "cortex-x1c", + .flatten = true, + }, + .{ + .llvm_name = "exynos", + .flatten = true, + }, + .{ + .llvm_name = "krait", + .flatten = true, + }, + .{ + .llvm_name = "kryo", + .flatten = true, + }, + .{ + .llvm_name = "m3", + .flatten = true, + }, + .{ + .llvm_name = "m7", + .flatten = true, + }, + .{ + .llvm_name = "neoverse-v1", + .flatten = true, + }, + .{ + .llvm_name = "r4", + .flatten = true, + }, + .{ + .llvm_name = "r5", + .flatten = true, + }, + .{ + .llvm_name = "r7", + .flatten = true, + }, + .{ + .llvm_name = "r52", + .flatten = true, + }, + .{ + .llvm_name = "r52plus", + .flatten = true, + }, + .{ + .llvm_name = "swift", + .flatten = true, + }, + .{ .llvm_name = "armv2", .zig_name = "v2", @@ -853,6 +843,7 @@ const targets = [_]ArchTarget{ .{ .llvm_name = "armv7-a", .zig_name = "v7a", + .omit_deps = &.{"neon"}, }, .{ .llvm_name = "armv7-m", @@ -877,58 +868,72 @@ const targets = [_]ArchTarget{ .{ .llvm_name = "armv7ve", .zig_name = "v7ve", + .omit_deps = &.{"neon"}, }, .{ .llvm_name = "armv8.1-a", .zig_name = "v8_1a", + .omit_deps = &.{"crypto"}, }, .{ .llvm_name = "armv8.1-m.main", .zig_name = "v8_1m_main", + .omit_deps = &.{"8msecext"}, }, .{ .llvm_name = "armv8.2-a", .zig_name = "v8_2a", + .omit_deps = &.{"crypto"}, }, .{ .llvm_name = "armv8.3-a", .zig_name = "v8_3a", + .omit_deps = &.{"crypto"}, }, .{ .llvm_name = "armv8.4-a", .zig_name = "v8_4a", + .omit_deps = &.{"crypto"}, }, .{ .llvm_name = "armv8.5-a", .zig_name = "v8_5a", + .omit_deps = &.{"crypto"}, }, .{ .llvm_name = "armv8.6-a", .zig_name = "v8_6a", + .omit_deps = &.{"crypto"}, }, .{ .llvm_name = "armv8.7-a", .zig_name = "v8_7a", + .omit_deps = &.{"crypto"}, }, .{ .llvm_name = "armv8.8-a", .zig_name = "v8_8a", + .omit_deps = &.{"crypto"}, }, .{ .llvm_name = "armv8.9-a", .zig_name = "v8_9a", + .omit_deps = &.{"crypto"}, }, .{ .llvm_name = "armv8-a", .zig_name = "v8a", + .omit_deps = &.{"crypto"}, }, .{ .llvm_name = "armv8-m.base", .zig_name = "v8m", + .omit_deps = &.{"8msecext"}, }, .{ .llvm_name = "armv8-m.main", .zig_name = "v8m_main", + .omit_deps = &.{"8msecext"}, }, .{ .llvm_name = "armv8-r", @@ -945,6 +950,7 @@ const targets = [_]ArchTarget{ .{ .llvm_name = "armv9.3-a", .zig_name = "v9_3a", + .omit_deps = &.{"crypto"}, }, .{ .llvm_name = "armv9.4-a", @@ -1087,23 +1093,6 @@ const targets = [_]ArchTarget{ .zig_name = "has_v9_7a", }, }, - .extra_cpus = &.{ - .{ - .llvm_name = "generic", - .zig_name = "baseline", - .features = &.{"v7a"}, - }, - .{ - .llvm_name = null, - .zig_name = "exynos_m1", - .features = &.{ "v8a", "exynos" }, - }, - .{ - .llvm_name = null, - .zig_name = "exynos_m2", - .features = &.{ "v8a", "exynos" }, - }, - }, .extra_features = &.{ // LLVM removed support for v2 and v3 but zig wants to support targeting old hardware .{ @@ -1127,6 +1116,198 @@ const targets = [_]ArchTarget{ .deps = &.{"strict_align"}, }, }, + .model_overrides = &.{ + .{ + .llvm_name = "cortex-a5", + .omit_deps = &.{"vfp4"}, + }, + .{ + .llvm_name = "cortex-a7", + .omit_deps = &.{"vfp4"}, + }, + .{ + .llvm_name = "cortex-a9", + .omit_deps = &.{"fp16"}, + }, + .{ + .llvm_name = "cortex-a12", + .omit_deps = &.{"vfp4"}, + }, + .{ + .llvm_name = "cortex-a15", + .omit_deps = &.{"vfp4"}, + }, + .{ + .llvm_name = "cortex-a17", + .omit_deps = &.{"vfp4"}, + }, + .{ + .llvm_name = "cortex-a32", + .omit_deps = &.{"crypto"}, + }, + .{ + .llvm_name = "cortex-a35", + .omit_deps = &.{"crypto"}, + }, + .{ + .llvm_name = "cortex-a53", + .omit_deps = &.{"crypto"}, + }, + .{ + .llvm_name = "cortex-a57", + .omit_deps = &.{"crypto"}, + }, + .{ + .llvm_name = "cortex-a72", + .omit_deps = &.{"crypto"}, + }, + .{ + .llvm_name = "cortex-a73", + .omit_deps = &.{"crypto"}, + }, + .{ + .llvm_name = "cortex-a76", + .omit_deps = &.{"crypto"}, + }, + .{ + .llvm_name = "cortex-a76ae", + .omit_deps = &.{"crypto"}, + }, + .{ + .llvm_name = "cortex-a77", + .omit_deps = &.{"crypto"}, + }, + .{ + .llvm_name = "cortex-a78", + .omit_deps = &.{"crypto"}, + }, + .{ + .llvm_name = "cortex-a78ae", + .omit_deps = &.{"crypto"}, + }, + .{ + .llvm_name = "cortex-a78c", + .omit_deps = &.{"crypto"}, + }, + .{ + .llvm_name = "cortex-m4", + .omit_deps = &.{"vfp4d16sp"}, + }, + .{ + .llvm_name = "cortex-m7", + .omit_deps = &.{"fp_armv8d16"}, + }, + .{ + .llvm_name = "cortex-m33", + .omit_deps = &.{ "dsp", "fp_armv8d16sp" }, + }, + .{ + .llvm_name = "cortex-m35p", + .omit_deps = &.{ "dsp", "fp_armv8d16sp" }, + }, + .{ + .llvm_name = "cortex-m52", + .omit_deps = &.{ "fp_armv8d16", "mve_fp", "pacbti" }, + }, + .{ + .llvm_name = "cortex-m55", + .omit_deps = &.{ "fp_armv8d16", "mve_fp" }, + }, + .{ + .llvm_name = "cortex-m85", + .extra_deps = &.{"8msecext"}, + .omit_deps = &.{ "fp_armv8d16", "mve_fp", "pacbti" }, + }, + .{ + .llvm_name = "cortex-r5", + .omit_deps = &.{"vfp3d16"}, + }, + .{ + .llvm_name = "cortex-r7", + .omit_deps = &.{ "fp16", "vfp3d16" }, + }, + .{ + .llvm_name = "cortex-r8", + .omit_deps = &.{ "fp16", "vfp3d16" }, + }, + .{ + .llvm_name = "cortex-r52", + .omit_deps = &.{ "fp_armv8", "neon" }, + }, + .{ + .llvm_name = "cortex-r52plus", + .omit_deps = &.{ "fp_armv8", "neon" }, + }, + .{ + .llvm_name = "cortex-x1", + .omit_deps = &.{"crypto"}, + }, + .{ + .llvm_name = "cortex-x1c", + .omit_deps = &.{"crypto"}, + }, + .{ + .llvm_name = "krait", + .extra_deps = &.{"neon"}, + }, + .{ + .llvm_name = "neoverse-n1", + .omit_deps = &.{"crypto"}, + }, + .{ + .llvm_name = "neoverse-v1", + .omit_deps = &.{"crypto"}, + }, + .{ + .llvm_name = "star-mc1", + .omit_deps = &.{ "dsp", "fp_armv8d16sp" }, + }, + .{ + .llvm_name = "star-mc3", + .omit_deps = &.{ "fp_armv8d16", "mve_fp", "pacbti" }, + }, + .{ + .llvm_name = "swift", + .extra_deps = &.{"neon"}, + }, + }, + .extra_models = &.{ + .{ + .llvm_name = "generic", + .zig_name = "baseline", + .features = &.{ "v7a", "vfp3d16" }, + }, + .{ + .llvm_name = null, + .zig_name = "exynos_m1", + .features = &.{ "v8a", "exynos" }, + }, + .{ + .llvm_name = null, + .zig_name = "exynos_m2", + .features = &.{ "v8a", "exynos" }, + }, + .{ + .llvm_name = "cortex-a9", + .zig_name = "kermit", + .features = &.{ + "avoid_partial_cpsr", + "expand_fp_mlx", + "fp16", + "mp", + "muxed_units", + "neon", + "neon_fpmovs", + "prefer_vmovsr", + "ret_addr_stack", + "trustzone", + "v7a", + "vldn_align", + "vmlx_forwarding", + "vmlx_hazards", + }, + }, + }, }, .{ .zig_name = "avr", @@ -1141,6 +1322,16 @@ const targets = [_]ArchTarget{ .name = "BPF", .td_name = "BPF", }, + .feature_overrides = &.{ + .{ + .llvm_name = "dummy", + .omit = true, + }, + .{ + .llvm_name = "dwarfris", + .omit = true, + }, + }, }, .{ .zig_name = "csky", @@ -1148,6 +1339,85 @@ const targets = [_]ArchTarget{ .name = "CSKY", .td_name = "CSKY", }, + .feature_overrides = &.{ + .{ + .llvm_name = "ccrt", + .omit = true, + }, + .{ + .llvm_name = "constpool", + .omit = true, + }, + .{ + .llvm_name = "multiple_stld", + .omit = true, + }, + .{ + .llvm_name = "nvic", + .omit = true, + }, + .{ + .llvm_name = "pushpop", + .omit = true, + }, + .{ + .llvm_name = "smart", + .omit = true, + }, + .{ + .llvm_name = "soft_tp", + .omit = true, + }, + .{ + .llvm_name = "stack_size", + .omit = true, + }, + + .{ + .llvm_name = "ck801", + .flatten = true, + }, + .{ + .llvm_name = "ck802", + .flatten = true, + }, + .{ + .llvm_name = "ck803", + .flatten = true, + }, + .{ + .llvm_name = "ck803s", + .flatten = true, + }, + .{ + .llvm_name = "ck804", + .flatten = true, + }, + .{ + .llvm_name = "ck805", + .flatten = true, + }, + .{ + .llvm_name = "ck807", + .flatten = true, + }, + .{ + .llvm_name = "ck810", + .flatten = true, + }, + .{ + .llvm_name = "ck810v", + .flatten = true, + }, + .{ + .llvm_name = "ck860", + .flatten = true, + }, + .{ + .llvm_name = "ck860v", + .flatten = true, + }, + }, }, .{ .zig_name = "hexagon", @@ -1160,11 +1430,6 @@ const targets = [_]ArchTarget{ .zig_name = "hppa", .llvm = null, .extra_features = &.{ - .{ - .zig_name = "64bit", - .desc = "Enable 64-bit PA-RISC 2.0", - .deps = &.{"v2_0"}, - }, .{ .zig_name = "max_1", .desc = "Enable MAX-1 multimedia acceleration extensions", @@ -1186,7 +1451,7 @@ const targets = [_]ArchTarget{ .deps = &.{ "max_2", "v1_1" }, }, }, - .extra_cpus = &.{ + .extra_models = &.{ .{ .llvm_name = null, .zig_name = "ts_1", @@ -1255,49 +1520,49 @@ const targets = [_]ArchTarget{ .llvm_name = null, .zig_name = "pa_8000", .features = &.{ - "64bit", + "v2_0", }, }, .{ .llvm_name = null, .zig_name = "pa_8200", .features = &.{ - "64bit", + "v2_0", }, }, .{ .llvm_name = null, .zig_name = "pa_8500", .features = &.{ - "64bit", + "v2_0", }, }, .{ .llvm_name = null, .zig_name = "pa_8600", .features = &.{ - "64bit", + "v2_0", }, }, .{ .llvm_name = null, .zig_name = "pa_8700", .features = &.{ - "64bit", + "v2_0", }, }, .{ .llvm_name = null, .zig_name = "pa_8800", .features = &.{ - "64bit", + "v2_0", }, }, .{ .llvm_name = null, .zig_name = "pa_8900", .features = &.{ - "64bit", + "v2_0", }, }, }, @@ -1314,7 +1579,7 @@ const targets = [_]ArchTarget{ .{ .zig_name = "v3_2", .desc = "Enable ISA v3.2", - .deps = &.{"v3_1"}, + .deps = &.{}, }, .{ .zig_name = "v4_1", @@ -1322,7 +1587,7 @@ const targets = [_]ArchTarget{ .deps = &.{"v3_2"}, }, }, - .extra_cpus = &.{ + .extra_models = &.{ .{ .llvm_name = null, .zig_name = "coolidge_v1", @@ -1352,7 +1617,25 @@ const targets = [_]ArchTarget{ .name = "LoongArch", .td_name = "LoongArch", }, - .extra_cpus = &.{ + .model_overrides = &.{ + .{ + .llvm_name = "generic", + .omit = true, + }, + .{ + .llvm_name = "generic-la64", + .omit = true, + }, + .{ + .llvm_name = "loongarch32", + .omit = true, + }, + .{ + .llvm_name = "loongarch64", + .omit = true, + }, + }, + .extra_models = &.{ .{ .llvm_name = null, .zig_name = "generic_la64", @@ -1403,12 +1686,6 @@ const targets = [_]ArchTarget{ }, }, }, - .omit_cpus = &.{ - "generic", - "generic-la64", - "loongarch32", - "loongarch64", - }, }, .{ .zig_name = "m68k", @@ -1437,7 +1714,7 @@ const targets = [_]ArchTarget{ .deps = &.{}, }, }, - .extra_cpus = &.{ + .extra_models = &.{ .{ .llvm_name = null, .zig_name = "r3000a", @@ -1489,7 +1766,13 @@ const targets = [_]ArchTarget{ .omit = true, }, }, - .extra_cpus = &.{ + .model_overrides = &.{ + .{ + .llvm_name = "ppc32", + .omit = true, + }, + }, + .extra_models = &.{ .{ .llvm_name = null, .zig_name = "cell", @@ -1525,9 +1808,6 @@ const targets = [_]ArchTarget{ }, }, }, - .omit_cpus = &.{ - "ppc32", - }, }, .{ .zig_name = "propeller", @@ -1539,7 +1819,7 @@ const targets = [_]ArchTarget{ .deps = &.{}, }, }, - .extra_cpus = &.{ + .extra_models = &.{ .{ .llvm_name = null, .zig_name = "p1", @@ -1560,7 +1840,7 @@ const targets = [_]ArchTarget{ }, .branch_quota = 2000, .extra_features = spirv_extra_features, - .extra_cpus = &.{ + .extra_models = &.{ .{ .llvm_name = null, .zig_name = "vulkan_v1_2", @@ -1586,7 +1866,7 @@ const targets = [_]ArchTarget{ .flatten = true, }, }, - .extra_cpus = &.{ + .extra_models = &.{ .{ .llvm_name = null, .zig_name = "baseline_rv32", @@ -1619,6 +1899,36 @@ const targets = [_]ArchTarget{ .name = "VE", .td_name = "VE", }, + .extra_features = &.{ + .{ + .zig_name = "ve3", + .desc = "Enable VE3 instructions", + .deps = &.{}, + }, + }, + .model_overrides = &.{ + .{ + .llvm_name = "generic", + .omit = true, + }, + }, + .extra_models = &.{ + .{ + .llvm_name = null, + .zig_name = "ve10", + .features = &.{"vpu"}, + }, + .{ + .llvm_name = null, + .zig_name = "ve20", + .features = &.{"vpu"}, + }, + .{ + .llvm_name = null, + .zig_name = "ve30", + .features = &.{ "ve3", "vpu" }, + }, + }, }, .{ .zig_name = "wasm", @@ -1633,9 +1943,17 @@ const targets = [_]ArchTarget{ .llvm_name = "bulk-memory", .extra_deps = &.{"bulk_memory_opt"}, }, + .{ + .llvm_name = "f16", + .extra_deps = &.{"simd128"}, + }, .{ .llvm_name = "reference-types", - .extra_deps = &.{"call_indirect_overlong"}, + .extra_deps = &.{ "bulk_memory", "call_indirect_overlong" }, + }, + .{ + .llvm_name = "relaxed-simd", + .extra_deps = &.{"simd128"}, }, }, .extra_features = &.{ @@ -1645,6 +1963,54 @@ const targets = [_]ArchTarget{ .deps = &.{"bulk_memory_opt"}, }, }, + .model_overrides = &.{ + .{ + .llvm_name = "bleeding-edge", + .omit = true, + }, + .{ + .llvm_name = "generic", + .omit = true, + }, + }, + .extra_models = &.{ + .{ + .llvm_name = null, + .zig_name = "wasm_v1_0", + .features = &.{ + "mutable_globals", + }, + }, + .{ + .llvm_name = null, + .zig_name = "wasm_v2_0", + .features = &.{ + "multivalue", + "mutable_globals", + "nontrapping_fptoint", + "reference_types", + "sign_ext", + "simd128", + }, + }, + .{ + .llvm_name = null, + .zig_name = "wasm_v3_0", + .features = &.{ + "atomics", + "exception_handling", + "extended_const", + "fp16", + "gc", + "multimemory", + "mutable_globals", + "nontrapping_fptoint", + "relaxed_simd", + "sign_ext", + "tail_call", + }, + }, + }, }, .{ .zig_name = "x86", @@ -1670,21 +2036,59 @@ const targets = [_]ArchTarget{ .omit = true, }, .{ - .llvm_name = "alderlake", - .extra_deps = &.{ "smap", "smep" }, + .llvm_name = "sse4.2", + .extra_deps = &.{"crc32"}, }, + }, + .extra_features = &.{ + // Features removed from LLVM + .{ + .zig_name = "3dnow", + .desc = "Enable 3DNow! instructions", + .deps = &.{"mmx"}, + }, + .{ + .zig_name = "3dnowa", + .desc = "Enable 3DNow! Athlon instructions", + .deps = &.{"3dnow"}, + }, + .{ + .zig_name = "avx512er", + .desc = "Enable AVX-512 Exponential and Reciprocal Instructions", + .deps = &.{"avx512f"}, + }, + .{ + .zig_name = "avx512pf", + .desc = "Enable AVX-512 PreFetch Instructions", + .deps = &.{"avx512f"}, + }, + .{ + .zig_name = "prefetchwt1", + .desc = "Prefetch with Intent to Write and T1 Hint", + .deps = &.{}, + }, + // Custom Zig features + .{ + .zig_name = "bsf_bsr_0_clobbers_result", + .desc = "BSF/BSR may clobber the lower 32-bits of the result register when the source is zero", + .deps = &.{}, + }, + .{ + .zig_name = "smap", + .desc = "Enable Supervisor Mode Access Prevention", + .deps = &.{}, + }, + .{ + .zig_name = "smep", + .desc = "Enable Supervisor Mode Execution Prevention", + .deps = &.{}, + }, + }, + .model_overrides = &.{ .{ .llvm_name = "amdfam10", .extra_deps = &.{"3dnowa"}, }, - .{ - .llvm_name = "arrowlake", - .extra_deps = &.{ "smap", "smep" }, - }, - .{ - .llvm_name = "arrowlake-s", - .extra_deps = &.{ "smap", "smep" }, - }, .{ .llvm_name = "athlon", .extra_deps = &.{"3dnowa"}, @@ -1862,8 +2266,16 @@ const targets = [_]ArchTarget{ .extra_deps = &.{"3dnow"}, }, .{ - .llvm_name = "sse4.2", - .extra_deps = &.{"crc32"}, + .llvm_name = "alderlake", + .extra_deps = &.{ "smap", "smep" }, + }, + .{ + .llvm_name = "arrowlake", + .extra_deps = &.{ "smap", "smep" }, + }, + .{ + .llvm_name = "arrowlake-s", + .extra_deps = &.{ "smap", "smep" }, }, .{ .llvm_name = "znver1", @@ -1885,92 +2297,140 @@ const targets = [_]ArchTarget{ .llvm_name = "znver5", .extra_deps = &.{ "smap", "smep" }, }, - }, - .extra_features = &.{ - // Features removed from LLVM + + // LLVM defines a bunch of dumb aliases with foreach loops in X86.td. + .{ + .llvm_name = "pentium_mmx", + .omit = true, + }, + .{ + .llvm_name = "pentium_pro", + .omit = true, + }, + .{ + .llvm_name = "pentium_ii", + .omit = true, + }, + .{ + .llvm_name = "pentium_3m", + .omit = true, + }, + .{ + .llvm_name = "pentium_iii", + .omit = true, + }, + .{ + .llvm_name = "pentium_iii_no_xmm_regs", + .omit = true, + }, + .{ + .llvm_name = "pentium_m", + .omit = true, + }, + .{ + .llvm_name = "pentium4m", + .omit = true, + }, + .{ + .llvm_name = "pentium_4", + .omit = true, + }, + .{ + .llvm_name = "pentium_4_sse3", + .omit = true, + }, + .{ + .llvm_name = "core_2_duo_ssse3", + .omit = true, + }, + .{ + .llvm_name = "core_2_duo_sse4_1", + .omit = true, + }, + .{ + .llvm_name = "atom_sse4_2", + .omit = true, + }, + .{ + .llvm_name = "goldmont-plus", + .omit = true, + }, + .{ + .llvm_name = "core_i7_sse4_2", + .omit = true, + }, + .{ + .llvm_name = "core_aes_pclmulqdq", + .omit = true, + }, + .{ + .llvm_name = "corei7-avx", + .omit = true, + }, + .{ + .llvm_name = "core_2nd_gen_avx", + .omit = true, + }, + .{ + .llvm_name = "core-avx-i", + .omit = true, + }, + .{ + .llvm_name = "core_3rd_gen_avx", + .omit = true, + }, + .{ + .llvm_name = "core-avx2", + .omit = true, + }, + .{ + .llvm_name = "core_4th_gen_avx", + .omit = true, + }, + .{ + .llvm_name = "core_4th_gen_avx_tsx", + .omit = true, + }, .{ - .zig_name = "3dnow", - .desc = "Enable 3DNow! instructions", - .deps = &.{"mmx"}, + .llvm_name = "core_5th_gen_avx", + .omit = true, }, .{ - .zig_name = "3dnowa", - .desc = "Enable 3DNow! Athlon instructions", - .deps = &.{"3dnow"}, + .llvm_name = "core_5th_gen_avx_tsx", + .omit = true, }, .{ - .zig_name = "avx512er", - .desc = "Enable AVX-512 Exponential and Reciprocal Instructions", - .deps = &.{"avx512f"}, + .llvm_name = "mic_avx512", + .omit = true, }, .{ - .zig_name = "avx512pf", - .desc = "Enable AVX-512 PreFetch Instructions", - .deps = &.{"avx512f"}, + .llvm_name = "skylake-avx512", + .omit = true, }, .{ - .zig_name = "prefetchwt1", - .desc = "Prefetch with Intent to Write and T1 Hint", - .deps = &.{}, + .llvm_name = "icelake-client", + .omit = true, }, - // Custom Zig features .{ - .zig_name = "bsf_bsr_0_clobbers_result", - .desc = "BSF/BSR may clobber the lower 32-bits of the result register when the source is zero", - .deps = &.{}, + .llvm_name = "icelake-server", + .omit = true, }, .{ - .zig_name = "smap", - .desc = "Enable Supervisor Mode Access Prevention", - .deps = &.{}, + .llvm_name = "graniterapids_d", + .omit = true, }, .{ - .zig_name = "smep", - .desc = "Enable Supervisor Mode Execution Prevention", - .deps = &.{}, + .llvm_name = "arrowlake_s", + .omit = true, }, }, - .extra_cpus = &.{ + .extra_models = &.{ .{ .llvm_name = null, .zig_name = "i86", .features = &.{"16bit_mode"}, }, }, - .omit_cpus = &.{ - // LLVM defines a bunch of dumb aliases with foreach loops in X86.td. - "pentium_mmx", - "pentium_pro", - "pentium_ii", - "pentium_3m", - "pentium_iii_no_xmm_regs", - "pentium_iii", - "pentium_m", - "pentium4m", - "pentium_4", - "pentium_4_sse3", - "core_2_duo_ssse3", - "core_2_duo_sse4_1", - "atom_sse4_2", - "goldmont_plus", - "core_i7_sse4_2", - "core_aes_pclmulqdq", - "corei7-avx", - "core_2nd_gen_avx", - "core-avx-i", - "core_3rd_gen_avx", - "core-avx2", - "core_4th_gen_avx", - "core_4th_gen_avx_tsx", - "core_5th_gen_avx", - "core_5th_gen_avx_tsx", - "mic_avx512", - "skylake_avx512", - "icelake_client", - "icelake_server", - "graniterapids_d", - "arrowlake_s", - }, }, .{ .zig_name = "xcore", @@ -1978,6 +2438,55 @@ const targets = [_]ArchTarget{ .name = "XCore", .td_name = "XCore", }, + .extra_features = &.{ + .{ + .zig_name = "xs2", + .desc = "Enable XS2 architecture", + .deps = &.{}, + }, + .{ + .zig_name = "xs3", + .desc = "Enable XS3 architecture", + .deps = &.{"xs2"}, + }, + .{ + .zig_name = "fpu", + .desc = "Enable single-precision floating point unit", + .deps = &.{"xs3"}, + }, + .{ + .zig_name = "vpu", + .desc = "Enable vector processing unit", + .deps = &.{"xs3"}, + }, + }, + .model_overrides = &.{ + .{ + .llvm_name = "generic", + .omit = true, + }, + .{ + .llvm_name = "xs1b-generic", + .omit = true, + }, + }, + .extra_models = &.{ + .{ + .llvm_name = null, + .zig_name = "xs1b", + .features = &.{}, + }, + .{ + .llvm_name = null, + .zig_name = "xs2a", + .features = &.{"xs2"}, + }, + .{ + .llvm_name = null, + .zig_name = "xs3a", + .features = &.{ "fpu", "vpu" }, + }, + }, }, .{ .zig_name = "xtensa", @@ -2073,7 +2582,7 @@ fn processOneTargetInner(io: Io, job: Job) !void { var features_table = std.StringHashMap(Feature).init(arena); var all_features = std.array_list.Managed(Feature).init(arena); - var all_cpus = std.array_list.Managed(Cpu).init(arena); + var all_models = std.array_list.Managed(Model).init(arena); if (target.llvm) |llvm| { const tblgen_progress = progress_node.start("running llvm-tblgen", 0); @@ -2133,7 +2642,7 @@ fn processOneTargetInner(io: Io, job: Job) !void { llvm: []const u8, zig: []const u8, }; - var cpu_aliases = std.StringHashMap(std.ArrayList(*Alias)).init(arena); + var model_aliases = std.StringHashMap(std.ArrayList(*Alias)).init(arena); { var it = root_map.iterator(); @@ -2147,7 +2656,7 @@ fn processOneTargetInner(io: Io, job: Job) !void { const llvm_alias = kv.value_ptr.object.get("Name").?.string; const llvm_name = kv.value_ptr.object.get("Alias").?.string; - const gop = try cpu_aliases.getOrPut(try llvmNameToZigName(arena, llvm_name)); + const gop = try model_aliases.getOrPut(try llvmNameToZigName(arena, llvm_name)); if (!gop.found_existing) { gop.value_ptr.* = .empty; @@ -2253,28 +2762,25 @@ fn processOneTargetInner(io: Io, job: Job) !void { if (hasSuperclass(&kv.value_ptr.object, "Processor")) { const llvm_name = kv.value_ptr.object.get("Name").?.string; if (llvm_name.len == 0) continue; - const omitted = for (target.omit_cpus) |omit_cpu_name| { - if (mem.eql(u8, omit_cpu_name, llvm_name)) break true; + + var zig_name = try llvmNameToZigName(arena, llvm_name); + var deps = std.array_list.Managed([]const u8).init(arena); + var omit_deps: []const []const u8 = &.{}; + var extra_deps: []const []const u8 = &.{}; + const omitted = for (target.model_overrides) |model_override| { + if (mem.eql(u8, llvm_name, model_override.llvm_name)) { + if (model_override.omit) { + break true; + } + if (model_override.zig_name) |override_name| { + zig_name = override_name; + } + omit_deps = model_override.omit_deps; + extra_deps = model_override.extra_deps; + break false; + } } else false; if (omitted) continue; - - var zig_name = try llvmNameToZigName(arena, llvm_name); - var deps = std.array_list.Managed([]const u8).init(arena); - var omit_deps: []const []const u8 = &.{}; - var extra_deps: []const []const u8 = &.{}; - for (target.feature_overrides) |feature_override| { - if (mem.eql(u8, llvm_name, feature_override.llvm_name)) { - if (feature_override.omit) { - continue; - } - if (feature_override.zig_name) |override_name| { - zig_name = override_name; - } - omit_deps = feature_override.omit_deps; - extra_deps = feature_override.extra_deps; - break; - } - } const features = kv.value_ptr.object.get("Features").?.array; for (features.items) |feature| { const feature_key = feature.object.get("def").?.string; @@ -2308,19 +2814,19 @@ fn processOneTargetInner(io: Io, job: Job) !void { )) orelse continue; try deps.append(feature_zig_name); } - try all_cpus.append(.{ + try all_models.append(.{ .llvm_name = llvm_name, .zig_name = zig_name, .features = deps.items, }); - if (cpu_aliases.get(zig_name)) |aliases| { + if (model_aliases.get(zig_name)) |aliases| { alias_it: for (aliases.items) |alias| { - for (target.omit_cpus) |omit_cpu_name| { - if (mem.eql(u8, omit_cpu_name, alias.llvm)) continue :alias_it; + for (target.model_overrides) |model_override| { + if (mem.eql(u8, alias.llvm, model_override.llvm_name) and model_override.omit) continue :alias_it; } - try all_cpus.append(.{ + try all_models.append(.{ .llvm_name = alias.llvm, .zig_name = alias.zig, .features = deps.items, @@ -2338,11 +2844,11 @@ fn processOneTargetInner(io: Io, job: Job) !void { try features_table.put(extra_feature.zig_name, extra_feature); try all_features.append(extra_feature); } - for (target.extra_cpus) |extra_cpu| { - try all_cpus.append(extra_cpu); + for (target.extra_models) |extra_model| { + try all_models.append(extra_model); } mem.sort(Feature, all_features.items, {}, featureLessThan); - mem.sort(Cpu, all_cpus.items, {}, cpuLessThan); + mem.sort(Model, all_models.items, {}, modelLessThan); const render_progress = progress_node.start("rendering Zig code", 0); @@ -2465,29 +2971,29 @@ fn processOneTargetInner(io: Io, job: Job) !void { \\pub const cpu = struct { \\ ); - for (all_cpus.items) |cpu| { + for (all_models.items) |model| { var deps_set = std.StringHashMap(void).init(arena); - for (cpu.features) |feature_zig_name| { + for (model.features) |feature_zig_name| { try putDep(&deps_set, features_table, feature_zig_name); } try pruneFeatures(arena, features_table, &deps_set); - var cpu_features = std.array_list.Managed([]const u8).init(arena); + var model_features = std.array_list.Managed([]const u8).init(arena); { var it = deps_set.keyIterator(); while (it.next()) |key| { - try cpu_features.append(key.*); + try model_features.append(key.*); } } - mem.sort([]const u8, cpu_features.items, {}, asciiLessThan); - if (cpu.llvm_name) |llvm_name| { + mem.sort([]const u8, model_features.items, {}, asciiLessThan); + if (model.llvm_name) |llvm_name| { try w.print( \\ pub const {f}: CpuModel = .{{ \\ .name = "{f}", \\ .llvm_name = "{f}", \\ .features = featureSet(&[_]Feature{{ , .{ - std.zig.fmtId(cpu.zig_name), - std.zig.fmtString(cpu.zig_name), + std.zig.fmtId(model.zig_name), + std.zig.fmtString(model.zig_name), std.zig.fmtString(llvm_name), }); } else { @@ -2497,11 +3003,11 @@ fn processOneTargetInner(io: Io, job: Job) !void { \\ .llvm_name = null, \\ .features = featureSet(&[_]Feature{{ , .{ - std.zig.fmtId(cpu.zig_name), - std.zig.fmtString(cpu.zig_name), + std.zig.fmtId(model.zig_name), + std.zig.fmtString(model.zig_name), }); } - if (cpu_features.items.len == 0) { + if (model_features.items.len == 0) { try w.writeAll( \\}), \\ }; @@ -2509,7 +3015,7 @@ fn processOneTargetInner(io: Io, job: Job) !void { ); } else { try w.writeAll("\n"); - for (cpu_features.items) |feature_zig_name| { + for (model_features.items) |feature_zig_name| { try w.print(" .{f},\n", .{std.zig.fmtIdPU(feature_zig_name)}); } try w.writeAll( @@ -2547,7 +3053,7 @@ fn featureLessThan(_: void, a: Feature, b: Feature) bool { return std.ascii.lessThanIgnoreCase(a.zig_name, b.zig_name); } -fn cpuLessThan(_: void, a: Cpu, b: Cpu) bool { +fn modelLessThan(_: void, a: Model, b: Model) bool { return std.ascii.lessThanIgnoreCase(a.zig_name, b.zig_name); }