authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2024-05-01 18:57:09-07:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2024-05-08 19:37:29-07:00
loge9efed9ed117c1b6f5fc138999d82e0dbb1f13bf
tree3873bdde6eaa02facc4be8eae8588c92f64599a0
parent7e1cba73fc5dce195af2c5cc6a2a1427710ed3ed

LLVM: zeroext/signext does happen on macos

Fixes a regression introduced in 3ce7fee9dd8bbb6f56e47758a9a8ada028400c71.

1 files changed, 23 insertions(+), 17 deletions(-)

src/codegen/llvm.zig+23-17
......@@ -11577,29 +11577,35 @@ fn ccAbiPromoteInt(
1157711577 .Int, .Enum, .ErrorSet => ty.intInfo(mod),
1157811578 else => return null,
1157911579 };
11580 return switch (target.cpu.arch) {
11581 .riscv64 => switch (int_info.bits) {
11580 return switch (target.os.tag) {
11581 .macos => switch (int_info.bits) {
1158211582 0...16 => int_info.signedness,
11583 32 => .signed, // LLVM always signextends 32 bit ints, unsure if bug.
11584 17...31, 33...63 => int_info.signedness,
1158511583 else => null,
1158611584 },
11585 else => switch (target.cpu.arch) {
11586 .riscv64 => switch (int_info.bits) {
11587 0...16 => int_info.signedness,
11588 32 => .signed, // LLVM always signextends 32 bit ints, unsure if bug.
11589 17...31, 33...63 => int_info.signedness,
11590 else => null,
11591 },
1158711592
11588 .sparc64,
11589 .powerpc64,
11590 .powerpc64le,
11591 => switch (int_info.bits) {
11592 0...63 => int_info.signedness,
11593 else => null,
11594 },
11593 .sparc64,
11594 .powerpc64,
11595 .powerpc64le,
11596 => switch (int_info.bits) {
11597 0...63 => int_info.signedness,
11598 else => null,
11599 },
1159511600
11596 .aarch64,
11597 .aarch64_be,
11598 => null,
11601 .aarch64,
11602 .aarch64_be,
11603 => null,
1159911604
11600 else => switch (int_info.bits) {
11601 0...16 => int_info.signedness,
11602 else => null,
11605 else => switch (int_info.bits) {
11606 0...16 => int_info.signedness,
11607 else => null,
11608 },
1160311609 },
1160411610 };
1160511611}