authorgravatar for david@vortan.devDavid Rubin <david@vortan.dev> 2024-03-29 07:30:04-07:00
committergravatar for david@vortan.devDavid Rubin <david@vortan.dev> 2024-05-11 02:17:11-07:00
logece70e08a09e24ac27f354579ee70446563cc4bf
tree6e20553efa937272c5bcbf9343a45bf1c3ac00cf
parent26ce82d98efce4847307c0b73d1765be7a104256

riscv: pass optionals by register_pair for resolveCallingConventionValues

2 files changed, 4 insertions(+), 14 deletions(-)

src/arch/riscv64/CodeGen.zig+1-8
...@@ -830,7 +830,7 @@ fn splitType(self: *Self, ty: Type) ![2]Type {...@@ -830,7 +830,7 @@ fn splitType(self: *Self, ty: Type) ![2]Type {
830 else => break,830 else => break,
831 };831 };
832 } else if (parts[0].abiSize(mod) + parts[1].abiSize(mod) == ty.abiSize(mod)) return parts;832 } else if (parts[0].abiSize(mod) + parts[1].abiSize(mod) == ty.abiSize(mod)) return parts;
833 return std.debug.panic("TODO implement splitType for {}", .{ty.fmt(mod)});833 return self.fail("TODO implement splitType for {}", .{ty.fmt(mod)});
834}834}
835835
836fn symbolIndex(self: *Self) !u32 {836fn symbolIndex(self: *Self) !u32 {
...@@ -3152,11 +3152,6 @@ fn genCopy(self: *Self, ty: Type, dst_mcv: MCValue, src_mcv: MCValue) !void {...@@ -3152,11 +3152,6 @@ fn genCopy(self: *Self, ty: Type, dst_mcv: MCValue, src_mcv: MCValue) !void {
3152 };3152 };
3153 defer if (src_info) |info| self.register_manager.unlockReg(info.addr_lock);3153 defer if (src_info) |info| self.register_manager.unlockReg(info.addr_lock);
31543154
3155 switch (ty.zigTypeTag(mod)) {
3156 .Optional => return,
3157 else => {},
3158 }
3159
3160 var part_disp: i32 = 0;3155 var part_disp: i32 = 0;
3161 for (dst_regs, try self.splitType(ty), 0..) |dst_reg, dst_ty, part_i| {3156 for (dst_regs, try self.splitType(ty), 0..) |dst_reg, dst_ty, part_i| {
3162 try self.genSetReg(dst_ty, dst_reg, switch (src_mcv) {3157 try self.genSetReg(dst_ty, dst_reg, switch (src_mcv) {
...@@ -3554,8 +3549,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, src_mcv: MCValue) InnerError!...@@ -3554,8 +3549,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, src_mcv: MCValue) InnerError!
3554 },3549 },
3555 },3550 },
3556 });3551 });
3557
3558 unreachable;
3559 },3552 },
3560 .air_ref => |ref| try self.genSetReg(ty, reg, try self.resolveInst(ref)),3553 .air_ref => |ref| try self.genSetReg(ty, reg, try self.resolveInst(ref)),
3561 .indirect => |reg_off| {3554 .indirect => |reg_off| {
src/arch/riscv64/abi.zig+3-6
...@@ -94,10 +94,6 @@ pub fn classifyType(ty: Type, mod: *Module) Class {...@@ -94,10 +94,6 @@ pub fn classifyType(ty: Type, mod: *Module) Class {
94/// There are a maximum of 8 possible return slots. Returned values are in94/// There are a maximum of 8 possible return slots. Returned values are in
95/// the beginning of the array; unused slots are filled with .none.95/// the beginning of the array; unused slots are filled with .none.
96pub fn classifySystemV(ty: Type, mod: *Module) [8]Class {96pub fn classifySystemV(ty: Type, mod: *Module) [8]Class {
97 const memory_class = [_]Class{
98 .memory, .none, .none, .none,
99 .none, .none, .none, .none,
100 };
101 var result = [1]Class{.none} ** 8;97 var result = [1]Class{.none} ** 8;
102 switch (ty.zigTypeTag(mod)) {98 switch (ty.zigTypeTag(mod)) {
103 .Pointer => switch (ty.ptrSize(mod)) {99 .Pointer => switch (ty.ptrSize(mod)) {
...@@ -113,10 +109,11 @@ pub fn classifySystemV(ty: Type, mod: *Module) [8]Class {...@@ -113,10 +109,11 @@ pub fn classifySystemV(ty: Type, mod: *Module) [8]Class {
113 },109 },
114 .Optional => {110 .Optional => {
115 if (ty.isPtrLikeOptional(mod)) {111 if (ty.isPtrLikeOptional(mod)) {
116 result[0] = .integer;
117 return result;112 return result;
118 }113 }
119 return memory_class;114 result[0] = .integer;
115 result[1] = .integer;
116 return result;
120 },117 },
121 else => return result,118 else => return result,
122 }119 }