Commit f014de6456f0cd56d692c2a93c441d83b01796a2 | zig

author	Joachim Schmidt <joachim.schmidt557@outlook.com> 2022-09-18 19:50:06+02:00
committer	Joachim Schmidt <joachim.schmidt557@outlook.com> 2022-09-20 17:14:31+02:00
log	f014de6456f0cd56d692c2a93c441d83b01796a2
tree	f70b1453ad6e2748374cbad4695601763e844679
parent	258b058eecb54e160ac60e72b0354f99f3202bdf
signature	Commit is signed but in an unrecognized format.

stage2 ARM: fix debug info for arguments passed in registers

1 files changed, 27 insertions(+), 29 deletions(-)

src
- arch
  - arm
    CodeGen.zig

src/arch/arm/CodeGen.zig+27-29

 @@ -428,6 +428,28 @@ fn gen(self: *Self) !void {
             self.ret_mcv = MCValue{ .stack_offset = stack_offset };
         }
+        for (self.args) |*arg, arg_index| {
+            // Copy register arguments to the stack
+            switch (arg.*) {
+                .register => |reg| {
+                    // The first AIR instructions of the main body are guaranteed
+                    // to be the functions arguments
+                    const inst = self.air.getMainBody()[arg_index];
+                    assert(self.air.instructions.items(.tag)[inst] == .arg);
+                    const ty = self.air.typeOfIndex(inst);
+                    const abi_size = @intCast(u32, ty.abiSize(self.target.*));
+                    const abi_align = ty.abiAlignment(self.target.*);
+                    const stack_offset = try self.allocMem(abi_size, abi_align, inst);
+                    try self.genSetStack(ty, stack_offset, MCValue{ .register = reg });
+                    arg.* = MCValue{ .stack_offset = stack_offset };
+                },
+                else => {},
+            }
+        }
         _ = try self.addInst(.{
             .tag = .dbg_prologue_end,
             .cond = undefined,
 @@ -3766,7 +3788,8 @@ fn genStrRegister(self: *Self, source_reg: Register, addr_reg: Register, ty: Typ
     const tag: Mir.Inst.Tag = switch (abi_size) {
         1 => .strb,
         2 => .strh,
-        3, 4 => .str,
+        4 => .str,
+        3 => return self.fail("TODO: genStrRegister for abi_size={}", .{abi_size}),
         else => unreachable,
     };
 @@ -3782,7 +3805,7 @@ fn genStrRegister(self: *Self, source_reg: Register, addr_reg: Register, ty: Typ
     } };
     const data: Mir.Inst.Data = switch (abi_size) {
-        1, 3, 4 => rr_offset,
+        1, 4 => rr_offset,
         2 => rr_extra_offset,
         else => unreachable,
     };
 @@ -4047,38 +4070,13 @@ fn airArg(self: *Self, inst: Air.Inst.Index) !void {
     const arg_index = self.arg_index;
     self.arg_index += 1;
-    const ty = self.air.typeOfIndex(inst);
-    const result = self.args[arg_index];
-    const mcv = switch (result) {
-        // Copy registers to the stack
-        .register => |reg| blk: {
-            const abi_size = @intCast(u32, ty.abiSize(self.target.*));
-            const abi_align = ty.abiAlignment(self.target.*);
-            const stack_offset = try self.allocMem(abi_size, abi_align, inst);
-            try self.genSetStack(ty, stack_offset, MCValue{ .register = reg });
-            break :blk MCValue{ .stack_offset = stack_offset };
-        },
-        else => result,
-    };
     try self.dbg_arg_relocs.append(self.gpa, .{
         .inst = inst,
         .index = arg_index,
     });
-    if (self.liveness.isUnused(inst))
+    const result: MCValue = if (self.liveness.isUnused(inst)) .dead else self.args[arg_index];
-        return self.finishAirBookkeeping();
+    return self.finishAir(inst, result, .{ .none, .none, .none });
-    switch (mcv) {
-        .register => |reg| {
-            self.register_manager.getRegAssumeFree(reg, inst);
-        },
-        else => {},
-    }
-    return self.finishAir(inst, mcv, .{ .none, .none, .none });
 }
 fn airBreakpoint(self: *Self) !void {