authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2023-05-03 15:12:20-07:00
committergravatar for noreply@github.comGitHub <noreply@github.com> 2023-05-03 15:12:20-07:00
logf05cd008d89f36da0aaea315dd480edeb7870a45
treebac1c8e73a43ab9a855107776ff3223528426b84
parent8d6336420b937075e3363f9548adb0092af7f819
parenta19faa2481e84e065a8762cb7c7cbf35426929fd
signaturebadge-question-mark Signed by PGP key 4AEE18F83AFDEB23

Merge pull request #15559 from jacobly0/x86_64-behavior

x86_64: more behavior

26 files changed, 403 insertions(+), 291 deletions(-)

src/arch/x86_64/CodeGen.zig+215-97
...@@ -229,6 +229,14 @@ pub const MCValue = union(enum) {...@@ -229,6 +229,14 @@ pub const MCValue = union(enum) {
229 fn isRegister(mcv: MCValue) bool {229 fn isRegister(mcv: MCValue) bool {
230 return switch (mcv) {230 return switch (mcv) {
231 .register => true,231 .register => true,
232 .register_offset => |reg_off| return reg_off.off == 0,
233 else => false,
234 };
235 }
236
237 fn isRegisterOffset(mcv: MCValue) bool {
238 return switch (mcv) {
239 .register, .register_offset => true,
232 else => false,240 else => false,
233 };241 };
234 }242 }
...@@ -1202,6 +1210,28 @@ fn asmRegisterMemory(self: *Self, tag: Mir.Inst.Tag, reg: Register, m: Memory) !...@@ -1202,6 +1210,28 @@ fn asmRegisterMemory(self: *Self, tag: Mir.Inst.Tag, reg: Register, m: Memory) !
1202 });1210 });
1203}1211}
12041212
1213fn asmRegisterMemoryImmediate(
1214 self: *Self,
1215 tag: Mir.Inst.Tag,
1216 reg: Register,
1217 m: Memory,
1218 imm: Immediate,
1219) !void {
1220 _ = try self.addInst(.{
1221 .tag = tag,
1222 .ops = switch (m) {
1223 .sib => .rmi_sib,
1224 .rip => .rmi_rip,
1225 else => unreachable,
1226 },
1227 .data = .{ .rix = .{ .r = reg, .i = @intCast(u8, imm.unsigned), .payload = switch (m) {
1228 .sib => try self.addExtra(Mir.MemorySib.encode(m)),
1229 .rip => try self.addExtra(Mir.MemoryRip.encode(m)),
1230 else => unreachable,
1231 } } },
1232 });
1233}
1234
1205fn asmMemoryRegister(self: *Self, tag: Mir.Inst.Tag, m: Memory, reg: Register) !void {1235fn asmMemoryRegister(self: *Self, tag: Mir.Inst.Tag, m: Memory, reg: Register) !void {
1206 _ = try self.addInst(.{1236 _ = try self.addInst(.{
1207 .tag = tag,1237 .tag = tag,
...@@ -1442,7 +1472,6 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {...@@ -1442,7 +1472,6 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
1442 .shl_sat => try self.airShlSat(inst),1472 .shl_sat => try self.airShlSat(inst),
1443 .slice => try self.airSlice(inst),1473 .slice => try self.airSlice(inst),
14441474
1445 .sqrt,
1446 .sin,1475 .sin,
1447 .cos,1476 .cos,
1448 .tan,1477 .tan,
...@@ -1451,14 +1480,14 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {...@@ -1451,14 +1480,14 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
1451 .log,1480 .log,
1452 .log2,1481 .log2,
1453 .log10,1482 .log10,
1454 .fabs,
1455 .floor,1483 .floor,
1456 .ceil,1484 .ceil,
1457 .round,1485 .round,
1458 .trunc_float,1486 .trunc_float,
1459 => try self.airUnaryMath(inst),1487 => try self.airUnaryMath(inst),
14601488
1461 .neg => try self.airNeg(inst),1489 .sqrt => try self.airSqrt(inst),
1490 .neg, .fabs => try self.airFloatSign(inst),
14621491
1463 .add_with_overflow => try self.airAddSubWithOverflow(inst),1492 .add_with_overflow => try self.airAddSubWithOverflow(inst),
1464 .sub_with_overflow => try self.airAddSubWithOverflow(inst),1493 .sub_with_overflow => try self.airAddSubWithOverflow(inst),
...@@ -1944,7 +1973,7 @@ fn allocRegOrMemAdvanced(self: *Self, elem_ty: Type, inst: ?Air.Inst.Index, reg_...@@ -1944,7 +1973,7 @@ fn allocRegOrMemAdvanced(self: *Self, elem_ty: Type, inst: ?Air.Inst.Index, reg_
1944 const ptr_bits = self.target.cpu.arch.ptrBitWidth();1973 const ptr_bits = self.target.cpu.arch.ptrBitWidth();
1945 const ptr_bytes: u64 = @divExact(ptr_bits, 8);1974 const ptr_bytes: u64 = @divExact(ptr_bits, 8);
1946 if (abi_size <= ptr_bytes) {1975 if (abi_size <= ptr_bytes) {
1947 if (self.register_manager.tryAllocReg(inst, try self.regClassForType(elem_ty))) |reg| {1976 if (self.register_manager.tryAllocReg(inst, regClassForType(elem_ty))) |reg| {
1948 return MCValue{ .register = registerAlias(reg, abi_size) };1977 return MCValue{ .register = registerAlias(reg, abi_size) };
1949 }1978 }
1950 }1979 }
...@@ -1954,14 +1983,9 @@ fn allocRegOrMemAdvanced(self: *Self, elem_ty: Type, inst: ?Air.Inst.Index, reg_...@@ -1954,14 +1983,9 @@ fn allocRegOrMemAdvanced(self: *Self, elem_ty: Type, inst: ?Air.Inst.Index, reg_
1954 return .{ .load_frame = .{ .index = frame_index } };1983 return .{ .load_frame = .{ .index = frame_index } };
1955}1984}
19561985
1957fn regClassForType(self: *Self, ty: Type) !RegisterManager.RegisterBitSet {1986fn regClassForType(ty: Type) RegisterManager.RegisterBitSet {
1958 return switch (ty.zigTypeTag()) {1987 return switch (ty.zigTypeTag()) {
1959 .Vector => self.fail("TODO regClassForType for {}", .{ty.fmt(self.bin_file.options.module.?)}),1988 .Float, .Vector => sse,
1960 .Float => switch (ty.floatBits(self.target.*)) {
1961 32 => if (Target.x86.featureSetHas(self.target.cpu.features, .sse)) sse else gp,
1962 64 => if (Target.x86.featureSetHas(self.target.cpu.features, .sse2)) sse else gp,
1963 else => gp,
1964 },
1965 else => gp,1989 else => gp,
1966 };1990 };
1967}1991}
...@@ -2104,7 +2128,7 @@ pub fn spillRegisters(self: *Self, registers: []const Register) !void {...@@ -2104,7 +2128,7 @@ pub fn spillRegisters(self: *Self, registers: []const Register) !void {
2104/// allocated. A second call to `copyToTmpRegister` may return the same register.2128/// allocated. A second call to `copyToTmpRegister` may return the same register.
2105/// This can have a side effect of spilling instructions to the stack to free up a register.2129/// This can have a side effect of spilling instructions to the stack to free up a register.
2106fn copyToTmpRegister(self: *Self, ty: Type, mcv: MCValue) !Register {2130fn copyToTmpRegister(self: *Self, ty: Type, mcv: MCValue) !Register {
2107 const reg = try self.register_manager.allocReg(null, try self.regClassForType(ty));2131 const reg = try self.register_manager.allocReg(null, regClassForType(ty));
2108 try self.genSetReg(reg, ty, mcv);2132 try self.genSetReg(reg, ty, mcv);
2109 return reg;2133 return reg;
2110}2134}
...@@ -2119,7 +2143,7 @@ fn copyToRegisterWithInstTracking(...@@ -2119,7 +2143,7 @@ fn copyToRegisterWithInstTracking(
2119 ty: Type,2143 ty: Type,
2120 mcv: MCValue,2144 mcv: MCValue,
2121) !MCValue {2145) !MCValue {
2122 const reg: Register = try self.register_manager.allocReg(reg_owner, try self.regClassForType(ty));2146 const reg: Register = try self.register_manager.allocReg(reg_owner, regClassForType(ty));
2123 try self.genSetReg(reg, ty, mcv);2147 try self.genSetReg(reg, ty, mcv);
2124 return MCValue{ .register = reg };2148 return MCValue{ .register = reg };
2125}2149}
...@@ -2152,8 +2176,7 @@ fn airFptrunc(self: *Self, inst: Air.Inst.Index) !void {...@@ -2152,8 +2176,7 @@ fn airFptrunc(self: *Self, inst: Air.Inst.Index) !void {
2152 if (dst_ty.floatBits(self.target.*) != 32 or src_ty.floatBits(self.target.*) != 64 or2176 if (dst_ty.floatBits(self.target.*) != 32 or src_ty.floatBits(self.target.*) != 64 or
2153 !Target.x86.featureSetHas(self.target.cpu.features, .sse2))2177 !Target.x86.featureSetHas(self.target.cpu.features, .sse2))
2154 return self.fail("TODO implement airFptrunc from {} to {}", .{2178 return self.fail("TODO implement airFptrunc from {} to {}", .{
2155 src_ty.fmt(self.bin_file.options.module.?),2179 src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
2156 dst_ty.fmt(self.bin_file.options.module.?),
2157 });2180 });
21582181
2159 const src_mcv = try self.resolveInst(ty_op.operand);2182 const src_mcv = try self.resolveInst(ty_op.operand);
...@@ -2175,8 +2198,7 @@ fn airFpext(self: *Self, inst: Air.Inst.Index) !void {...@@ -2175,8 +2198,7 @@ fn airFpext(self: *Self, inst: Air.Inst.Index) !void {
2175 if (dst_ty.floatBits(self.target.*) != 64 or src_ty.floatBits(self.target.*) != 32 or2198 if (dst_ty.floatBits(self.target.*) != 64 or src_ty.floatBits(self.target.*) != 32 or
2176 !Target.x86.featureSetHas(self.target.cpu.features, .sse2))2199 !Target.x86.featureSetHas(self.target.cpu.features, .sse2))
2177 return self.fail("TODO implement airFpext from {} to {}", .{2200 return self.fail("TODO implement airFpext from {} to {}", .{
2178 src_ty.fmt(self.bin_file.options.module.?),2201 src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
2179 dst_ty.fmt(self.bin_file.options.module.?),
2180 });2202 });
21812203
2182 const src_mcv = try self.resolveInst(ty_op.operand);2204 const src_mcv = try self.resolveInst(ty_op.operand);
...@@ -3502,17 +3524,7 @@ fn genSliceElemPtr(self: *Self, lhs: Air.Inst.Ref, rhs: Air.Inst.Ref) !MCValue {...@@ -3502,17 +3524,7 @@ fn genSliceElemPtr(self: *Self, lhs: Air.Inst.Ref, rhs: Air.Inst.Ref) !MCValue {
3502 defer self.register_manager.unlockReg(offset_reg_lock);3524 defer self.register_manager.unlockReg(offset_reg_lock);
35033525
3504 const addr_reg = try self.register_manager.allocReg(null, gp);3526 const addr_reg = try self.register_manager.allocReg(null, gp);
3505 switch (slice_mcv) {3527 try self.genSetReg(addr_reg, Type.usize, slice_mcv);
3506 .load_frame => |frame_addr| try self.asmRegisterMemory(
3507 .mov,
3508 addr_reg.to64(),
3509 Memory.sib(.qword, .{
3510 .base = .{ .frame = frame_addr.index },
3511 .disp = frame_addr.off,
3512 }),
3513 ),
3514 else => return self.fail("TODO implement slice_elem_ptr when slice is {}", .{slice_mcv}),
3515 }
3516 // TODO we could allocate register here, but need to expect addr register and potentially3528 // TODO we could allocate register here, but need to expect addr register and potentially
3517 // offset register.3529 // offset register.
3518 try self.genBinOpMir(.add, slice_ptr_field_type, .{ .register = addr_reg }, .{3530 try self.genBinOpMir(.add, slice_ptr_field_type, .{ .register = addr_reg }, .{
...@@ -4188,7 +4200,7 @@ fn airBitReverse(self: *Self, inst: Air.Inst.Index) !void {...@@ -4188,7 +4200,7 @@ fn airBitReverse(self: *Self, inst: Air.Inst.Index) !void {
4188 return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });4200 return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });
4189}4201}
41904202
4191fn airNeg(self: *Self, inst: Air.Inst.Index) !void {4203fn airFloatSign(self: *Self, inst: Air.Inst.Index) !void {
4192 const un_op = self.air.instructions.items(.data)[inst].un_op;4204 const un_op = self.air.instructions.items(.data)[inst].un_op;
4193 const ty = self.air.typeOf(un_op);4205 const ty = self.air.typeOf(un_op);
4194 const ty_bits = ty.floatBits(self.target.*);4206 const ty_bits = ty.floatBits(self.target.*);
...@@ -4231,16 +4243,46 @@ fn airNeg(self: *Self, inst: Air.Inst.Index) !void {...@@ -4231,16 +4243,46 @@ fn airNeg(self: *Self, inst: Air.Inst.Index) !void {
4231 const dst_lock = self.register_manager.lockReg(dst_mcv.register);4243 const dst_lock = self.register_manager.lockReg(dst_mcv.register);
4232 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);4244 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
42334245
4246 const tag = self.air.instructions.items(.tag)[inst];
4234 try self.genBinOpMir(switch (ty_bits) {4247 try self.genBinOpMir(switch (ty_bits) {
4235 32 => .xorps,4248 // No point using an extra prefix byte for *pd which performs the same operation.
4236 64 => .xorpd,4249 32, 64 => switch (tag) {
4237 else => return self.fail("TODO implement airNeg for {}", .{4250 .neg => .xorps,
4251 .fabs => .andnps,
4252 else => unreachable,
4253 },
4254 else => return self.fail("TODO implement airFloatSign for {}", .{
4238 ty.fmt(self.bin_file.options.module.?),4255 ty.fmt(self.bin_file.options.module.?),
4239 }),4256 }),
4240 }, vec_ty, dst_mcv, sign_mcv);4257 }, vec_ty, dst_mcv, sign_mcv);
4241 return self.finishAir(inst, dst_mcv, .{ un_op, .none, .none });4258 return self.finishAir(inst, dst_mcv, .{ un_op, .none, .none });
4242}4259}
42434260
4261fn airSqrt(self: *Self, inst: Air.Inst.Index) !void {
4262 const un_op = self.air.instructions.items(.data)[inst].un_op;
4263 const ty = self.air.typeOf(un_op);
4264
4265 const src_mcv = try self.resolveInst(un_op);
4266 const dst_mcv = if (src_mcv.isRegister() and self.reuseOperand(inst, un_op, 0, src_mcv))
4267 src_mcv
4268 else
4269 try self.copyToRegisterWithInstTracking(inst, ty, src_mcv);
4270
4271 try self.genBinOpMir(switch (ty.zigTypeTag()) {
4272 .Float => switch (ty.floatBits(self.target.*)) {
4273 32 => .sqrtss,
4274 64 => .sqrtsd,
4275 else => return self.fail("TODO implement airSqrt for {}", .{
4276 ty.fmt(self.bin_file.options.module.?),
4277 }),
4278 },
4279 else => return self.fail("TODO implement airSqrt for {}", .{
4280 ty.fmt(self.bin_file.options.module.?),
4281 }),
4282 }, ty, dst_mcv, src_mcv);
4283 return self.finishAir(inst, dst_mcv, .{ un_op, .none, .none });
4284}
4285
4244fn airUnaryMath(self: *Self, inst: Air.Inst.Index) !void {4286fn airUnaryMath(self: *Self, inst: Air.Inst.Index) !void {
4245 const un_op = self.air.instructions.items(.data)[inst].un_op;4287 const un_op = self.air.instructions.items(.data)[inst].un_op;
4246 _ = un_op;4288 _ = un_op;
...@@ -4409,8 +4451,8 @@ fn airLoad(self: *Self, inst: Air.Inst.Index) !void {...@@ -4409,8 +4451,8 @@ fn airLoad(self: *Self, inst: Air.Inst.Index) !void {
4409 const ptr_ty = self.air.typeOf(ty_op.operand);4451 const ptr_ty = self.air.typeOf(ty_op.operand);
4410 const elem_size = elem_ty.abiSize(self.target.*);4452 const elem_size = elem_ty.abiSize(self.target.*);
44114453
4412 const elem_rc = try self.regClassForType(elem_ty);4454 const elem_rc = regClassForType(elem_ty);
4413 const ptr_rc = try self.regClassForType(ptr_ty);4455 const ptr_rc = regClassForType(ptr_ty);
44144456
4415 const ptr_mcv = try self.resolveInst(ty_op.operand);4457 const ptr_mcv = try self.resolveInst(ty_op.operand);
4416 const dst_mcv = if (elem_size <= 8 and elem_rc.supersetOf(ptr_rc) and4458 const dst_mcv = if (elem_size <= 8 and elem_rc.supersetOf(ptr_rc) and
...@@ -4782,10 +4824,21 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {...@@ -4782,10 +4824,21 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
4782}4824}
47834825
4784fn airFieldParentPtr(self: *Self, inst: Air.Inst.Index) !void {4826fn airFieldParentPtr(self: *Self, inst: Air.Inst.Index) !void {
4785 const ty_op = self.air.instructions.items(.data)[inst].ty_op;4827 const ty_pl = self.air.instructions.items(.data)[inst].ty_pl;
4786 _ = ty_op;4828 const extra = self.air.extraData(Air.FieldParentPtr, ty_pl.payload).data;
4787 return self.fail("TODO implement airFieldParentPtr for {}", .{self.target.cpu.arch});4829
4788 //return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });4830 const inst_ty = self.air.typeOfIndex(inst);
4831 const parent_ty = inst_ty.childType();
4832 const field_offset = @intCast(i32, parent_ty.structFieldOffset(extra.field_index, self.target.*));
4833
4834 const src_mcv = try self.resolveInst(extra.field_ptr);
4835 const dst_mcv = if (src_mcv.isRegisterOffset() and
4836 self.reuseOperand(inst, extra.field_ptr, 0, src_mcv))
4837 src_mcv
4838 else
4839 try self.copyToRegisterWithInstTracking(inst, inst_ty, src_mcv);
4840 const result = dst_mcv.offset(-field_offset);
4841 return self.finishAir(inst, result, .{ extra.field_ptr, .none, .none });
4789}4842}
47904843
4791fn genUnOp(self: *Self, maybe_inst: ?Air.Inst.Index, tag: Air.Inst.Tag, src_air: Air.Inst.Ref) !MCValue {4844fn genUnOp(self: *Self, maybe_inst: ?Air.Inst.Index, tag: Air.Inst.Tag, src_air: Air.Inst.Ref) !MCValue {
...@@ -5219,8 +5272,7 @@ fn genMulDivBinOp(...@@ -5219,8 +5272,7 @@ fn genMulDivBinOp(
5219 .mul, .mulwrap => dst_abi_size != src_abi_size and dst_abi_size != src_abi_size * 2,5272 .mul, .mulwrap => dst_abi_size != src_abi_size and dst_abi_size != src_abi_size * 2,
5220 .div_trunc, .div_floor, .div_exact, .rem, .mod => dst_abi_size != src_abi_size,5273 .div_trunc, .div_floor, .div_exact, .rem, .mod => dst_abi_size != src_abi_size,
5221 } or src_abi_size > 8) return self.fail("TODO implement genMulDivBinOp from {} to {}", .{5274 } or src_abi_size > 8) return self.fail("TODO implement genMulDivBinOp from {} to {}", .{
5222 src_ty.fmt(self.bin_file.options.module.?),5275 src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
5223 dst_ty.fmt(self.bin_file.options.module.?),
5224 });5276 });
5225 const ty = if (dst_abi_size <= 8) dst_ty else src_ty;5277 const ty = if (dst_abi_size <= 8) dst_ty else src_ty;
5226 const abi_size = if (dst_abi_size <= 8) dst_abi_size else src_abi_size;5278 const abi_size = if (dst_abi_size <= 8) dst_abi_size else src_abi_size;
...@@ -5520,7 +5572,9 @@ fn genBinOp(...@@ -5520,7 +5572,9 @@ fn genBinOp(
5520 }, lhs_ty, dst_mcv, src_mcv),5572 }, lhs_ty, dst_mcv, src_mcv),
55215573
5522 .mul => try self.genBinOpMir(switch (lhs_ty.zigTypeTag()) {5574 .mul => try self.genBinOpMir(switch (lhs_ty.zigTypeTag()) {
5523 else => return self.fail("TODO implement genBinOp for {s} {}", .{ @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?) }),5575 else => return self.fail("TODO implement genBinOp for {s} {}", .{
5576 @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?),
5577 }),
5524 .Float => switch (lhs_ty.floatBits(self.target.*)) {5578 .Float => switch (lhs_ty.floatBits(self.target.*)) {
5525 32 => if (Target.x86.featureSetHas(self.target.cpu.features, .sse))5579 32 => if (Target.x86.featureSetHas(self.target.cpu.features, .sse))
5526 .mulss5580 .mulss
...@@ -5723,9 +5777,13 @@ fn genBinOp(...@@ -5723,9 +5777,13 @@ fn genBinOp(
5723 .max => .maxsd,5777 .max => .maxsd,
5724 else => unreachable,5778 else => unreachable,
5725 },5779 },
5726 else => return self.fail("TODO implement genBinOp for {s} {}", .{ @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?) }),5780 else => return self.fail("TODO implement genBinOp for {s} {}", .{
5781 @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?),
5782 }),
5727 }, lhs_ty, dst_mcv, src_mcv),5783 }, lhs_ty, dst_mcv, src_mcv),
5728 else => return self.fail("TODO implement genBinOp for {s} {}", .{ @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?) }),5784 else => return self.fail("TODO implement genBinOp for {s} {}", .{
5785 @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?),
5786 }),
5729 },5787 },
57305788
5731 else => unreachable,5789 else => unreachable,
...@@ -5764,8 +5822,7 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, ty: Type, dst_mcv: MCValue, s...@@ -5764,8 +5822,7 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, ty: Type, dst_mcv: MCValue, s
5764 .Float => {5822 .Float => {
5765 if (!Target.x86.featureSetHas(self.target.cpu.features, .sse))5823 if (!Target.x86.featureSetHas(self.target.cpu.features, .sse))
5766 return self.fail("TODO genBinOpMir for {s} {} without sse", .{5824 return self.fail("TODO genBinOpMir for {s} {} without sse", .{
5767 @tagName(mir_tag),5825 @tagName(mir_tag), ty.fmt(self.bin_file.options.module.?),
5768 ty.fmt(self.bin_file.options.module.?),
5769 });5826 });
5770 return self.asmRegisterRegister(mir_tag, dst_reg.to128(), src_reg.to128());5827 return self.asmRegisterRegister(mir_tag, dst_reg.to128(), src_reg.to128());
5771 },5828 },
...@@ -5863,7 +5920,12 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, ty: Type, dst_mcv: MCValue, s...@@ -5863,7 +5920,12 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, ty: Type, dst_mcv: MCValue, s
5863 .load_got,5920 .load_got,
5864 .load_tlv,5921 .load_tlv,
5865 => {5922 => {
5866 const addr_reg = try self.copyToTmpRegister(ty, src_mcv.address());5923 var ptr_pl = Type.Payload.ElemType{
5924 .base = .{ .tag = .single_const_pointer },
5925 .data = ty,
5926 };
5927 const ptr_ty = Type.initPayload(&ptr_pl.base);
5928 const addr_reg = try self.copyToTmpRegister(ptr_ty, src_mcv.address());
5867 return self.genBinOpMir(mir_tag, ty, dst_mcv, .{5929 return self.genBinOpMir(mir_tag, ty, dst_mcv, .{
5868 .indirect = .{ .reg = addr_reg },5930 .indirect = .{ .reg = addr_reg },
5869 });5931 });
...@@ -7545,10 +7607,11 @@ fn movMirTag(self: *Self, ty: Type) !Mir.Inst.Tag {...@@ -7545,10 +7607,11 @@ fn movMirTag(self: *Self, ty: Type) !Mir.Inst.Tag {
7545 return switch (ty.zigTypeTag()) {7607 return switch (ty.zigTypeTag()) {
7546 else => .mov,7608 else => .mov,
7547 .Float => switch (ty.floatBits(self.target.*)) {7609 .Float => switch (ty.floatBits(self.target.*)) {
7548 16 => .mov,7610 16 => unreachable, // needs special handling
7549 32 => if (Target.x86.featureSetHas(self.target.cpu.features, .sse)) .movss else .mov,7611 32 => .movss,
7550 64 => if (Target.x86.featureSetHas(self.target.cpu.features, .sse2)) .movsd else .mov,7612 64 => .movsd,
7551 else => return self.fail("TODO movMirTag for {}", .{7613 128 => .movaps,
7614 else => return self.fail("TODO movMirTag from {}", .{
7552 ty.fmt(self.bin_file.options.module.?),7615 ty.fmt(self.bin_file.options.module.?),
7553 }),7616 }),
7554 },7617 },
...@@ -7657,8 +7720,17 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr...@@ -7657,8 +7720,17 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
7657 },7720 },
7658 .register => |src_reg| if (dst_reg.id() != src_reg.id()) try self.asmRegisterRegister(7721 .register => |src_reg| if (dst_reg.id() != src_reg.id()) try self.asmRegisterRegister(
7659 if ((dst_reg.class() == .floating_point) == (src_reg.class() == .floating_point))7722 if ((dst_reg.class() == .floating_point) == (src_reg.class() == .floating_point))
7660 try self.movMirTag(ty)7723 switch (ty.zigTypeTag()) {
7724 else => .mov,
7725 .Float, .Vector => .movaps,
7726 }
7661 else switch (abi_size) {7727 else switch (abi_size) {
7728 2 => return try self.asmRegisterRegisterImmediate(
7729 if (dst_reg.class() == .floating_point) .pinsrw else .pextrw,
7730 registerAlias(dst_reg, abi_size),
7731 registerAlias(src_reg, abi_size),
7732 Immediate.u(0),
7733 ),
7662 4 => .movd,7734 4 => .movd,
7663 8 => .movq,7735 8 => .movq,
7664 else => return self.fail(7736 else => return self.fail(
...@@ -7669,18 +7741,12 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr...@@ -7669,18 +7741,12 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
7669 registerAlias(dst_reg, abi_size),7741 registerAlias(dst_reg, abi_size),
7670 registerAlias(src_reg, abi_size),7742 registerAlias(src_reg, abi_size),
7671 ),7743 ),
7672 .register_offset, .indirect, .load_frame, .lea_frame => try self.asmRegisterMemory(7744 .register_offset,
7673 switch (src_mcv) {7745 .indirect,
7674 .register_offset => |reg_off| switch (reg_off.off) {7746 .load_frame,
7675 0 => return self.genSetReg(dst_reg, ty, .{ .register = reg_off.reg }),7747 .lea_frame,
7676 else => .lea,7748 => {
7677 },7749 const src_mem = Memory.sib(Memory.PtrSize.fromSize(abi_size), switch (src_mcv) {
7678 .indirect, .load_frame => try self.movMirTag(ty),
7679 .lea_frame => .lea,
7680 else => unreachable,
7681 },
7682 registerAlias(dst_reg, abi_size),
7683 Memory.sib(Memory.PtrSize.fromSize(abi_size), switch (src_mcv) {
7684 .register_offset, .indirect => |reg_off| .{7750 .register_offset, .indirect => |reg_off| .{
7685 .base = .{ .reg = reg_off.reg },7751 .base = .{ .reg = reg_off.reg },
7686 .disp = reg_off.off,7752 .disp = reg_off.off,
...@@ -7690,20 +7756,51 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr...@@ -7690,20 +7756,51 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
7690 .disp = frame_addr.off,7756 .disp = frame_addr.off,
7691 },7757 },
7692 else => unreachable,7758 else => unreachable,
7693 }),7759 });
7694 ),7760 if (ty.isRuntimeFloat() and ty.floatBits(self.target.*) == 16)
7761 try self.asmRegisterMemoryImmediate(
7762 .pinsrw,
7763 registerAlias(dst_reg, abi_size),
7764 src_mem,
7765 Immediate.u(0),
7766 )
7767 else
7768 try self.asmRegisterMemory(
7769 switch (src_mcv) {
7770 .register_offset => |reg_off| switch (reg_off.off) {
7771 0 => return self.genSetReg(dst_reg, ty, .{ .register = reg_off.reg }),
7772 else => .lea,
7773 },
7774 .indirect, .load_frame => try self.movMirTag(ty),
7775 .lea_frame => .lea,
7776 else => unreachable,
7777 },
7778 registerAlias(dst_reg, abi_size),
7779 src_mem,
7780 );
7781 },
7695 .memory, .load_direct, .load_got, .load_tlv => {7782 .memory, .load_direct, .load_got, .load_tlv => {
7696 switch (src_mcv) {7783 switch (src_mcv) {
7697 .memory => |addr| if (math.cast(i32, @bitCast(i64, addr))) |small_addr|7784 .memory => |addr| if (math.cast(i32, @bitCast(i64, addr))) |small_addr| {
7698 return self.asmRegisterMemory(7785 const src_mem = Memory.sib(Memory.PtrSize.fromSize(abi_size), .{
7699 try self.movMirTag(ty),7786 .base = .{ .reg = .ds },
7700 registerAlias(dst_reg, abi_size),7787 .disp = small_addr,
7701 Memory.sib(Memory.PtrSize.fromSize(abi_size), .{7788 });
7702 .base = .{ .reg = .ds },7789 return if (ty.isRuntimeFloat() and ty.floatBits(self.target.*) == 16)
7703 .disp = small_addr,7790 self.asmRegisterMemoryImmediate(
7704 }),7791 .pinsrw,
7705 ),7792 registerAlias(dst_reg, abi_size),
7706 .load_direct => |sym_index| if (try self.movMirTag(ty) == .mov) {7793 src_mem,
7794 Immediate.u(0),
7795 )
7796 else
7797 self.asmRegisterMemory(
7798 try self.movMirTag(ty),
7799 registerAlias(dst_reg, abi_size),
7800 src_mem,
7801 );
7802 },
7803 .load_direct => |sym_index| if (!ty.isRuntimeFloat()) {
7707 const atom_index = try self.owner.getSymbolIndex(self);7804 const atom_index = try self.owner.getSymbolIndex(self);
7708 _ = try self.addInst(.{7805 _ = try self.addInst(.{
7709 .tag = .mov_linker,7806 .tag = .mov_linker,
...@@ -7724,11 +7821,22 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr...@@ -7724,11 +7821,22 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
7724 const addr_lock = self.register_manager.lockRegAssumeUnused(addr_reg);7821 const addr_lock = self.register_manager.lockRegAssumeUnused(addr_reg);
7725 defer self.register_manager.unlockReg(addr_lock);7822 defer self.register_manager.unlockReg(addr_lock);
77267823
7727 try self.asmRegisterMemory(7824 const src_mem = Memory.sib(Memory.PtrSize.fromSize(abi_size), .{
7728 try self.movMirTag(ty),7825 .base = .{ .reg = addr_reg },
7729 registerAlias(dst_reg, abi_size),7826 });
7730 Memory.sib(Memory.PtrSize.fromSize(abi_size), .{ .base = .{ .reg = addr_reg } }),7827 if (ty.isRuntimeFloat() and ty.floatBits(self.target.*) == 16)
7731 );7828 try self.asmRegisterMemoryImmediate(
7829 .pinsrw,
7830 registerAlias(dst_reg, abi_size),
7831 src_mem,
7832 Immediate.u(0),
7833 )
7834 else
7835 try self.asmRegisterMemory(
7836 try self.movMirTag(ty),
7837 registerAlias(dst_reg, abi_size),
7838 src_mem,
7839 );
7732 },7840 },
7733 .lea_direct, .lea_got => |sym_index| {7841 .lea_direct, .lea_got => |sym_index| {
7734 const atom_index = try self.owner.getSymbolIndex(self);7842 const atom_index = try self.owner.getSymbolIndex(self);
...@@ -7821,11 +7929,25 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal...@@ -7821,11 +7929,25 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal
7821 },7929 },
7822 },7930 },
7823 .eflags => |cc| try self.asmSetccMemory(Memory.sib(.byte, .{ .base = base, .disp = disp }), cc),7931 .eflags => |cc| try self.asmSetccMemory(Memory.sib(.byte, .{ .base = base, .disp = disp }), cc),
7824 .register => |reg| try self.asmMemoryRegister(7932 .register => |src_reg| {
7825 try self.movMirTag(ty),7933 const dst_mem = Memory.sib(
7826 Memory.sib(Memory.PtrSize.fromSize(abi_size), .{ .base = base, .disp = disp }),7934 Memory.PtrSize.fromSize(abi_size),
7827 registerAlias(reg, abi_size),7935 .{ .base = base, .disp = disp },
7828 ),7936 );
7937 if (ty.isRuntimeFloat() and ty.floatBits(self.target.*) == 16)
7938 try self.asmMemoryRegisterImmediate(
7939 .pextrw,
7940 dst_mem,
7941 registerAlias(src_reg, abi_size),
7942 Immediate.u(0),
7943 )
7944 else
7945 try self.asmMemoryRegister(
7946 try self.movMirTag(ty),
7947 dst_mem,
7948 registerAlias(src_reg, abi_size),
7949 );
7950 },
7829 .register_overflow => |ro| {7951 .register_overflow => |ro| {
7830 try self.genSetMem(7952 try self.genSetMem(
7831 base,7953 base,
...@@ -8028,8 +8150,8 @@ fn airBitCast(self: *Self, inst: Air.Inst.Index) !void {...@@ -8028,8 +8150,8 @@ fn airBitCast(self: *Self, inst: Air.Inst.Index) !void {
8028 const src_ty = self.air.typeOf(ty_op.operand);8150 const src_ty = self.air.typeOf(ty_op.operand);
80298151
8030 const result = result: {8152 const result = result: {
8031 const dst_rc = try self.regClassForType(dst_ty);8153 const dst_rc = regClassForType(dst_ty);
8032 const src_rc = try self.regClassForType(src_ty);8154 const src_rc = regClassForType(src_ty);
8033 const operand = try self.resolveInst(ty_op.operand);8155 const operand = try self.resolveInst(ty_op.operand);
8034 if (dst_rc.supersetOf(src_rc) and self.reuseOperand(inst, ty_op.operand, 0, operand))8156 if (dst_rc.supersetOf(src_rc) and self.reuseOperand(inst, ty_op.operand, 0, operand))
8035 break :result operand;8157 break :result operand;
...@@ -8084,8 +8206,7 @@ fn airIntToFloat(self: *Self, inst: Air.Inst.Index) !void {...@@ -8084,8 +8206,7 @@ fn airIntToFloat(self: *Self, inst: Air.Inst.Index) !void {
8084 .unsigned => src_bits + 1,8206 .unsigned => src_bits + 1,
8085 }, 32), 8) catch unreachable;8207 }, 32), 8) catch unreachable;
8086 if (src_size > 8) return self.fail("TODO implement airIntToFloat from {} to {}", .{8208 if (src_size > 8) return self.fail("TODO implement airIntToFloat from {} to {}", .{
8087 src_ty.fmt(self.bin_file.options.module.?),8209 src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
8088 dst_ty.fmt(self.bin_file.options.module.?),
8089 });8210 });
80908211
8091 const src_mcv = try self.resolveInst(ty_op.operand);8212 const src_mcv = try self.resolveInst(ty_op.operand);
...@@ -8098,7 +8219,7 @@ fn airIntToFloat(self: *Self, inst: Air.Inst.Index) !void {...@@ -8098,7 +8219,7 @@ fn airIntToFloat(self: *Self, inst: Air.Inst.Index) !void {
80988219
8099 if (src_bits < src_size * 8) try self.truncateRegister(src_ty, src_reg);8220 if (src_bits < src_size * 8) try self.truncateRegister(src_ty, src_reg);
81008221
8101 const dst_reg = try self.register_manager.allocReg(inst, try self.regClassForType(dst_ty));8222 const dst_reg = try self.register_manager.allocReg(inst, regClassForType(dst_ty));
8102 const dst_mcv = MCValue{ .register = dst_reg };8223 const dst_mcv = MCValue{ .register = dst_reg };
8103 const dst_lock = self.register_manager.lockRegAssumeUnused(dst_reg);8224 const dst_lock = self.register_manager.lockRegAssumeUnused(dst_reg);
8104 defer self.register_manager.unlockReg(dst_lock);8225 defer self.register_manager.unlockReg(dst_lock);
...@@ -8108,19 +8229,16 @@ fn airIntToFloat(self: *Self, inst: Air.Inst.Index) !void {...@@ -8108,19 +8229,16 @@ fn airIntToFloat(self: *Self, inst: Air.Inst.Index) !void {
8108 .cvtsi2ss8229 .cvtsi2ss
8109 else8230 else
8110 return self.fail("TODO implement airIntToFloat from {} to {} without sse", .{8231 return self.fail("TODO implement airIntToFloat from {} to {} without sse", .{
8111 src_ty.fmt(self.bin_file.options.module.?),8232 src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
8112 dst_ty.fmt(self.bin_file.options.module.?),
8113 }),8233 }),
8114 64 => if (Target.x86.featureSetHas(self.target.cpu.features, .sse2))8234 64 => if (Target.x86.featureSetHas(self.target.cpu.features, .sse2))
8115 .cvtsi2sd8235 .cvtsi2sd
8116 else8236 else
8117 return self.fail("TODO implement airIntToFloat from {} to {} without sse2", .{8237 return self.fail("TODO implement airIntToFloat from {} to {} without sse2", .{
8118 src_ty.fmt(self.bin_file.options.module.?),8238 src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
8119 dst_ty.fmt(self.bin_file.options.module.?),
8120 }),8239 }),
8121 else => return self.fail("TODO implement airIntToFloat from {} to {}", .{8240 else => return self.fail("TODO implement airIntToFloat from {} to {}", .{
8122 src_ty.fmt(self.bin_file.options.module.?),8241 src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
8123 dst_ty.fmt(self.bin_file.options.module.?),
8124 }),8242 }),
8125 }, dst_reg.to128(), registerAlias(src_reg, src_size));8243 }, dst_reg.to128(), registerAlias(src_reg, src_size));
81268244
...@@ -9000,7 +9118,7 @@ fn airUnionInit(self: *Self, inst: Air.Inst.Index) !void {...@@ -9000,7 +9118,7 @@ fn airUnionInit(self: *Self, inst: Air.Inst.Index) !void {
9000 const ty_pl = self.air.instructions.items(.data)[inst].ty_pl;9118 const ty_pl = self.air.instructions.items(.data)[inst].ty_pl;
9001 const extra = self.air.extraData(Air.UnionInit, ty_pl.payload).data;9119 const extra = self.air.extraData(Air.UnionInit, ty_pl.payload).data;
9002 _ = extra;9120 _ = extra;
9003 return self.fail("TODO implement airAggregateInit for x86_64", .{});9121 return self.fail("TODO implement airUnionInit for x86_64", .{});
9004 //return self.finishAir(inst, result, .{ extra.init, .none, .none });9122 //return self.finishAir(inst, result, .{ extra.init, .none, .none });
9005}9123}
90069124
src/arch/x86_64/Encoding.zig+15-1
...@@ -268,23 +268,37 @@ pub const Mnemonic = enum {...@@ -268,23 +268,37 @@ pub const Mnemonic = enum {
268 movd,268 movd,
269 // SSE269 // SSE
270 addss,270 addss,
271 andps,
272 andnps,
271 cmpss,273 cmpss,
272 cvtsi2ss,274 cvtsi2ss,
273 divss,275 divss,
274 maxss, minss,276 maxss, minss,
275 movss,277 movaps, movss, movups,
276 mulss,278 mulss,
279 orps,
280 pextrw,
281 pinsrw,
282 sqrtps,
283 sqrtss,
277 subss,284 subss,
278 ucomiss,285 ucomiss,
279 xorps,286 xorps,
280 // SSE2287 // SSE2
281 addsd,288 addsd,
289 andpd,
290 andnpd,
282 //cmpsd,291 //cmpsd,
283 cvtsd2ss, cvtsi2sd, cvtss2sd,292 cvtsd2ss, cvtsi2sd, cvtss2sd,
284 divsd,293 divsd,
285 maxsd, minsd,294 maxsd, minsd,
295 movapd,
286 movq, //movd, movsd,296 movq, //movd, movsd,
297 movupd,
287 mulsd,298 mulsd,
299 orpd,
300 sqrtpd,
301 sqrtsd,
288 subsd,302 subsd,
289 ucomisd,303 ucomisd,
290 xorpd,304 xorpd,
src/arch/x86_64/Lower.zig+23
...@@ -94,18 +94,29 @@ pub fn lowerMir(lower: *Lower, inst: Mir.Inst) Error![]const Instruction {...@@ -94,18 +94,29 @@ pub fn lowerMir(lower: *Lower, inst: Mir.Inst) Error![]const Instruction {
94 .xor,94 .xor,
9595
96 .addss,96 .addss,
97 .andnps,
98 .andps,
97 .cmpss,99 .cmpss,
98 .cvtsi2ss,100 .cvtsi2ss,
99 .divss,101 .divss,
100 .maxss,102 .maxss,
101 .minss,103 .minss,
104 .movaps,
102 .movss,105 .movss,
106 .movups,
103 .mulss,107 .mulss,
108 .orps,
109 .pextrw,
110 .pinsrw,
104 .roundss,111 .roundss,
112 .sqrtps,
113 .sqrtss,
105 .subss,114 .subss,
106 .ucomiss,115 .ucomiss,
107 .xorps,116 .xorps,
108 .addsd,117 .addsd,
118 .andnpd,
119 .andpd,
109 .cmpsd,120 .cmpsd,
110 .cvtsd2ss,121 .cvtsd2ss,
111 .cvtsi2sd,122 .cvtsi2sd,
...@@ -115,7 +126,10 @@ pub fn lowerMir(lower: *Lower, inst: Mir.Inst) Error![]const Instruction {...@@ -115,7 +126,10 @@ pub fn lowerMir(lower: *Lower, inst: Mir.Inst) Error![]const Instruction {
115 .minsd,126 .minsd,
116 .movsd,127 .movsd,
117 .mulsd,128 .mulsd,
129 .orpd,
118 .roundsd,130 .roundsd,
131 .sqrtpd,
132 .sqrtsd,
119 .subsd,133 .subsd,
120 .ucomisd,134 .ucomisd,
121 .xorpd,135 .xorpd,
...@@ -188,6 +202,8 @@ fn imm(lower: Lower, ops: Mir.Inst.Ops, i: u32) Immediate {...@@ -188,6 +202,8 @@ fn imm(lower: Lower, ops: Mir.Inst.Ops, i: u32) Immediate {
188 .mi_rip_u,202 .mi_rip_u,
189 .lock_mi_sib_u,203 .lock_mi_sib_u,
190 .lock_mi_rip_u,204 .lock_mi_rip_u,
205 .rmi_sib,
206 .rmi_rip,
191 .mri_sib,207 .mri_sib,
192 .mri_rip,208 .mri_rip,
193 => Immediate.u(i),209 => Immediate.u(i),
...@@ -202,6 +218,7 @@ fn mem(lower: Lower, ops: Mir.Inst.Ops, payload: u32) Memory {...@@ -202,6 +218,7 @@ fn mem(lower: Lower, ops: Mir.Inst.Ops, payload: u32) Memory {
202 return lower.mir.resolveFrameLoc(switch (ops) {218 return lower.mir.resolveFrameLoc(switch (ops) {
203 .rm_sib,219 .rm_sib,
204 .rm_sib_cc,220 .rm_sib_cc,
221 .rmi_sib,
205 .m_sib,222 .m_sib,
206 .m_sib_cc,223 .m_sib_cc,
207 .mi_sib_u,224 .mi_sib_u,
...@@ -217,6 +234,7 @@ fn mem(lower: Lower, ops: Mir.Inst.Ops, payload: u32) Memory {...@@ -217,6 +234,7 @@ fn mem(lower: Lower, ops: Mir.Inst.Ops, payload: u32) Memory {
217234
218 .rm_rip,235 .rm_rip,
219 .rm_rip_cc,236 .rm_rip_cc,
237 .rmi_rip,
220 .m_rip,238 .m_rip,
221 .m_rip_cc,239 .m_rip_cc,
222 .mi_rip_u,240 .mi_rip_u,
...@@ -311,6 +329,11 @@ fn mirGeneric(lower: *Lower, inst: Mir.Inst) Error!void {...@@ -311,6 +329,11 @@ fn mirGeneric(lower: *Lower, inst: Mir.Inst) Error!void {
311 .{ .reg = inst.data.rx.r },329 .{ .reg = inst.data.rx.r },
312 .{ .mem = lower.mem(inst.ops, inst.data.rx.payload) },330 .{ .mem = lower.mem(inst.ops, inst.data.rx.payload) },
313 },331 },
332 .rmi_sib, .rmi_rip => &.{
333 .{ .reg = inst.data.rix.r },
334 .{ .mem = lower.mem(inst.ops, inst.data.rix.payload) },
335 .{ .imm = lower.imm(inst.ops, inst.data.rix.i) },
336 },
314 .mr_sib, .lock_mr_sib, .mr_rip, .lock_mr_rip => &.{337 .mr_sib, .lock_mr_sib, .mr_rip, .lock_mr_rip => &.{
315 .{ .mem = lower.mem(inst.ops, inst.data.rx.payload) },338 .{ .mem = lower.mem(inst.ops, inst.data.rx.payload) },
316 .{ .reg = inst.data.rx.r },339 .{ .reg = inst.data.rx.r },
src/arch/x86_64/Mir.zig+34
...@@ -168,6 +168,10 @@ pub const Inst = struct {...@@ -168,6 +168,10 @@ pub const Inst = struct {
168168
169 /// Add single precision floating point values169 /// Add single precision floating point values
170 addss,170 addss,
171 /// Bitwise logical and of packed single precision floating-point values
172 andps,
173 /// Bitwise logical and not of packed single precision floating-point values
174 andnps,
171 /// Compare scalar single-precision floating-point values175 /// Compare scalar single-precision floating-point values
172 cmpss,176 cmpss,
173 /// Convert doubleword integer to scalar single-precision floating-point value177 /// Convert doubleword integer to scalar single-precision floating-point value
...@@ -178,13 +182,27 @@ pub const Inst = struct {...@@ -178,13 +182,27 @@ pub const Inst = struct {
178 maxss,182 maxss,
179 /// Return minimum single-precision floating-point value183 /// Return minimum single-precision floating-point value
180 minss,184 minss,
185 /// Move aligned packed single-precision floating-point values
186 movaps,
181 /// Move scalar single-precision floating-point value187 /// Move scalar single-precision floating-point value
182 movss,188 movss,
189 /// Move unaligned packed single-precision floating-point values
190 movups,
183 /// Multiply scalar single-precision floating-point values191 /// Multiply scalar single-precision floating-point values
184 mulss,192 mulss,
193 /// Bitwise logical or of packed single precision floating-point values
194 orps,
195 /// Extract word
196 pextrw,
197 /// Insert word
198 pinsrw,
185 /// Round scalar single-precision floating-point values199 /// Round scalar single-precision floating-point values
186 roundss,200 roundss,
201 /// Square root of scalar single precision floating-point value
202 sqrtps,
187 /// Subtract scalar single-precision floating-point values203 /// Subtract scalar single-precision floating-point values
204 sqrtss,
205 /// Square root of single precision floating-point values
188 subss,206 subss,
189 /// Unordered compare scalar single-precision floating-point values207 /// Unordered compare scalar single-precision floating-point values
190 ucomiss,208 ucomiss,
...@@ -192,6 +210,10 @@ pub const Inst = struct {...@@ -192,6 +210,10 @@ pub const Inst = struct {
192 xorps,210 xorps,
193 /// Add double precision floating point values211 /// Add double precision floating point values
194 addsd,212 addsd,
213 /// Bitwise logical and not of packed double precision floating-point values
214 andnpd,
215 /// Bitwise logical and of packed double precision floating-point values
216 andpd,
195 /// Compare scalar double-precision floating-point values217 /// Compare scalar double-precision floating-point values
196 cmpsd,218 cmpsd,
197 /// Convert scalar double-precision floating-point value to scalar single-precision floating-point value219 /// Convert scalar double-precision floating-point value to scalar single-precision floating-point value
...@@ -210,8 +232,14 @@ pub const Inst = struct {...@@ -210,8 +232,14 @@ pub const Inst = struct {
210 movsd,232 movsd,
211 /// Multiply scalar double-precision floating-point values233 /// Multiply scalar double-precision floating-point values
212 mulsd,234 mulsd,
235 /// Bitwise logical or of packed double precision floating-point values
236 orpd,
213 /// Round scalar double-precision floating-point values237 /// Round scalar double-precision floating-point values
214 roundsd,238 roundsd,
239 /// Square root of double precision floating-point values
240 sqrtpd,
241 /// Square root of scalar double precision floating-point value
242 sqrtsd,
215 /// Subtract scalar double-precision floating-point values243 /// Subtract scalar double-precision floating-point values
216 subsd,244 subsd,
217 /// Unordered compare scalar double-precision floating-point values245 /// Unordered compare scalar double-precision floating-point values
...@@ -326,6 +354,12 @@ pub const Inst = struct {...@@ -326,6 +354,12 @@ pub const Inst = struct {
326 /// Register, memory (RIP) operands with condition code (CC).354 /// Register, memory (RIP) operands with condition code (CC).
327 /// Uses `rx_cc` payload.355 /// Uses `rx_cc` payload.
328 rm_rip_cc,356 rm_rip_cc,
357 /// Register, memory (SIB), immediate (byte) operands.
358 /// Uses `rix` payload with extra data of type `MemorySib`.
359 rmi_sib,
360 /// Register, memory (RIP), immediate (byte) operands.
361 /// Uses `rix` payload with extra data of type `MemoryRip`.
362 rmi_rip,
329 /// Single memory (SIB) operand.363 /// Single memory (SIB) operand.
330 /// Uses `payload` with extra data of type `MemorySib`.364 /// Uses `payload` with extra data of type `MemorySib`.
331 m_sib,365 m_sib,
src/arch/x86_64/encodings.zig+36
...@@ -832,6 +832,10 @@ pub const table = [_]Entry{...@@ -832,6 +832,10 @@ pub const table = [_]Entry{
832 // SSE832 // SSE
833 .{ .addss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x58 }, 0, .sse },833 .{ .addss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x58 }, 0, .sse },
834834
835 .{ .andnps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x55 }, 0, .sse },
836
837 .{ .andps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x54 }, 0, .sse },
838
835 .{ .cmpss, .rmi, &.{ .xmm, .xmm_m32, .imm8 }, &.{ 0xf3, 0x0f, 0xc2 }, 0, .sse },839 .{ .cmpss, .rmi, &.{ .xmm, .xmm_m32, .imm8 }, &.{ 0xf3, 0x0f, 0xc2 }, 0, .sse },
836840
837 .{ .cvtsi2ss, .rm, &.{ .xmm, .rm32 }, &.{ 0xf3, 0x0f, 0x2a }, 0, .sse },841 .{ .cvtsi2ss, .rm, &.{ .xmm, .rm32 }, &.{ 0xf3, 0x0f, 0x2a }, 0, .sse },
...@@ -843,13 +847,24 @@ pub const table = [_]Entry{...@@ -843,13 +847,24 @@ pub const table = [_]Entry{
843847
844 .{ .minss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x5d }, 0, .sse },848 .{ .minss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x5d }, 0, .sse },
845849
850 .{ .movaps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x28 }, 0, .sse },
851 .{ .movaps, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x0f, 0x29 }, 0, .sse },
852
846 .{ .movss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x10 }, 0, .sse },853 .{ .movss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x10 }, 0, .sse },
847 .{ .movss, .mr, &.{ .xmm_m32, .xmm }, &.{ 0xf3, 0x0f, 0x11 }, 0, .sse },854 .{ .movss, .mr, &.{ .xmm_m32, .xmm }, &.{ 0xf3, 0x0f, 0x11 }, 0, .sse },
848855
856 .{ .movups, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x10 }, 0, .sse },
857 .{ .movups, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x0f, 0x11 }, 0, .sse },
858
849 .{ .mulss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x59 }, 0, .sse },859 .{ .mulss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x59 }, 0, .sse },
850860
861 .{ .orps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x56 }, 0, .sse },
862
851 .{ .subss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x5c }, 0, .sse },863 .{ .subss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x5c }, 0, .sse },
852864
865 .{ .sqrtps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x51 }, 0, .sse },
866 .{ .sqrtss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x51 }, 0, .sse },
867
853 .{ .ucomiss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0x0f, 0x2e }, 0, .sse },868 .{ .ucomiss, .rm, &.{ .xmm, .xmm_m32 }, &.{ 0x0f, 0x2e }, 0, .sse },
854869
855 .{ .xorps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x57 }, 0, .sse },870 .{ .xorps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x57 }, 0, .sse },
...@@ -857,6 +872,10 @@ pub const table = [_]Entry{...@@ -857,6 +872,10 @@ pub const table = [_]Entry{
857 // SSE2872 // SSE2
858 .{ .addsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x58 }, 0, .sse2 },873 .{ .addsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x58 }, 0, .sse2 },
859874
875 .{ .andnpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x55 }, 0, .sse2 },
876
877 .{ .andpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x54 }, 0, .sse2 },
878
860 .{ .cmpsd, .rmi, &.{ .xmm, .xmm_m64, .imm8 }, &.{ 0xf2, 0x0f, 0xc2 }, 0, .sse2 },879 .{ .cmpsd, .rmi, &.{ .xmm, .xmm_m64, .imm8 }, &.{ 0xf2, 0x0f, 0xc2 }, 0, .sse2 },
861880
862 .{ .cvtsd2ss, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x5a }, 0, .sse2 },881 .{ .cvtsd2ss, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x5a }, 0, .sse2 },
...@@ -872,6 +891,9 @@ pub const table = [_]Entry{...@@ -872,6 +891,9 @@ pub const table = [_]Entry{
872891
873 .{ .minsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x5d }, 0, .sse2 },892 .{ .minsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x5d }, 0, .sse2 },
874893
894 .{ .movapd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x28 }, 0, .sse2 },
895 .{ .movapd, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x66, 0x0f, 0x29 }, 0, .sse2 },
896
875 .{ .movd, .rm, &.{ .xmm, .rm32 }, &.{ 0x66, 0x0f, 0x6e }, 0, .sse2 },897 .{ .movd, .rm, &.{ .xmm, .rm32 }, &.{ 0x66, 0x0f, 0x6e }, 0, .sse2 },
876 .{ .movd, .mr, &.{ .rm32, .xmm }, &.{ 0x66, 0x0f, 0x7e }, 0, .sse2 },898 .{ .movd, .mr, &.{ .rm32, .xmm }, &.{ 0x66, 0x0f, 0x7e }, 0, .sse2 },
877899
...@@ -881,8 +903,20 @@ pub const table = [_]Entry{...@@ -881,8 +903,20 @@ pub const table = [_]Entry{
881 .{ .movq, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf3, 0x0f, 0x7e }, 0, .sse2 },903 .{ .movq, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf3, 0x0f, 0x7e }, 0, .sse2 },
882 .{ .movq, .mr, &.{ .xmm_m64, .xmm }, &.{ 0x66, 0x0f, 0xd6 }, 0, .sse2 },904 .{ .movq, .mr, &.{ .xmm_m64, .xmm }, &.{ 0x66, 0x0f, 0xd6 }, 0, .sse2 },
883905
906 .{ .movupd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x10 }, 0, .sse2 },
907 .{ .movupd, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x66, 0x0f, 0x11 }, 0, .sse2 },
908
884 .{ .mulsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x59 }, 0, .sse2 },909 .{ .mulsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x59 }, 0, .sse2 },
885910
911 .{ .orpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x56 }, 0, .sse2 },
912
913 .{ .pextrw, .mri, &.{ .r16, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0xc5 }, 0, .sse2 },
914
915 .{ .pinsrw, .rmi, &.{ .xmm, .rm16, .imm8 }, &.{ 0x66, 0x0f, 0xc4 }, 0, .sse2 },
916
917 .{ .sqrtpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x51 }, 0, .sse2 },
918 .{ .sqrtsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x51 }, 0, .sse2 },
919
886 .{ .subsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x5c }, 0, .sse2 },920 .{ .subsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x5c }, 0, .sse2 },
887921
888 .{ .movsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x10 }, 0, .sse2 },922 .{ .movsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x10 }, 0, .sse2 },
...@@ -893,6 +927,8 @@ pub const table = [_]Entry{...@@ -893,6 +927,8 @@ pub const table = [_]Entry{
893 .{ .xorpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x57 }, 0, .sse2 },927 .{ .xorpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x57 }, 0, .sse2 },
894928
895 // SSE4.1929 // SSE4.1
930 .{ .pextrw, .mri, &.{ .rm16, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x15 }, 0, .sse4_1 },
931
896 .{ .roundss, .rmi, &.{ .xmm, .xmm_m32, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0a }, 0, .sse4_1 },932 .{ .roundss, .rmi, &.{ .xmm, .xmm_m32, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0a }, 0, .sse4_1 },
897 .{ .roundsd, .rmi, &.{ .xmm, .xmm_m64, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0b }, 0, .sse4_1 },933 .{ .roundsd, .rmi, &.{ .xmm, .xmm_m64, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0b }, 0, .sse4_1 },
898};934};
src/codegen.zig+80-102
...@@ -341,14 +341,20 @@ pub fn generateSymbol(...@@ -341,14 +341,20 @@ pub fn generateSymbol(
341 }341 }
342 return Result.ok;342 return Result.ok;
343 },343 },
344 .variable => {344 .variable, .decl_ref, .decl_ref_mut => |tag| return lowerDeclRef(
345 const decl = typed_value.val.castTag(.variable).?.data.owner_decl;345 bin_file,
346 return lowerDeclRef(bin_file, src_loc, typed_value, decl, code, debug_output, reloc_info);346 src_loc,
347 },347 typed_value,
348 .decl_ref => {348 switch (tag) {
349 const decl = typed_value.val.castTag(.decl_ref).?.data;349 .variable => typed_value.val.castTag(.variable).?.data.owner_decl,
350 return lowerDeclRef(bin_file, src_loc, typed_value, decl, code, debug_output, reloc_info);350 .decl_ref => typed_value.val.castTag(.decl_ref).?.data,
351 },351 .decl_ref_mut => typed_value.val.castTag(.decl_ref_mut).?.data.decl_index,
352 else => unreachable,
353 },
354 code,
355 debug_output,
356 reloc_info,
357 ),
352 .slice => {358 .slice => {
353 const slice = typed_value.val.castTag(.slice).?.data;359 const slice = typed_value.val.castTag(.slice).?.data;
354360
...@@ -374,66 +380,7 @@ pub fn generateSymbol(...@@ -374,66 +380,7 @@ pub fn generateSymbol(
374380
375 return Result.ok;381 return Result.ok;
376 },382 },
377 .field_ptr => {383 .field_ptr, .elem_ptr => return lowerParentPtr(
378 const field_ptr = typed_value.val.castTag(.field_ptr).?.data;
379 const container_ptr = field_ptr.container_ptr;
380
381 switch (container_ptr.tag()) {
382 .decl_ref => {
383 const decl_index = container_ptr.castTag(.decl_ref).?.data;
384 const decl = mod.declPtr(decl_index);
385 const addend = blk: {
386 switch (decl.ty.zigTypeTag()) {
387 .Struct => {
388 const addend = decl.ty.structFieldOffset(field_ptr.field_index, target);
389 break :blk @intCast(u32, addend);
390 },
391 .Pointer => {
392 assert(decl.ty.isSlice());
393 var buf: Type.SlicePtrFieldTypeBuffer = undefined;
394 const addend = switch (field_ptr.field_index) {
395 0 => 0,
396 1 => decl.ty.slicePtrFieldType(&buf).abiSize(target),
397 else => unreachable,
398 };
399 break :blk @intCast(u32, addend);
400 },
401 else => return Result{
402 .fail = try ErrorMsg.create(
403 bin_file.allocator,
404 src_loc,
405 "TODO implement generateSymbol for pointer type value: '{s}'",
406 .{@tagName(typed_value.val.tag())},
407 ),
408 },
409 }
410 };
411 return lowerDeclRef(bin_file, src_loc, typed_value, decl_index, code, debug_output, .{
412 .parent_atom_index = reloc_info.parent_atom_index,
413 .addend = (reloc_info.addend orelse 0) + addend,
414 });
415 },
416 .field_ptr => {
417 switch (try generateSymbol(bin_file, src_loc, .{
418 .ty = typed_value.ty,
419 .val = container_ptr,
420 }, code, debug_output, reloc_info)) {
421 .ok => {},
422 .fail => |em| return Result{ .fail = em },
423 }
424 return Result.ok;
425 },
426 else => return Result{
427 .fail = try ErrorMsg.create(
428 bin_file.allocator,
429 src_loc,
430 "TODO implement generateSymbol for pointer type value: '{s}'",
431 .{@tagName(typed_value.val.tag())},
432 ),
433 },
434 }
435 },
436 .elem_ptr => return lowerParentPtr(
437 bin_file,384 bin_file,
438 src_loc,385 src_loc,
439 typed_value,386 typed_value,
...@@ -846,16 +793,12 @@ pub fn generateSymbol(...@@ -846,16 +793,12 @@ pub fn generateSymbol(
846 },793 },
847 else => unreachable,794 else => unreachable,
848 },795 },
849 else => |t| {796 else => |tag| return Result{ .fail = try ErrorMsg.create(
850 return Result{797 bin_file.allocator,
851 .fail = try ErrorMsg.create(798 src_loc,
852 bin_file.allocator,799 "TODO implement generateSymbol for type '{s}'",
853 src_loc,800 .{@tagName(tag)},
854 "TODO implement generateSymbol for type '{s}'",801 ) },
855 .{@tagName(t)},
856 ),
857 };
858 },
859 }802 }
860}803}
861804
...@@ -871,40 +814,70 @@ fn lowerParentPtr(...@@ -871,40 +814,70 @@ fn lowerParentPtr(
871 const target = bin_file.options.target;814 const target = bin_file.options.target;
872815
873 switch (parent_ptr.tag()) {816 switch (parent_ptr.tag()) {
874 .elem_ptr => {817 .field_ptr => {
875 const elem_ptr = parent_ptr.castTag(.elem_ptr).?.data;818 const field_ptr = parent_ptr.castTag(.field_ptr).?.data;
876 return lowerParentPtr(819 return lowerParentPtr(
877 bin_file,820 bin_file,
878 src_loc,821 src_loc,
879 typed_value,822 typed_value,
880 elem_ptr.array_ptr,823 field_ptr.container_ptr,
881 code,824 code,
882 debug_output,825 debug_output,
883 reloc_info.offset(@intCast(u32, elem_ptr.index * elem_ptr.elem_ty.abiSize(target))),826 reloc_info.offset(@intCast(u32, switch (field_ptr.container_ty.zigTypeTag()) {
827 .Pointer => offset: {
828 assert(field_ptr.container_ty.isSlice());
829 var buf: Type.SlicePtrFieldTypeBuffer = undefined;
830 break :offset switch (field_ptr.field_index) {
831 0 => 0,
832 1 => field_ptr.container_ty.slicePtrFieldType(&buf).abiSize(target),
833 else => unreachable,
834 };
835 },
836 .Struct, .Union => field_ptr.container_ty.structFieldOffset(
837 field_ptr.field_index,
838 target,
839 ),
840 else => return Result{ .fail = try ErrorMsg.create(
841 bin_file.allocator,
842 src_loc,
843 "TODO implement lowerParentPtr for field_ptr with a container of type {}",
844 .{field_ptr.container_ty.fmt(bin_file.options.module.?)},
845 ) },
846 })),
884 );847 );
885 },848 },
886 .decl_ref => {849 .elem_ptr => {
887 const decl_index = parent_ptr.castTag(.decl_ref).?.data;850 const elem_ptr = parent_ptr.castTag(.elem_ptr).?.data;
888 return lowerDeclRef(851 return lowerParentPtr(
889 bin_file,852 bin_file,
890 src_loc,853 src_loc,
891 typed_value,854 typed_value,
892 decl_index,855 elem_ptr.array_ptr,
893 code,856 code,
894 debug_output,857 debug_output,
895 reloc_info,858 reloc_info.offset(@intCast(u32, elem_ptr.index * elem_ptr.elem_ty.abiSize(target))),
896 );859 );
897 },860 },
898 else => |t| {861 .variable, .decl_ref, .decl_ref_mut => |tag| return lowerDeclRef(
899 return Result{862 bin_file,
900 .fail = try ErrorMsg.create(863 src_loc,
901 bin_file.allocator,864 typed_value,
902 src_loc,865 switch (tag) {
903 "TODO implement lowerParentPtr for type '{s}'",866 .variable => parent_ptr.castTag(.variable).?.data.owner_decl,
904 .{@tagName(t)},867 .decl_ref => parent_ptr.castTag(.decl_ref).?.data,
905 ),868 .decl_ref_mut => parent_ptr.castTag(.decl_ref_mut).?.data.decl_index,
906 };869 else => unreachable,
907 },870 },
871 code,
872 debug_output,
873 reloc_info,
874 ),
875 else => |tag| return Result{ .fail = try ErrorMsg.create(
876 bin_file.allocator,
877 src_loc,
878 "TODO implement lowerParentPtr for type '{s}'",
879 .{@tagName(tag)},
880 ) },
908 }881 }
909}882}
910883
...@@ -1156,11 +1129,16 @@ pub fn genTypedValue(...@@ -1156,11 +1129,16 @@ pub fn genTypedValue(
1156 const target = bin_file.options.target;1129 const target = bin_file.options.target;
1157 const ptr_bits = target.cpu.arch.ptrBitWidth();1130 const ptr_bits = target.cpu.arch.ptrBitWidth();
11581131
1159 if (typed_value.val.castTag(.decl_ref)) |payload| {1132 if (!typed_value.ty.isSlice()) {
1160 return genDeclRef(bin_file, src_loc, typed_value, payload.data);1133 if (typed_value.val.castTag(.variable)) |payload| {
1161 }1134 return genDeclRef(bin_file, src_loc, typed_value, payload.data.owner_decl);
1162 if (typed_value.val.castTag(.decl_ref_mut)) |payload| {1135 }
1163 return genDeclRef(bin_file, src_loc, typed_value, payload.data.decl_index);1136 if (typed_value.val.castTag(.decl_ref)) |payload| {
1137 return genDeclRef(bin_file, src_loc, typed_value, payload.data);
1138 }
1139 if (typed_value.val.castTag(.decl_ref_mut)) |payload| {
1140 return genDeclRef(bin_file, src_loc, typed_value, payload.data.decl_index);
1141 }
1164 }1142 }
11651143
1166 switch (typed_value.ty.zigTypeTag()) {1144 switch (typed_value.ty.zigTypeTag()) {
test/behavior/basic.zig-8
...@@ -363,8 +363,6 @@ fn hereIsAnOpaqueType(ptr: *OpaqueA) *OpaqueA {...@@ -363,8 +363,6 @@ fn hereIsAnOpaqueType(ptr: *OpaqueA) *OpaqueA {
363}363}
364364
365test "take address of parameter" {365test "take address of parameter" {
366 if (builtin.zig_backend == .stage2_x86_64 and
367 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
368 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;366 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
369 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;367 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
370 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO368 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
...@@ -392,8 +390,6 @@ test "array 2D const double ptr" {...@@ -392,8 +390,6 @@ test "array 2D const double ptr" {
392 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;390 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
393 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO391 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
394 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;392 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
395 if (builtin.zig_backend == .stage2_x86_64 and
396 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
397 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO393 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
398394
399 const rect_2d_vertexes = [_][1]f32{395 const rect_2d_vertexes = [_][1]f32{
...@@ -407,8 +403,6 @@ test "array 2D const double ptr with offset" {...@@ -407,8 +403,6 @@ test "array 2D const double ptr with offset" {
407 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;403 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
408 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO404 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
409 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;405 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
410 if (builtin.zig_backend == .stage2_x86_64 and
411 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
412 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest;406 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest;
413407
414 const rect_2d_vertexes = [_][2]f32{408 const rect_2d_vertexes = [_][2]f32{
...@@ -422,8 +416,6 @@ test "array 3D const double ptr with offset" {...@@ -422,8 +416,6 @@ test "array 3D const double ptr with offset" {
422 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;416 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
423 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO417 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
424 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;418 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
425 if (builtin.zig_backend == .stage2_x86_64 and
426 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
427 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO419 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
428420
429 const rect_3d_vertexes = [_][2][2]f32{421 const rect_3d_vertexes = [_][2][2]f32{
test/behavior/bugs/13069.zig-2
...@@ -6,8 +6,6 @@ test {...@@ -6,8 +6,6 @@ test {
6 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO6 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
7 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO7 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
8 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO8 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
9 if (builtin.zig_backend == .stage2_x86_64 and
10 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
119
12 var opt_x: ?[3]f32 = [_]f32{0.0} ** 3;10 var opt_x: ?[3]f32 = [_]f32{0.0} ** 3;
1311
test/behavior/cast.zig-9
...@@ -95,9 +95,6 @@ test "comptime_int @intToFloat" {...@@ -95,9 +95,6 @@ test "comptime_int @intToFloat" {
9595
96test "@intToFloat" {96test "@intToFloat" {
97 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO97 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
98 if (builtin.zig_backend == .stage2_x86_64 and
99 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
100
101 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO98 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
102 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO99 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
103100
...@@ -636,8 +633,6 @@ test "vector casts" {...@@ -636,8 +633,6 @@ test "vector casts" {
636}633}
637634
638test "@floatCast cast down" {635test "@floatCast cast down" {
639 if (builtin.zig_backend == .stage2_x86_64 and
640 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
641 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO636 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
642 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO637 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
643 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO638 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
...@@ -688,7 +683,6 @@ test "peer cast: error set any anyerror" {...@@ -688,7 +683,6 @@ test "peer cast: error set any anyerror" {
688}683}
689684
690test "peer type resolution: error set supersets" {685test "peer type resolution: error set supersets" {
691 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
692 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO686 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
693 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO687 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
694 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO688 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
...@@ -718,7 +712,6 @@ test "peer type resolution: error set supersets" {...@@ -718,7 +712,6 @@ test "peer type resolution: error set supersets" {
718}712}
719713
720test "peer type resolution: disjoint error sets" {714test "peer type resolution: disjoint error sets" {
721 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
722 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO715 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
723 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO716 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
724 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO717 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
...@@ -748,7 +741,6 @@ test "peer type resolution: disjoint error sets" {...@@ -748,7 +741,6 @@ test "peer type resolution: disjoint error sets" {
748}741}
749742
750test "peer type resolution: error union and error set" {743test "peer type resolution: error union and error set" {
751 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
752 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO744 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
753 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO745 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
754 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO746 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
...@@ -782,7 +774,6 @@ test "peer type resolution: error union and error set" {...@@ -782,7 +774,6 @@ test "peer type resolution: error union and error set" {
782}774}
783775
784test "peer type resolution: error union after non-error" {776test "peer type resolution: error union after non-error" {
785 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
786 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO777 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
787 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO778 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
788 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO779 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
test/behavior/enum.zig-2
...@@ -940,8 +940,6 @@ test "constant enum initialization with differing sizes" {...@@ -940,8 +940,6 @@ test "constant enum initialization with differing sizes" {
940 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;940 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
941 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;941 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
942 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO942 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
943 if (builtin.zig_backend == .stage2_x86_64 and
944 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
945943
946 try test3_1(test3_foo);944 try test3_1(test3_foo);
947 try test3_2(test3_bar);945 try test3_2(test3_bar);
test/behavior/eval.zig-3
...@@ -535,8 +535,6 @@ test "static eval list init" {...@@ -535,8 +535,6 @@ test "static eval list init" {
535 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO535 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
536 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO536 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
537 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO537 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
538 if (builtin.zig_backend == .stage2_x86_64 and
539 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
540538
541 try expect(static_vec3.data[2] == 1.0);539 try expect(static_vec3.data[2] == 1.0);
542 try expect(vec3(0.0, 0.0, 3.0).data[2] == 3.0);540 try expect(vec3(0.0, 0.0, 3.0).data[2] == 3.0);
...@@ -1185,7 +1183,6 @@ test "equality of pointers to comptime const" {...@@ -1185,7 +1183,6 @@ test "equality of pointers to comptime const" {
1185}1183}
11861184
1187test "storing an array of type in a field" {1185test "storing an array of type in a field" {
1188 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
1189 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO1186 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
1190 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO1187 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1191 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO1188 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
test/behavior/floatop.zig-9
...@@ -96,7 +96,6 @@ test "negative f128 floatToInt at compile-time" {...@@ -96,7 +96,6 @@ test "negative f128 floatToInt at compile-time" {
96}96}
9797
98test "@sqrt" {98test "@sqrt" {
99 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
100 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO99 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
101 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO100 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
102 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO101 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
...@@ -904,8 +903,6 @@ test "negation f16" {...@@ -904,8 +903,6 @@ test "negation f16" {
904}903}
905904
906test "negation f32" {905test "negation f32" {
907 if (builtin.zig_backend == .stage2_x86_64 and
908 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
909 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO906 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
910 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO907 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
911 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO908 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
...@@ -925,8 +922,6 @@ test "negation f32" {...@@ -925,8 +922,6 @@ test "negation f32" {
925}922}
926923
927test "negation f64" {924test "negation f64" {
928 if (builtin.zig_backend == .stage2_x86_64 and
929 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
930 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO925 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
931 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO926 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
932 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO927 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
...@@ -1061,8 +1056,6 @@ test "nan negation f16" {...@@ -1061,8 +1056,6 @@ test "nan negation f16" {
1061}1056}
10621057
1063test "nan negation f32" {1058test "nan negation f32" {
1064 if (builtin.zig_backend == .stage2_x86_64 and
1065 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
1066 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO1059 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
1067 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO1060 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1068 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO1061 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
...@@ -1082,8 +1075,6 @@ test "nan negation f32" {...@@ -1082,8 +1075,6 @@ test "nan negation f32" {
10821075
1083test "nan negation f64" {1076test "nan negation f64" {
1084 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO1077 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
1085 if (builtin.zig_backend == .stage2_x86_64 and
1086 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
1087 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO1078 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
1088 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO1079 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1089 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO1080 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
test/behavior/fn.zig-4
...@@ -338,8 +338,6 @@ test "function call with anon list literal" {...@@ -338,8 +338,6 @@ test "function call with anon list literal" {
338 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO338 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
339 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO339 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
340 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO340 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
341 if (builtin.zig_backend == .stage2_x86_64 and
342 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
343341
344 const S = struct {342 const S = struct {
345 fn doTheTest() !void {343 fn doTheTest() !void {
...@@ -360,8 +358,6 @@ test "function call with anon list literal - 2D" {...@@ -360,8 +358,6 @@ test "function call with anon list literal - 2D" {
360 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO358 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
361 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO359 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
362 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO360 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
363 if (builtin.zig_backend == .stage2_x86_64 and
364 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
365361
366 const S = struct {362 const S = struct {
367 fn doTheTest() !void {363 fn doTheTest() !void {
test/behavior/for.zig-4
...@@ -66,7 +66,6 @@ test "ignore lval with underscore (for loop)" {...@@ -66,7 +66,6 @@ test "ignore lval with underscore (for loop)" {
66}66}
6767
68test "basic for loop" {68test "basic for loop" {
69 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
70 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;69 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
71 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;70 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
72 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO71 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
...@@ -306,7 +305,6 @@ test "1-based counter and ptr to array" {...@@ -306,7 +305,6 @@ test "1-based counter and ptr to array" {
306test "slice and two counters, one is offset and one is runtime" {305test "slice and two counters, one is offset and one is runtime" {
307 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO306 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
308 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO307 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
309 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
310 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO308 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
311309
312 const slice: []const u8 = "blah";310 const slice: []const u8 = "blah";
...@@ -335,7 +333,6 @@ test "slice and two counters, one is offset and one is runtime" {...@@ -335,7 +333,6 @@ test "slice and two counters, one is offset and one is runtime" {
335test "two slices, one captured by-ref" {333test "two slices, one captured by-ref" {
336 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO334 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
337 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO335 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
338 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
339 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO336 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
340337
341 var buf: [10]u8 = undefined;338 var buf: [10]u8 = undefined;
...@@ -355,7 +352,6 @@ test "two slices, one captured by-ref" {...@@ -355,7 +352,6 @@ test "two slices, one captured by-ref" {
355test "raw pointer and slice" {352test "raw pointer and slice" {
356 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO353 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
357 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO354 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
358 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
359 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO355 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
360356
361 var buf: [10]u8 = undefined;357 var buf: [10]u8 = undefined;
test/behavior/generics.zig-5
...@@ -59,8 +59,6 @@ test "fn with comptime args" {...@@ -59,8 +59,6 @@ test "fn with comptime args" {
59 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;59 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
60 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;60 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
61 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO61 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
62 if (builtin.zig_backend == .stage2_x86_64 and
63 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
6462
65 try expect(gimmeTheBigOne(1234, 5678) == 5678);63 try expect(gimmeTheBigOne(1234, 5678) == 5678);
66 try expect(shouldCallSameInstance(34, 12) == 34);64 try expect(shouldCallSameInstance(34, 12) == 34);
...@@ -71,8 +69,6 @@ test "anytype params" {...@@ -71,8 +69,6 @@ test "anytype params" {
71 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;69 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
72 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;70 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
73 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO71 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
74 if (builtin.zig_backend == .stage2_x86_64 and
75 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
7672
77 try expect(max_i32(12, 34) == 34);73 try expect(max_i32(12, 34) == 34);
78 try expect(max_f64(1.2, 3.4) == 3.4);74 try expect(max_f64(1.2, 3.4) == 3.4);
...@@ -250,7 +246,6 @@ test "function parameter is generic" {...@@ -250,7 +246,6 @@ test "function parameter is generic" {
250}246}
251247
252test "generic function instantiation turns into comptime call" {248test "generic function instantiation turns into comptime call" {
253 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
254 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO249 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
255 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO250 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
256 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO251 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
test/behavior/math.zig-2
...@@ -203,8 +203,6 @@ test "float equality" {...@@ -203,8 +203,6 @@ test "float equality" {
203 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO203 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
204 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO204 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
205 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO205 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
206 if (builtin.zig_backend == .stage2_x86_64 and
207 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
208206
209 const x: f64 = 0.012;207 const x: f64 = 0.012;
210 const y: f64 = x + 1.0;208 const y: f64 = x + 1.0;
test/behavior/maximum_minimum.zig-4
...@@ -8,8 +8,6 @@ test "@max" {...@@ -8,8 +8,6 @@ test "@max" {
8 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO8 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
9 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO9 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
10 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO10 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
11 if (builtin.zig_backend == .stage2_x86_64 and
12 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
1311
14 const S = struct {12 const S = struct {
15 fn doTheTest() !void {13 fn doTheTest() !void {
...@@ -56,8 +54,6 @@ test "@min" {...@@ -56,8 +54,6 @@ test "@min" {
56 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO54 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
57 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO55 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
58 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO56 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
59 if (builtin.zig_backend == .stage2_x86_64 and
60 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
6157
62 const S = struct {58 const S = struct {
63 fn doTheTest() !void {59 fn doTheTest() !void {
test/behavior/pointers.zig-4
...@@ -206,8 +206,6 @@ test "allowzero pointer and slice" {...@@ -206,8 +206,6 @@ test "allowzero pointer and slice" {
206}206}
207207
208test "assign null directly to C pointer and test null equality" {208test "assign null directly to C pointer and test null equality" {
209 if (builtin.zig_backend == .stage2_x86_64 and
210 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
211 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO209 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
212 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO210 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
213 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO211 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
...@@ -346,8 +344,6 @@ test "pointer sentinel with +inf" {...@@ -346,8 +344,6 @@ test "pointer sentinel with +inf" {
346 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO344 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
347 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO345 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
348 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO346 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
349 if (builtin.zig_backend == .stage2_x86_64 and
350 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
351347
352 const S = struct {348 const S = struct {
353 fn doTheTest() !void {349 fn doTheTest() !void {
test/behavior/ptrcast.zig-2
...@@ -128,7 +128,6 @@ fn testReinterpretOverAlignedExternStructAsExternStruct() !void {...@@ -128,7 +128,6 @@ fn testReinterpretOverAlignedExternStructAsExternStruct() !void {
128test "lower reinterpreted comptime field ptr (with under-aligned fields)" {128test "lower reinterpreted comptime field ptr (with under-aligned fields)" {
129 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO129 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
130 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO130 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
131 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
132 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO131 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
133 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO132 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
134133
...@@ -152,7 +151,6 @@ test "lower reinterpreted comptime field ptr (with under-aligned fields)" {...@@ -152,7 +151,6 @@ test "lower reinterpreted comptime field ptr (with under-aligned fields)" {
152test "lower reinterpreted comptime field ptr" {151test "lower reinterpreted comptime field ptr" {
153 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO152 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
154 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO153 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
155 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
156 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO154 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
157 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO155 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
158156
test/behavior/src.zig-1
...@@ -14,7 +14,6 @@ const builtin = @import("builtin");...@@ -14,7 +14,6 @@ const builtin = @import("builtin");
14const expect = std.testing.expect;14const expect = std.testing.expect;
1515
16test "@src" {16test "@src" {
17 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
18 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO17 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
19 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO18 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
20 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO19 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
test/behavior/struct.zig-3
...@@ -744,8 +744,6 @@ var g_foo: S0 = S0.init();...@@ -744,8 +744,6 @@ var g_foo: S0 = S0.init();
744744
745test "packed struct with fp fields" {745test "packed struct with fp fields" {
746 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO746 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
747 if (builtin.zig_backend == .stage2_x86_64 and
748 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
749 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO747 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
750 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO748 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
751 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO749 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
...@@ -1333,7 +1331,6 @@ test "under-aligned struct field" {...@@ -1333,7 +1331,6 @@ test "under-aligned struct field" {
1333}1331}
13341332
1335test "fieldParentPtr of a zero-bit field" {1333test "fieldParentPtr of a zero-bit field" {
1336 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
1337 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO1334 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
1338 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO1335 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
13391336
test/behavior/switch.zig-2
...@@ -230,8 +230,6 @@ test "switch prong with variable" {...@@ -230,8 +230,6 @@ test "switch prong with variable" {
230 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO230 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
231 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO231 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
232 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO232 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
233 if (builtin.zig_backend == .stage2_x86_64 and
234 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
235233
236 try switchProngWithVarFn(SwitchProngWithVarEnum{ .One = 13 });234 try switchProngWithVarFn(SwitchProngWithVarEnum{ .One = 13 });
237 try switchProngWithVarFn(SwitchProngWithVarEnum{ .Two = 13.0 });235 try switchProngWithVarFn(SwitchProngWithVarEnum{ .Two = 13.0 });
test/behavior/tuple.zig-2
...@@ -209,7 +209,6 @@ test "initializing anon struct with explicit type" {...@@ -209,7 +209,6 @@ test "initializing anon struct with explicit type" {
209}209}
210210
211test "fieldParentPtr of tuple" {211test "fieldParentPtr of tuple" {
212 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
213 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;212 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
214 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;213 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
215 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO214 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
...@@ -220,7 +219,6 @@ test "fieldParentPtr of tuple" {...@@ -220,7 +219,6 @@ test "fieldParentPtr of tuple" {
220}219}
221220
222test "fieldParentPtr of anon struct" {221test "fieldParentPtr of anon struct" {
223 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
224 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;222 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
225 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;223 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
226 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO224 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
test/behavior/type_info.zig-4
...@@ -159,7 +159,6 @@ fn testArray() !void {...@@ -159,7 +159,6 @@ fn testArray() !void {
159test "type info: error set, error union info, anyerror" {159test "type info: error set, error union info, anyerror" {
160 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;160 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
161 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO161 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
162 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
163 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO162 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
164163
165 try testErrorSet();164 try testErrorSet();
...@@ -191,7 +190,6 @@ fn testErrorSet() !void {...@@ -191,7 +190,6 @@ fn testErrorSet() !void {
191test "type info: error set single value" {190test "type info: error set single value" {
192 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;191 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
193 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO192 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
194 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
195 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO193 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
196194
197 const TestSet = error.One;195 const TestSet = error.One;
...@@ -205,7 +203,6 @@ test "type info: error set single value" {...@@ -205,7 +203,6 @@ test "type info: error set single value" {
205test "type info: error set merged" {203test "type info: error set merged" {
206 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;204 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
207 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO205 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
208 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
209 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO206 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
210207
211 const TestSet = error{ One, Two } || error{Three};208 const TestSet = error{ One, Two } || error{Three};
...@@ -219,7 +216,6 @@ test "type info: error set merged" {...@@ -219,7 +216,6 @@ test "type info: error set merged" {
219}216}
220217
221test "type info: enum info" {218test "type info: enum info" {
222 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
223 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;219 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
224 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;220 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
225 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO221 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
test/behavior/union.zig-15
...@@ -14,8 +14,6 @@ test "basic unions with floats" {...@@ -14,8 +14,6 @@ test "basic unions with floats" {
14 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;14 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
15 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;15 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
16 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO16 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
17 if (builtin.zig_backend == .stage2_x86_64 and
18 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
1917
20 var foo = FooWithFloats{ .int = 1 };18 var foo = FooWithFloats{ .int = 1 };
21 try expect(foo.int == 1);19 try expect(foo.int == 1);
...@@ -31,8 +29,6 @@ test "init union with runtime value - floats" {...@@ -31,8 +29,6 @@ test "init union with runtime value - floats" {
31 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;29 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
32 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;30 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
33 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO31 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
34 if (builtin.zig_backend == .stage2_x86_64 and
35 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
3632
37 var foo: FooWithFloats = undefined;33 var foo: FooWithFloats = undefined;
3834
...@@ -220,8 +216,6 @@ test "union with specified enum tag" {...@@ -220,8 +216,6 @@ test "union with specified enum tag" {
220 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;216 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
221 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;217 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
222 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO218 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
223 if (builtin.zig_backend == .stage2_x86_64 and
224 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
225219
226 try doTest();220 try doTest();
227 comptime try doTest();221 comptime try doTest();
...@@ -231,8 +225,6 @@ test "packed union generates correctly aligned type" {...@@ -231,8 +225,6 @@ test "packed union generates correctly aligned type" {
231 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;225 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
232 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;226 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
233 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO227 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
234 if (builtin.zig_backend == .stage2_x86_64 and
235 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
236228
237 const U = packed union {229 const U = packed union {
238 f1: *const fn () error{TestUnexpectedResult}!void,230 f1: *const fn () error{TestUnexpectedResult}!void,
...@@ -448,7 +440,6 @@ const Foo1 = union(enum) {...@@ -448,7 +440,6 @@ const Foo1 = union(enum) {
448var glbl: Foo1 = undefined;440var glbl: Foo1 = undefined;
449441
450test "global union with single field is correctly initialized" {442test "global union with single field is correctly initialized" {
451 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
452 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;443 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
453 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;444 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
454 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO445 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
...@@ -911,8 +902,6 @@ test "anonymous union literal syntax" {...@@ -911,8 +902,6 @@ test "anonymous union literal syntax" {
911 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO902 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
912 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO903 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
913 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO904 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
914 if (builtin.zig_backend == .stage2_x86_64 and
915 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
916905
917 const S = struct {906 const S = struct {
918 const Number = union {907 const Number = union {
...@@ -1065,8 +1054,6 @@ test "containers with single-field enums" {...@@ -1065,8 +1054,6 @@ test "containers with single-field enums" {
1065 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO1054 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1066 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO1055 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
1067 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO1056 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
1068 if (builtin.zig_backend == .stage2_x86_64 and
1069 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
10701057
1071 const S = struct {1058 const S = struct {
1072 const A = union(enum) { f1 };1059 const A = union(enum) { f1 };
...@@ -1525,8 +1512,6 @@ test "reinterpreting enum value inside packed union" {...@@ -1525,8 +1512,6 @@ test "reinterpreting enum value inside packed union" {
1525 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO1512 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
1526 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO1513 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1527 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO1514 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
1528 if (builtin.zig_backend == .stage2_x86_64 and
1529 comptime !std.Target.x86.featureSetHasAll(builtin.cpu.features, .{ .sse, .sse2, .sse4_1 })) return error.SkipZigTest; // TODO
15301515
1531 const U = packed union {1516 const U = packed union {
1532 tag: enum { a, b },1517 tag: enum { a, b },
test/behavior/vector.zig-6
...@@ -133,7 +133,6 @@ test "vector bit operators" {...@@ -133,7 +133,6 @@ test "vector bit operators" {
133}133}
134134
135test "implicit cast vector to array" {135test "implicit cast vector to array" {
136 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
137 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO136 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
138 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO137 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
139 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO138 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
...@@ -151,7 +150,6 @@ test "implicit cast vector to array" {...@@ -151,7 +150,6 @@ test "implicit cast vector to array" {
151}150}
152151
153test "array to vector" {152test "array to vector" {
154 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
155 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO153 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
156 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO154 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
157 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO155 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
...@@ -321,7 +319,6 @@ test "load vector elements via comptime index" {...@@ -321,7 +319,6 @@ test "load vector elements via comptime index" {
321 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO319 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
322 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO320 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
323 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO321 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
324 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
325322
326 const S = struct {323 const S = struct {
327 fn doTheTest() !void {324 fn doTheTest() !void {
...@@ -343,7 +340,6 @@ test "store vector elements via comptime index" {...@@ -343,7 +340,6 @@ test "store vector elements via comptime index" {
343 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO340 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
344 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO341 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
345 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO342 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
346 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
347343
348 const S = struct {344 const S = struct {
349 fn doTheTest() !void {345 fn doTheTest() !void {
...@@ -371,7 +367,6 @@ test "load vector elements via runtime index" {...@@ -371,7 +367,6 @@ test "load vector elements via runtime index" {
371 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO367 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
372 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO368 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
373 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO369 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
374 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
375370
376 const S = struct {371 const S = struct {
377 fn doTheTest() !void {372 fn doTheTest() !void {
...@@ -393,7 +388,6 @@ test "store vector elements via runtime index" {...@@ -393,7 +388,6 @@ test "store vector elements via runtime index" {
393 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO388 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
394 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO389 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
395 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO390 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
396 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
397391
398 const S = struct {392 const S = struct {
399 fn doTheTest() !void {393 fn doTheTest() !void {