| ... | @@ -1135,6 +1135,7 @@ extern fn c_ret_medium_vec() MediumVec; | ... | @@ -1135,6 +1135,7 @@ extern fn c_ret_medium_vec() MediumVec; |
| 1135 | test "medium simd vector" { | 1135 | test "medium simd vector" { |
| 1136 | if (builtin.zig_backend == .stage2_x86_64 and !comptime builtin.cpu.has(.x86, .avx)) return error.SkipZigTest; | 1136 | if (builtin.zig_backend == .stage2_x86_64 and !comptime builtin.cpu.has(.x86, .avx)) return error.SkipZigTest; |
| 1137 | if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; | 1137 | if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; |
| | 1138 | if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest; |
| 1138 | | 1139 | |
| 1139 | c_medium_vec(.{ 1, 2, 3, 4 }); | 1140 | c_medium_vec(.{ 1, 2, 3, 4 }); |
| 1140 | | 1141 | |
| ... | @@ -1155,6 +1156,7 @@ test "big simd vector" { | ... | @@ -1155,6 +1156,7 @@ test "big simd vector" { |
| 1155 | | 1156 | |
| 1156 | if (builtin.cpu.arch.isMIPS64() and builtin.mode != .Debug) return error.SkipZigTest; | 1157 | if (builtin.cpu.arch.isMIPS64() and builtin.mode != .Debug) return error.SkipZigTest; |
| 1157 | if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; | 1158 | if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; |
| | 1159 | if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest; |
| 1158 | if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .x86_64 and builtin.os.tag == .macos and builtin.mode != .Debug) return error.SkipZigTest; | 1160 | if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .x86_64 and builtin.os.tag == .macos and builtin.mode != .Debug) return error.SkipZigTest; |
| 1159 | | 1161 | |
| 1160 | c_big_vec(.{ 1, 2, 3, 4, 5, 6, 7, 8 }); | 1162 | c_big_vec(.{ 1, 2, 3, 4, 5, 6, 7, 8 }); |