authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-07-21 14:10:07+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-07-21 22:38:30+02:00
logf1e0c35db4167b8cc5a70d2270028287e737fff4
treecbd5e142e629b2fca80af47ebbc3cf94b2e757ba
parent67a052df81dbd40a49ce07b58e854d56b1def03a
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.Target: Remove `hsail`/`hsail64` arch tags.

This seems to just be dead. See: https://github.com/search?q=repo%3Allvm%2Fllvm-project%20hsail&type=code See: https://github.com/HSAFoundation/HSAIL-Tools/commits/master

6 files changed, 0 insertions(+), 34 deletions(-)

lib/compiler/aro/aro/target.zig-6
......@@ -480,7 +480,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
480480 .x86,
481481 .xcore,
482482 .nvptx,
483 .hsail,
484483 .spir,
485484 .kalimba,
486485 .shave,
......@@ -497,7 +496,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
497496 .aarch64_be => copy.cpu.arch = .armeb,
498497 .nvptx64 => copy.cpu.arch = .nvptx,
499498 .wasm64 => copy.cpu.arch = .wasm32,
500 .hsail64 => copy.cpu.arch = .hsail,
501499 .spir64 => copy.cpu.arch = .spir,
502500 .spirv64 => copy.cpu.arch = .spirv32,
503501 .loongarch64 => copy.cpu.arch = .loongarch32,
......@@ -540,7 +538,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
540538 .bpfel,
541539 .nvptx64,
542540 .wasm64,
543 .hsail64,
544541 .spir64,
545542 .spirv64,
546543 .loongarch64,
......@@ -558,7 +555,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
558555 .aarch64_32 => copy.cpu.arch = .aarch64,
559556 .arm => copy.cpu.arch = .aarch64,
560557 .armeb => copy.cpu.arch = .aarch64_be,
561 .hsail => copy.cpu.arch = .hsail64,
562558 .loongarch32 => copy.cpu.arch = .loongarch64,
563559 .mips => copy.cpu.arch = .mips64,
564560 .mipsel => copy.cpu.arch = .mips64el,
......@@ -627,8 +623,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
627623 .xtensa => "xtensa",
628624 .nvptx => "nvptx",
629625 .nvptx64 => "nvptx64",
630 .hsail => "hsail",
631 .hsail64 => "hsail64",
632626 .spir => "spir",
633627 .spir64 => "spir64",
634628 .spirv32 => "spirv32",
lib/std/Target.zig-16
......@@ -1011,8 +1011,6 @@ pub const Cpu = struct {
10111011 xtensa,
10121012 nvptx,
10131013 nvptx64,
1014 hsail,
1015 hsail64,
10161014 spir,
10171015 spir64,
10181016 spirv,
......@@ -1154,7 +1152,6 @@ pub const Cpu = struct {
11541152 .xcore => .XCORE,
11551153 .xtensa => .XTENSA,
11561154 .nvptx => .NONE,
1157 .hsail => .NONE,
11581155 .spir => .NONE,
11591156 .kalimba => .CSR_KALIMBA,
11601157 .shave => .NONE,
......@@ -1170,7 +1167,6 @@ pub const Cpu = struct {
11701167 .riscv64 => .RISCV,
11711168 .x86_64 => .X86_64,
11721169 .nvptx64 => .NONE,
1173 .hsail64 => .NONE,
11741170 .spir64 => .NONE,
11751171 .wasm64 => .NONE,
11761172 .amdgcn => .AMDGPU,
......@@ -1213,7 +1209,6 @@ pub const Cpu = struct {
12131209 .xcore => .Unknown,
12141210 .xtensa => .Unknown,
12151211 .nvptx => .Unknown,
1216 .hsail => .Unknown,
12171212 .spir => .Unknown,
12181213 .kalimba => .Unknown,
12191214 .shave => .Unknown,
......@@ -1229,7 +1224,6 @@ pub const Cpu = struct {
12291224 .riscv64 => .RISCV64,
12301225 .x86_64 => .X64,
12311226 .nvptx64 => .Unknown,
1232 .hsail64 => .Unknown,
12331227 .spir64 => .Unknown,
12341228 .wasm64 => .Unknown,
12351229 .amdgcn => .Unknown,
......@@ -1259,8 +1253,6 @@ pub const Cpu = struct {
12591253 .csky,
12601254 .xtensa,
12611255 .hexagon,
1262 .hsail,
1263 .hsail64,
12641256 .kalimba,
12651257 .mipsel,
12661258 .mips64el,
......@@ -1764,8 +1756,6 @@ pub const DynamicLinker = struct {
17641756 .tce,
17651757 .tcele,
17661758 .xcore,
1767 .hsail,
1768 .hsail64,
17691759 .spir,
17701760 .spir64,
17711761 .kalimba,
......@@ -1868,7 +1858,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
18681858 .x86,
18691859 .xcore,
18701860 .nvptx,
1871 .hsail,
18721861 .spir,
18731862 .kalimba,
18741863 .shave,
......@@ -1890,7 +1879,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
18901879 .riscv64,
18911880 .x86_64,
18921881 .nvptx64,
1893 .hsail64,
18941882 .spir64,
18951883 .wasm64,
18961884 .amdgcn,
......@@ -2390,7 +2378,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
23902378 .loongarch32,
23912379 .tce,
23922380 .tcele,
2393 .hsail,
23942381 .spir,
23952382 .spirv32,
23962383 .kalimba,
......@@ -2405,7 +2392,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
24052392 .bpfel,
24062393 .bpfeb,
24072394 .hexagon,
2408 .hsail64,
24092395 .loongarch64,
24102396 .m68k,
24112397 .mips,
......@@ -2504,7 +2490,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
25042490 .loongarch32,
25052491 .tce,
25062492 .tcele,
2507 .hsail,
25082493 .spir,
25092494 .spirv32,
25102495 .kalimba,
......@@ -2525,7 +2510,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
25252510 .bpfel,
25262511 .bpfeb,
25272512 .hexagon,
2528 .hsail64,
25292513 .x86,
25302514 .loongarch64,
25312515 .m68k,
src/Type.zig-2
......@@ -1650,13 +1650,11 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
16501650 .m68k,
16511651 .tce,
16521652 .tcele,
1653 .hsail,
16541653 .spir,
16551654 .kalimba,
16561655 .spirv,
16571656 .spirv32,
16581657 .shave,
1659 .hsail64,
16601658 .spir64,
16611659 .ve,
16621660 .spirv64,
src/Zcu.zig-2
......@@ -3255,7 +3255,6 @@ pub fn atomicPtrAlignment(
32553255 .thumbeb,
32563256 .x86,
32573257 .xcore,
3258 .hsail,
32593258 .spir,
32603259 .kalimba,
32613260 .lanai,
......@@ -3279,7 +3278,6 @@ pub fn atomicPtrAlignment(
32793278 .riscv64,
32803279 .sparc64,
32813280 .s390x,
3282 .hsail64,
32833281 .spir64,
32843282 .wasm64,
32853283 .ve,
src/codegen/llvm.zig-6
......@@ -82,8 +82,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
8282 .xtensa => "xtensa",
8383 .nvptx => "nvptx",
8484 .nvptx64 => "nvptx64",
85 .hsail => "hsail",
86 .hsail64 => "hsail64",
8785 .spir => "spir",
8886 .spir64 => "spir64",
8987 .spirv => "spirv",
......@@ -301,8 +299,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
301299 .xtensa => .xtensa,
302300 .nvptx => .nvptx,
303301 .nvptx64 => .nvptx64,
304 .hsail => .hsail,
305 .hsail64 => .hsail64,
306302 .spir => .spir,
307303 .spir64 => .spir64,
308304 .spirv => .spirv,
......@@ -12084,8 +12080,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
1208412080 // LLVM backends that have no initialization functions.
1208512081 .tce,
1208612082 .tcele,
12087 .hsail,
12088 .hsail64,
1208912083 .shave,
1209012084 .spir,
1209112085 .spir64,
src/target.zig-2
......@@ -152,8 +152,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
152152 .xtensa,
153153 .nvptx,
154154 .nvptx64,
155 .hsail,
156 .hsail64,
157155 .spir,
158156 .spir64,
159157 .spirv,