| author |  Alex Rønne Petersen <alex@alexrp.com> 2024-10-02 08:16:05+02:00 |
| committer | Alex Rønne Petersen <alex@alexrp.com> 2024-10-03 09:53:59+02:00 |
| log | f31173d379eb7c63f214579ffbba611c1fa38900 |
| tree | 2f4cc148a6a741619b6706bae5bd7ad56b24564b |
| parent | 56b0c7bd2f5936c17571e878f835cf0d542ca1fd |
| signature |  Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM |
llvm: Disable f16 lowering for hexagon.
In theory, this should work for v68+. In practice, it runs into an LLVM
assertion when using a `freeze` instruction on `f16` values, similar to the
issue we had for LoongArch.1 files changed, 1 insertions(+), 0 deletions(-)
src- codegen
src/codegen/llvm.zig+1
| ... | @@ -12380,6 +12380,7 @@ fn backendSupportsF80(target: std.Target) bool { | ... | @@ -12380,6 +12380,7 @@ fn backendSupportsF80(target: std.Target) bool { |
| 12380 | /// if it produces miscompilations. | 12380 | /// if it produces miscompilations. |
| 12381 | fn backendSupportsF16(target: std.Target) bool { | 12381 | fn backendSupportsF16(target: std.Target) bool { |
| 12382 | return switch (target.cpu.arch) { | 12382 | return switch (target.cpu.arch) { |
| 12383 | .hexagon, | ||
| 12383 | .powerpc, | 12384 | .powerpc, |
| 12384 | .powerpcle, | 12385 | .powerpcle, |
| 12385 | .powerpc64, | 12386 | .powerpc64, |