| ... | ... | @@ -626,16 +626,24 @@ fn detectNativeCpuWithLLVM( |
| 626 | 626 | } |
| 627 | 627 | |
| 628 | 628 | // ABI warning |
| 629 | | export fn stage2_cmd_targets(zig_triple: [*:0]const u8) c_int { |
| 630 | | cmdTargets(zig_triple) catch |err| { |
| 629 | export fn stage2_cmd_targets( |
| 630 | zig_triple: ?[*:0]const u8, |
| 631 | mcpu: ?[*:0]const u8, |
| 632 | dynamic_linker: ?[*:0]const u8, |
| 633 | ) c_int { |
| 634 | cmdTargets(zig_triple, mcpu, dynamic_linker) catch |err| { |
| 631 | 635 | std.debug.warn("unable to list targets: {}\n", .{@errorName(err)}); |
| 632 | 636 | return -1; |
| 633 | 637 | }; |
| 634 | 638 | return 0; |
| 635 | 639 | } |
| 636 | 640 | |
| 637 | | fn cmdTargets(zig_triple: [*:0]const u8) !void { |
| 638 | | var cross_target = try CrossTarget.parse(.{ .arch_os_abi = mem.toSliceConst(u8, zig_triple) }); |
| 641 | fn cmdTargets( |
| 642 | zig_triple_oz: ?[*:0]const u8, |
| 643 | mcpu_oz: ?[*:0]const u8, |
| 644 | dynamic_linker_oz: ?[*:0]const u8, |
| 645 | ) !void { |
| 646 | const cross_target = try stage2CrossTarget(zig_triple_oz, mcpu_oz, dynamic_linker_oz); |
| 639 | 647 | var dynamic_linker: ?[*:0]u8 = null; |
| 640 | 648 | const target = try crossTargetToTarget(cross_target, &dynamic_linker); |
| 641 | 649 | return @import("print_targets.zig").cmdTargets( |
| ... | ... | @@ -673,12 +681,11 @@ export fn stage2_target_parse( |
| 673 | 681 | return .None; |
| 674 | 682 | } |
| 675 | 683 | |
| 676 | | fn stage2TargetParse( |
| 677 | | stage1_target: *Stage2Target, |
| 684 | fn stage2CrossTarget( |
| 678 | 685 | zig_triple_oz: ?[*:0]const u8, |
| 679 | 686 | mcpu_oz: ?[*:0]const u8, |
| 680 | 687 | dynamic_linker_oz: ?[*:0]const u8, |
| 681 | | ) !void { |
| 688 | ) !CrossTarget { |
| 682 | 689 | const zig_triple = if (zig_triple_oz) |zig_triple_z| mem.toSliceConst(u8, zig_triple_z) else "native"; |
| 683 | 690 | const mcpu = if (mcpu_oz) |mcpu_z| mem.toSliceConst(u8, mcpu_z) else null; |
| 684 | 691 | const dynamic_linker = if (dynamic_linker_oz) |dl_z| mem.toSliceConst(u8, dl_z) else null; |
| ... | ... | @@ -716,6 +723,16 @@ fn stage2TargetParse( |
| 716 | 723 | else => |e| return e, |
| 717 | 724 | }; |
| 718 | 725 | |
| 726 | return target; |
| 727 | } |
| 728 | |
| 729 | fn stage2TargetParse( |
| 730 | stage1_target: *Stage2Target, |
| 731 | zig_triple_oz: ?[*:0]const u8, |
| 732 | mcpu_oz: ?[*:0]const u8, |
| 733 | dynamic_linker_oz: ?[*:0]const u8, |
| 734 | ) !void { |
| 735 | const target = try stage2CrossTarget(zig_triple_oz, mcpu_oz, dynamic_linker_oz); |
| 719 | 736 | try stage1_target.fromTarget(target); |
| 720 | 737 | } |
| 721 | 738 | |
| ... | ... | @@ -905,22 +922,6 @@ const Stage2Target = extern struct { |
| 905 | 922 | |
| 906 | 923 | dynamic_linker: ?[*:0]const u8, |
| 907 | 924 | |
| 908 | | fn toTarget(in_target: Stage2Target) CrossTarget { |
| 909 | | if (in_target.is_native) return .{}; |
| 910 | | |
| 911 | | const in_arch = in_target.arch - 1; // skip over ZigLLVM_UnknownArch |
| 912 | | const in_os = in_target.os; |
| 913 | | const in_abi = in_target.abi; |
| 914 | | |
| 915 | | return .{ |
| 916 | | .Cross = .{ |
| 917 | | .cpu = Target.Cpu.baseline(enumInt(Target.Cpu.Arch, in_arch)), |
| 918 | | .os = Target.Os.defaultVersionRange(enumInt(Target.Os.Tag, in_os)), |
| 919 | | .abi = enumInt(Target.Abi, in_abi), |
| 920 | | }, |
| 921 | | }; |
| 922 | | } |
| 923 | | |
| 924 | 925 | fn fromTarget(self: *Stage2Target, cross_target: CrossTarget) !void { |
| 925 | 926 | const allocator = std.heap.c_allocator; |
| 926 | 927 | |