authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-10-07 00:45:27+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-10-07 16:47:57+02:00
logfeba8a83a7c4eda738ebcf619c33ade8d0dfbfa7
treee884fc4d0d8a7efeef1a51aa5ac19b42dfad7339
parent9a6fad2706d05743a512c9ab5b54ba91cf5956fa
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.debug.Dwarf: use 65 as the (fake) RISC-V PC register

32-63 conflict with the floating point registers. 64 is the Alternate Frame Return Column.

2 files changed, 2 insertions(+), 2 deletions(-)

lib/std/debug/Dwarf.zig+1-1
...@@ -1435,7 +1435,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {...@@ -1435,7 +1435,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
1435 .loongarch32, .loongarch64 => 64,1435 .loongarch32, .loongarch64 => 64,
1436 .mips, .mipsel, .mips64, .mips64el => 37,1436 .mips, .mipsel, .mips64, .mips64el => 37,
1437 .powerpc, .powerpcle, .powerpc64, .powerpc64le => 357,1437 .powerpc, .powerpcle, .powerpc64, .powerpc64le => 357,
1438 .riscv32, .riscv32be, .riscv64, .riscv64be => 32,1438 .riscv32, .riscv32be, .riscv64, .riscv64be => 65,
1439 .s390x => 65,1439 .s390x => 65,
1440 .x86 => 8,1440 .x86 => 8,
1441 .x86_64 => 16,1441 .x86_64 => 16,
lib/std/debug/cpu_context.zig+1-1
...@@ -1018,7 +1018,7 @@ pub const Riscv = extern struct {...@@ -1018,7 +1018,7 @@ pub const Riscv = extern struct {
1018 pub fn dwarfRegisterBytes(ctx: *Riscv, register_num: u16) DwarfRegisterError![]u8 {1018 pub fn dwarfRegisterBytes(ctx: *Riscv, register_num: u16) DwarfRegisterError![]u8 {
1019 switch (register_num) {1019 switch (register_num) {
1020 0...31 => return @ptrCast(&ctx.r[register_num]),1020 0...31 => return @ptrCast(&ctx.r[register_num]),
1021 32 => return @ptrCast(&ctx.pc),1021 65 => return @ptrCast(&ctx.pc),
10221022
1023 else => return error.InvalidRegister,1023 else => return error.InvalidRegister,
1024 }1024 }