| 5 years ago |  Timon Kruiper | | stage2: handle void value in genRet in LLVM backend |
| 5 years ago | Timon Kruiper | | stage2: rename fail to todo in LLVM backend |
| 5 years ago |  Isaac Freund | | stage2: fix two return types to be Ref not Index |
| 5 years ago | Timon Kruiper | | astgen: implement assign operations |
| 5 years ago |  Andrew Kelley | | stage2: fix `if` expressions |
| 5 years ago | Andrew Kelley | | astgen: improve the ensure_unused_result elision |
| 5 years ago | Andrew Kelley | | stage2: Sema improvements and boolean logic astgen |
| 5 years ago | Isaac Freund | | stage2: remove all async related code |
| 5 years ago |  Dimenus | | fix calculation in ensureCapacity |
| 5 years ago | Isaac Freund | | astgen: implement pointer types |
| 5 years ago | Isaac Freund | | astgen: implement array types |
| 5 years ago | Andrew Kelley | | cleanups from previous commit |
| 5 years ago |  Jacob G-W | | zir-memory-layout: astgen: varDecl |
| 5 years ago | Andrew Kelley | | Sema: implement arithmetic |
| 5 years ago | Andrew Kelley | | Sema: no explicit coercion needed for inline asm args |
| 5 years ago | Isaac Freund | | astgen: implement bool_and/bool_or |
| 5 years ago | Isaac Freund | | astgen: implement simple binary operators |
| 5 years ago | Isaac Freund | | zir: add negate/negate_wrap, implement astgen |
| 5 years ago | Andrew Kelley | | astgen: fix not detecting volatile asm |
| 5 years ago | Andrew Kelley | | stage2: fix memory management of ZIR code |
| 5 years ago | Andrew Kelley | | astgen: implement string literals |
| 5 years ago | Andrew Kelley | | astgen: implement inline assembly |
| 5 years ago | Andrew Kelley | | ZIR: move some un_tok tags to un_node instead |
| 5 years ago | Andrew Kelley | | astgen: implement function calls |
| 5 years ago | Jacob G-W | | zir-memory-layout: remove all absolute src consts |
| 5 years ago | Jacob G-W | | zir-memory-layout: astgen: more instructions |
| 5 years ago | Timon Kruiper | | stage2: restructure LLVM backend |
| 5 years ago | Andrew Kelley | | astgen: support blocks |
| 5 years ago | Andrew Kelley | | stage2: first pass at repairing ZIR printing |
| 5 years ago | Andrew Kelley | | Sema: allocate inst_map with arena where appropriate |
| 5 years ago | Andrew Kelley | | stage2: fix some math oopsies and typos |
| 5 years ago | Andrew Kelley | | stage2: fix export source locations not being relative to Decl |
| 5 years ago | Jacob G-W | | zir-memory-layout: astgen: literals and *, & |
| 5 years ago | Jacob G-W | | llvm backend: use new srcloc |
| 5 years ago | Jacob G-W | | zir-memory-layout: astgen: fill in identifier |
| 5 years ago | Andrew Kelley | | stage2: codegen: update asm IR to new names |
| 5 years ago | Andrew Kelley | | stage2: the code is compiling again |
| 5 years ago | Andrew Kelley | | stage2: get Module and Sema compiling again |
| 5 years ago | Andrew Kelley | | Merge remote-tracking branch 'origin/master' into zir-memory-layout |
| 5 years ago | Andrew Kelley | | stage2: Module and Sema are compiling again |
| 5 years ago | Andrew Kelley | | stage2: work through some compile errors in Module and Sema |
| 5 years ago | Jacob G-W | | zir-memory-layout: fix @setEvalBranchQuota |
| 5 years ago | Andrew Kelley | | stage2: rename zir_sema.zig to Sema.zig |
| 5 years ago | Andrew Kelley | | stage2: *WIP*: rework ZIR memory layout; overhaul source locations |
| 5 years ago |  Anders Conbere | | std: support optional getaddrinfo arguments |
| 5 years ago |  Lewis Gaul | | Add test for multi-line while cont expr with same-line then expr |
| 5 years ago | Isaac Freund | | zig fmt: simplify and improve consistency of if/for/while handling |
| 5 years ago | Lewis Gaul | | zig fmt: fix extra newline before if nested in for |
| 5 years ago |  Michael Dusan | | macho: fix various linker flags |
| 5 years ago |  LemonBoy | | std: Replace testing fns for floating-point values |
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