authorgravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-03-21 23:38:01+01:00
committergravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-03-21 23:38:01+01:00
log00e2113c8b07f9d1c67c7c70b69e7b9e6343b2d9
treed9789d224479308fda94a6b1b1ba6624484c9d0b
parent79e2d4b3f6d759c8d9689d05e880c387daabe3b1

x64: refactor fix reg aliasing in genSetReg

2 files changed, 7 insertions(+), 7 deletions(-)

src/arch/x86_64/CodeGen.zig+6-7
......@@ -953,8 +953,7 @@ pub fn spillCompareFlagsIfOccupied(self: *Self) !void {
953953/// This can have a side effect of spilling instructions to the stack to free up a register.
954954fn copyToTmpRegister(self: *Self, ty: Type, mcv: MCValue) !Register {
955955 const reg = try self.register_manager.allocReg(null);
956 const sized_reg = registerAlias(reg, @intCast(u32, ty.abiSize(self.target.*)));
957 try self.genSetReg(ty, sized_reg, mcv);
956 try self.genSetReg(ty, reg, mcv);
958957 return reg;
959958}
960959
......@@ -5201,7 +5200,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
52015200 if (!self.wantSafety())
52025201 return; // The already existing value will do just fine.
52035202 // Write the debug undefined value.
5204 switch (reg.size()) {
5203 switch (registerAlias(reg, abi_size).size()) {
52055204 8 => return self.genSetReg(ty, reg, .{ .immediate = 0xaa }),
52065205 16 => return self.genSetReg(ty, reg, .{ .immediate = 0xaaaa }),
52075206 32 => return self.genSetReg(ty, reg, .{ .immediate = 0xaaaaaaaa }),
......@@ -5338,7 +5337,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
53385337 _ = try self.addInst(.{
53395338 .tag = .mov,
53405339 .ops = (Mir.Ops{
5341 .reg1 = reg,
5340 .reg1 = registerAlias(reg, abi_size),
53425341 .reg2 = reg.to64(),
53435342 .flags = 0b01,
53445343 }).encode(),
......@@ -5351,7 +5350,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
53515350 _ = try self.addInst(.{
53525351 .tag = .mov,
53535352 .ops = (Mir.Ops{
5354 .reg1 = reg,
5353 .reg1 = registerAlias(reg, abi_size),
53555354 .flags = 0b01,
53565355 }).encode(),
53575356 .data = .{ .imm = @truncate(u32, x) },
......@@ -5378,8 +5377,8 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
53785377 _ = try self.addInst(.{
53795378 .tag = .mov,
53805379 .ops = (Mir.Ops{
5381 .reg1 = reg,
5382 .reg2 = reg,
5380 .reg1 = registerAlias(reg, abi_size),
5381 .reg2 = reg.to64(),
53835382 .flags = 0b01,
53845383 }).encode(),
53855384 .data = .{ .imm = 0 },
test/behavior/eval.zig+1
......@@ -424,6 +424,7 @@ test "f64 at compile time is lossy" {
424424}
425425
426426test {
427 if (builtin.zig_backend != .stage1 and builtin.os.tag == .macos) return error.SkipZigTest;
427428 comptime try expect(@as(f128, 1 << 113) == 10384593717069655257060992658440192);
428429}
429430