authorgravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-03-21 23:38:01+01:00
committergravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-03-21 23:38:01+01:00
log00e2113c8b07f9d1c67c7c70b69e7b9e6343b2d9
treed9789d224479308fda94a6b1b1ba6624484c9d0b
parent79e2d4b3f6d759c8d9689d05e880c387daabe3b1

x64: refactor fix reg aliasing in genSetReg

2 files changed, 7 insertions(+), 7 deletions(-)

src/arch/x86_64/CodeGen.zig+6-7
...@@ -953,8 +953,7 @@ pub fn spillCompareFlagsIfOccupied(self: *Self) !void {...@@ -953,8 +953,7 @@ pub fn spillCompareFlagsIfOccupied(self: *Self) !void {
953/// This can have a side effect of spilling instructions to the stack to free up a register.953/// This can have a side effect of spilling instructions to the stack to free up a register.
954fn copyToTmpRegister(self: *Self, ty: Type, mcv: MCValue) !Register {954fn copyToTmpRegister(self: *Self, ty: Type, mcv: MCValue) !Register {
955 const reg = try self.register_manager.allocReg(null);955 const reg = try self.register_manager.allocReg(null);
956 const sized_reg = registerAlias(reg, @intCast(u32, ty.abiSize(self.target.*)));956 try self.genSetReg(ty, reg, mcv);
957 try self.genSetReg(ty, sized_reg, mcv);
958 return reg;957 return reg;
959}958}
960959
...@@ -5201,7 +5200,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -5201,7 +5200,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
5201 if (!self.wantSafety())5200 if (!self.wantSafety())
5202 return; // The already existing value will do just fine.5201 return; // The already existing value will do just fine.
5203 // Write the debug undefined value.5202 // Write the debug undefined value.
5204 switch (reg.size()) {5203 switch (registerAlias(reg, abi_size).size()) {
5205 8 => return self.genSetReg(ty, reg, .{ .immediate = 0xaa }),5204 8 => return self.genSetReg(ty, reg, .{ .immediate = 0xaa }),
5206 16 => return self.genSetReg(ty, reg, .{ .immediate = 0xaaaa }),5205 16 => return self.genSetReg(ty, reg, .{ .immediate = 0xaaaa }),
5207 32 => return self.genSetReg(ty, reg, .{ .immediate = 0xaaaaaaaa }),5206 32 => return self.genSetReg(ty, reg, .{ .immediate = 0xaaaaaaaa }),
...@@ -5338,7 +5337,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -5338,7 +5337,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
5338 _ = try self.addInst(.{5337 _ = try self.addInst(.{
5339 .tag = .mov,5338 .tag = .mov,
5340 .ops = (Mir.Ops{5339 .ops = (Mir.Ops{
5341 .reg1 = reg,5340 .reg1 = registerAlias(reg, abi_size),
5342 .reg2 = reg.to64(),5341 .reg2 = reg.to64(),
5343 .flags = 0b01,5342 .flags = 0b01,
5344 }).encode(),5343 }).encode(),
...@@ -5351,7 +5350,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -5351,7 +5350,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
5351 _ = try self.addInst(.{5350 _ = try self.addInst(.{
5352 .tag = .mov,5351 .tag = .mov,
5353 .ops = (Mir.Ops{5352 .ops = (Mir.Ops{
5354 .reg1 = reg,5353 .reg1 = registerAlias(reg, abi_size),
5355 .flags = 0b01,5354 .flags = 0b01,
5356 }).encode(),5355 }).encode(),
5357 .data = .{ .imm = @truncate(u32, x) },5356 .data = .{ .imm = @truncate(u32, x) },
...@@ -5378,8 +5377,8 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -5378,8 +5377,8 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
5378 _ = try self.addInst(.{5377 _ = try self.addInst(.{
5379 .tag = .mov,5378 .tag = .mov,
5380 .ops = (Mir.Ops{5379 .ops = (Mir.Ops{
5381 .reg1 = reg,5380 .reg1 = registerAlias(reg, abi_size),
5382 .reg2 = reg,5381 .reg2 = reg.to64(),
5383 .flags = 0b01,5382 .flags = 0b01,
5384 }).encode(),5383 }).encode(),
5385 .data = .{ .imm = 0 },5384 .data = .{ .imm = 0 },
test/behavior/eval.zig+1
...@@ -424,6 +424,7 @@ test "f64 at compile time is lossy" {...@@ -424,6 +424,7 @@ test "f64 at compile time is lossy" {
424}424}
425425
426test {426test {
427 if (builtin.zig_backend != .stage1 and builtin.os.tag == .macos) return error.SkipZigTest;
427 comptime try expect(@as(f128, 1 << 113) == 10384593717069655257060992658440192);428 comptime try expect(@as(f128, 1 << 113) == 10384593717069655257060992658440192);
428}429}
429430