| author | |
| committer | |
| log | 01dc0d5a7222470939d3eb96b1d14c27b70161ad |
| tree | 45dfbd583e95e4a293856a1c4088713471f8de87 |
| parent | 397be0c9cc8156d38d1487a4c80210007033cbd0 |
| signature |
2 files changed, 4 insertions(+), 2 deletions(-)
lib/std/Target.zig+2-1| ... | @@ -1967,7 +1967,6 @@ pub fn stackAlignment(target: Target) u16 { | ... | @@ -1967,7 +1967,6 @@ pub fn stackAlignment(target: Target) u16 { |
| 1967 | .bpfel, | 1967 | .bpfel, |
| 1968 | .mips64, | 1968 | .mips64, |
| 1969 | .mips64el, | 1969 | .mips64el, |
| 1970 | .riscv32, | ||
| 1971 | .riscv64, | 1970 | .riscv64, |
| 1972 | .sparc64, | 1971 | .sparc64, |
| 1973 | .x86_64, | 1972 | .x86_64, |
| ... | @@ -1976,6 +1975,8 @@ pub fn stackAlignment(target: Target) u16 { | ... | @@ -1976,6 +1975,8 @@ pub fn stackAlignment(target: Target) u16 { |
| 1976 | .wasm64, | 1975 | .wasm64, |
| 1977 | .loongarch64, | 1976 | .loongarch64, |
| 1978 | => 16, | 1977 | => 16, |
| 1978 | .riscv32, | ||
| 1979 | => if (Target.riscv.featureSetHas(target.cpu.features, .e)) 4 else 16, | ||
| 1979 | .powerpc64, | 1980 | .powerpc64, |
| 1980 | .powerpc64le, | 1981 | .powerpc64le, |
| 1981 | => switch (target.os.tag) { | 1982 | => switch (target.os.tag) { |
src/codegen/llvm.zig+2-1| ... | @@ -542,7 +542,8 @@ const DataLayoutBuilder = struct { | ... | @@ -542,7 +542,8 @@ const DataLayoutBuilder = struct { |
| 542 | try self.typeAlignment(.float, 64, 64, 64, true, writer); | 542 | try self.typeAlignment(.float, 64, 64, 64, true, writer); |
| 543 | } | 543 | } |
| 544 | if (stack_abi != ptr_bit_width or self.target.cpu.arch == .msp430 or | 544 | if (stack_abi != ptr_bit_width or self.target.cpu.arch == .msp430 or |
| 545 | self.target.os.tag == .uefi or self.target.os.tag == .windows) | 545 | self.target.os.tag == .uefi or self.target.os.tag == .windows or |
| 546 | self.target.cpu.arch == .riscv32) | ||
| 546 | try writer.print("-S{d}", .{stack_abi}); | 547 | try writer.print("-S{d}", .{stack_abi}); |
| 547 | switch (self.target.cpu.arch) { | 548 | switch (self.target.cpu.arch) { |
| 548 | .hexagon, .ve => { | 549 | .hexagon, .ve => { |