authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-05-27 21:27:06-07:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-05-28 12:58:40-07:00
log01e0a4b2f06d60a58b3d2df410776b164d05c1ec
tree833ada28094dd93d4ad5c04039542134bf458c0d
parent548ef780707eb2b438015c28d594a59a3f37ba3e

stage1: rename IrBasicBlockSrc to Stage1ZirBasicBlock

5 files changed, 136 insertions(+), 136 deletions(-)

src/stage1/all_types.hpp+17-17
......@@ -38,7 +38,7 @@ struct IrInstGenCast;
3838struct IrInstGenAlloca;
3939struct IrInstGenCall;
4040struct IrInstGenAwait;
41struct IrBasicBlockSrc;
41struct Stage1ZirBasicBlock;
4242struct IrBasicBlockGen;
4343struct ScopeDecls;
4444struct ZigWindowsSDK;
......@@ -111,7 +111,7 @@ enum X64CABIClass {
111111};
112112
113113struct Stage1Zir {
114 ZigList<IrBasicBlockSrc *> basic_block_list;
114 ZigList<Stage1ZirBasicBlock *> basic_block_list;
115115 Buf *name;
116116 ZigFn *name_fn;
117117 Scope *begin_scope;
......@@ -2255,11 +2255,11 @@ struct ScopeBlock {
22552255 Scope base;
22562256
22572257 Buf *name;
2258 IrBasicBlockSrc *end_block;
2258 Stage1ZirBasicBlock *end_block;
22592259 IrInstSrc *is_comptime;
22602260 ResultLocPeerParent *peer_parent;
22612261 ZigList<IrInstSrc *> *incoming_values;
2262 ZigList<IrBasicBlockSrc *> *incoming_blocks;
2262 ZigList<Stage1ZirBasicBlock *> *incoming_blocks;
22632263
22642264 AstNode *safety_set_node;
22652265 AstNode *fast_math_set_node;
......@@ -2311,11 +2311,11 @@ struct ScopeLoop {
23112311
23122312 LVal lval;
23132313 Buf *name;
2314 IrBasicBlockSrc *break_block;
2315 IrBasicBlockSrc *continue_block;
2314 Stage1ZirBasicBlock *break_block;
2315 Stage1ZirBasicBlock *continue_block;
23162316 IrInstSrc *is_comptime;
23172317 ZigList<IrInstSrc *> *incoming_values;
2318 ZigList<IrBasicBlockSrc *> *incoming_blocks;
2318 ZigList<Stage1ZirBasicBlock *> *incoming_blocks;
23192319 ResultLocPeerParent *peer_parent;
23202320 ScopeExpr *spill_scope;
23212321
......@@ -2426,7 +2426,7 @@ enum AtomicRmwOp {
24262426// to another basic block.
24272427// Phi instructions must be first in a basic block.
24282428// The last instruction in a basic block must be of type unreachable.
2429struct IrBasicBlockSrc {
2429struct Stage1ZirBasicBlock {
24302430 ZigList<IrInstSrc *> instruction_list;
24312431 IrBasicBlockGen *child;
24322432 Scope *scope;
......@@ -2729,7 +2729,7 @@ struct IrInstSrc {
27292729 // can find the instruction that corresponds to this value in the "new ir"
27302730 // with this child field.
27312731 IrInstGen *child;
2732 IrBasicBlockSrc *owner_bb;
2732 Stage1ZirBasicBlock *owner_bb;
27332733
27342734 // for debugging purposes, these are useful to call to inspect the instruction
27352735 void dump();
......@@ -2774,8 +2774,8 @@ struct IrInstSrcCondBr {
27742774 IrInstSrc base;
27752775
27762776 IrInstSrc *condition;
2777 IrBasicBlockSrc *then_block;
2778 IrBasicBlockSrc *else_block;
2777 Stage1ZirBasicBlock *then_block;
2778 Stage1ZirBasicBlock *else_block;
27792779 IrInstSrc *is_comptime;
27802780 ResultLoc *result_loc;
27812781};
......@@ -2791,7 +2791,7 @@ struct IrInstGenCondBr {
27912791struct IrInstSrcBr {
27922792 IrInstSrc base;
27932793
2794 IrBasicBlockSrc *dest_block;
2794 Stage1ZirBasicBlock *dest_block;
27952795 IrInstSrc *is_comptime;
27962796};
27972797
......@@ -2803,14 +2803,14 @@ struct IrInstGenBr {
28032803
28042804struct IrInstSrcSwitchBrCase {
28052805 IrInstSrc *value;
2806 IrBasicBlockSrc *block;
2806 Stage1ZirBasicBlock *block;
28072807};
28082808
28092809struct IrInstSrcSwitchBr {
28102810 IrInstSrc base;
28112811
28122812 IrInstSrc *target_value;
2813 IrBasicBlockSrc *else_block;
2813 Stage1ZirBasicBlock *else_block;
28142814 size_t case_count;
28152815 IrInstSrcSwitchBrCase *cases;
28162816 IrInstSrc *is_comptime;
......@@ -2856,7 +2856,7 @@ struct IrInstSrcPhi {
28562856 IrInstSrc base;
28572857
28582858 size_t incoming_count;
2859 IrBasicBlockSrc **incoming_blocks;
2859 Stage1ZirBasicBlock **incoming_blocks;
28602860 IrInstSrc **incoming_values;
28612861 ResultLocPeerParent *peer_parent;
28622862};
......@@ -4520,7 +4520,7 @@ struct ResultLocPeerParent {
45204520
45214521 bool skipped;
45224522 bool done_resuming;
4523 IrBasicBlockSrc *end_bb;
4523 Stage1ZirBasicBlock *end_bb;
45244524 ResultLoc *parent;
45254525 ZigList<ResultLocPeer *> peers;
45264526 ZigType *resolved_type;
......@@ -4531,7 +4531,7 @@ struct ResultLocPeer {
45314531 ResultLoc base;
45324532
45334533 ResultLocPeerParent *parent;
4534 IrBasicBlockSrc *next_bb;
4534 Stage1ZirBasicBlock *next_bb;
45354535 IrSuspendPosition suspend_pos;
45364536};
45374537
src/stage1/astgen.cpp+96-96
......@@ -14,7 +14,7 @@
1414struct Stage1AstGen {
1515 CodeGen *codegen;
1616 Stage1Zir *exec;
17 IrBasicBlockSrc *current_basic_block;
17 Stage1ZirBasicBlock *current_basic_block;
1818 AstNode *main_block_node;
1919 size_t next_debug_id;
2020 ZigFn *fn;
......@@ -358,7 +358,7 @@ bool ir_should_inline(Stage1Zir *exec, Scope *scope) {
358358 return false;
359359}
360360
361static void ir_instruction_append(IrBasicBlockSrc *basic_block, IrInstSrc *instruction) {
361static void ir_instruction_append(Stage1ZirBasicBlock *basic_block, IrInstSrc *instruction) {
362362 assert(basic_block);
363363 assert(instruction);
364364 basic_block->instruction_list.append(instruction);
......@@ -370,11 +370,11 @@ static size_t irb_next_debug_id(Stage1AstGen *ag) {
370370 return result;
371371}
372372
373static void ir_ref_bb(IrBasicBlockSrc *bb) {
373static void ir_ref_bb(Stage1ZirBasicBlock *bb) {
374374 bb->ref_count += 1;
375375}
376376
377static void ir_ref_instruction(IrInstSrc *instruction, IrBasicBlockSrc *cur_bb) {
377static void ir_ref_instruction(IrInstSrc *instruction, Stage1ZirBasicBlock *cur_bb) {
378378 assert(instruction->id != IrInstSrcIdInvalid);
379379 instruction->base.ref_count += 1;
380380 if (instruction->owner_bb != cur_bb && !instr_is_unreachable(instruction)
......@@ -384,8 +384,8 @@ static void ir_ref_instruction(IrInstSrc *instruction, IrBasicBlockSrc *cur_bb)
384384 }
385385}
386386
387static IrBasicBlockSrc *ir_create_basic_block(Stage1AstGen *ag, Scope *scope, const char *name_hint) {
388 IrBasicBlockSrc *result = heap::c_allocator.create<IrBasicBlockSrc>();
387static Stage1ZirBasicBlock *ir_create_basic_block(Stage1AstGen *ag, Scope *scope, const char *name_hint) {
388 Stage1ZirBasicBlock *result = heap::c_allocator.create<Stage1ZirBasicBlock>();
389389 result->scope = scope;
390390 result->name_hint = name_hint;
391391 result->debug_id = irb_next_debug_id(ag);
......@@ -944,7 +944,7 @@ static T *ir_build_instruction(Stage1AstGen *ag, Scope *scope, AstNode *source_n
944944}
945945
946946static IrInstSrc *ir_build_cond_br(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *condition,
947 IrBasicBlockSrc *then_block, IrBasicBlockSrc *else_block, IrInstSrc *is_comptime)
947 Stage1ZirBasicBlock *then_block, Stage1ZirBasicBlock *else_block, IrInstSrc *is_comptime)
948948{
949949 IrInstSrcCondBr *inst = ir_build_instruction<IrInstSrcCondBr>(ag, scope, source_node);
950950 inst->base.is_noreturn = true;
......@@ -1279,7 +1279,7 @@ static IrInstSrc *ir_build_call_src(Stage1AstGen *ag, Scope *scope, AstNode *sou
12791279}
12801280
12811281static IrInstSrc *ir_build_phi(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1282 size_t incoming_count, IrBasicBlockSrc **incoming_blocks, IrInstSrc **incoming_values,
1282 size_t incoming_count, Stage1ZirBasicBlock **incoming_blocks, IrInstSrc **incoming_values,
12831283 ResultLocPeerParent *peer_parent)
12841284{
12851285 assert(incoming_count != 0);
......@@ -1300,7 +1300,7 @@ static IrInstSrc *ir_build_phi(Stage1AstGen *ag, Scope *scope, AstNode *source_n
13001300}
13011301
13021302static IrInstSrc *ir_build_br(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1303 IrBasicBlockSrc *dest_block, IrInstSrc *is_comptime)
1303 Stage1ZirBasicBlock *dest_block, IrInstSrc *is_comptime)
13041304{
13051305 IrInstSrcBr *inst = ir_build_instruction<IrInstSrcBr>(ag, scope, source_node);
13061306 inst->base.is_noreturn = true;
......@@ -1714,7 +1714,7 @@ static IrInstSrc *ir_build_bit_reverse(Stage1AstGen *ag, Scope *scope, AstNode *
17141714}
17151715
17161716static IrInstSrcSwitchBr *ir_build_switch_br_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1717 IrInstSrc *target_value, IrBasicBlockSrc *else_block, size_t case_count, IrInstSrcSwitchBrCase *cases,
1717 IrInstSrc *target_value, Stage1ZirBasicBlock *else_block, size_t case_count, IrInstSrcSwitchBrCase *cases,
17181718 IrInstSrc *is_comptime, IrInstSrc *switch_prongs_void)
17191719{
17201720 IrInstSrcSwitchBr *instruction = ir_build_instruction<IrInstSrcSwitchBr>(ag, scope, source_node);
......@@ -2976,12 +2976,12 @@ static bool ir_gen_defers_for_block(Stage1AstGen *ag, Scope *inner_scope, Scope
29762976 return true;
29772977}
29782978
2979static void ir_set_cursor_at_end(Stage1AstGen *ag, IrBasicBlockSrc *basic_block) {
2979static void ir_set_cursor_at_end(Stage1AstGen *ag, Stage1ZirBasicBlock *basic_block) {
29802980 assert(basic_block);
29812981 ag->current_basic_block = basic_block;
29822982}
29832983
2984static void ir_set_cursor_at_end_and_append_block(Stage1AstGen *ag, IrBasicBlockSrc *basic_block) {
2984static void ir_set_cursor_at_end_and_append_block(Stage1AstGen *ag, Stage1ZirBasicBlock *basic_block) {
29852985 basic_block->index = ag->exec->basic_block_list.length;
29862986 ag->exec->basic_block_list.append(basic_block);
29872987 ir_set_cursor_at_end(ag, basic_block);
......@@ -3062,8 +3062,8 @@ static IrInstSrc *ir_gen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L
30623062 }
30633063 bool should_inline = ir_should_inline(ag->exec, scope);
30643064
3065 IrBasicBlockSrc *err_block = ir_create_basic_block(ag, scope, "ErrRetErr");
3066 IrBasicBlockSrc *ok_block = ir_create_basic_block(ag, scope, "ErrRetOk");
3065 Stage1ZirBasicBlock *err_block = ir_create_basic_block(ag, scope, "ErrRetErr");
3066 Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, scope, "ErrRetOk");
30673067
30683068 IrInstSrc *is_err = ir_build_test_err_src(ag, scope, node, return_value, false, true);
30693069
......@@ -3075,7 +3075,7 @@ static IrInstSrc *ir_gen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L
30753075 }
30763076
30773077 ir_mark_gen(ir_build_cond_br(ag, scope, node, is_err, err_block, ok_block, is_comptime));
3078 IrBasicBlockSrc *ret_stmt_block = ir_create_basic_block(ag, scope, "RetStmt");
3078 Stage1ZirBasicBlock *ret_stmt_block = ir_create_basic_block(ag, scope, "RetStmt");
30793079
30803080 ir_set_cursor_at_end_and_append_block(ag, err_block);
30813081 if (!ir_gen_defers_for_block(ag, scope, outer_scope, nullptr, return_value))
......@@ -3103,8 +3103,8 @@ static IrInstSrc *ir_gen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L
31033103 return ag->codegen->invalid_inst_src;
31043104 IrInstSrc *is_err_val = ir_build_test_err_src(ag, scope, node, err_union_ptr, true, false);
31053105
3106 IrBasicBlockSrc *return_block = ir_create_basic_block(ag, scope, "ErrRetReturn");
3107 IrBasicBlockSrc *continue_block = ir_create_basic_block(ag, scope, "ErrRetContinue");
3106 Stage1ZirBasicBlock *return_block = ir_create_basic_block(ag, scope, "ErrRetReturn");
3107 Stage1ZirBasicBlock *continue_block = ir_create_basic_block(ag, scope, "ErrRetContinue");
31083108 IrInstSrc *is_comptime;
31093109 bool should_inline = ir_should_inline(ag->exec, scope);
31103110 if (should_inline) {
......@@ -3266,7 +3266,7 @@ static IrInstSrc *ir_gen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *b
32663266 assert(block_node->type == NodeTypeBlock);
32673267
32683268 ZigList<IrInstSrc *> incoming_values = {0};
3269 ZigList<IrBasicBlockSrc *> incoming_blocks = {0};
3269 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
32703270
32713271 if (is_duplicate_label(ag->codegen, parent_scope, block_node, block_node->data.block.name))
32723272 return ag->codegen->invalid_inst_src;
......@@ -3479,7 +3479,7 @@ static IrInstSrc *ir_gen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node)
34793479 IrInstSrc *val1 = ir_gen_node(ag, node->data.bin_op_expr.op1, scope);
34803480 if (val1 == ag->codegen->invalid_inst_src)
34813481 return ag->codegen->invalid_inst_src;
3482 IrBasicBlockSrc *post_val1_block = ag->current_basic_block;
3482 Stage1ZirBasicBlock *post_val1_block = ag->current_basic_block;
34833483
34843484 IrInstSrc *is_comptime;
34853485 if (ir_should_inline(ag->exec, scope)) {
......@@ -3489,9 +3489,9 @@ static IrInstSrc *ir_gen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node)
34893489 }
34903490
34913491 // block for when val1 == false
3492 IrBasicBlockSrc *false_block = ir_create_basic_block(ag, scope, "BoolOrFalse");
3492 Stage1ZirBasicBlock *false_block = ir_create_basic_block(ag, scope, "BoolOrFalse");
34933493 // block for when val1 == true (don't even evaluate the second part)
3494 IrBasicBlockSrc *true_block = ir_create_basic_block(ag, scope, "BoolOrTrue");
3494 Stage1ZirBasicBlock *true_block = ir_create_basic_block(ag, scope, "BoolOrTrue");
34953495
34963496 ir_build_cond_br(ag, scope, node, val1, true_block, false_block, is_comptime);
34973497
......@@ -3499,7 +3499,7 @@ static IrInstSrc *ir_gen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node)
34993499 IrInstSrc *val2 = ir_gen_node(ag, node->data.bin_op_expr.op2, scope);
35003500 if (val2 == ag->codegen->invalid_inst_src)
35013501 return ag->codegen->invalid_inst_src;
3502 IrBasicBlockSrc *post_val2_block = ag->current_basic_block;
3502 Stage1ZirBasicBlock *post_val2_block = ag->current_basic_block;
35033503
35043504 ir_build_br(ag, scope, node, true_block, is_comptime);
35053505
......@@ -3508,7 +3508,7 @@ static IrInstSrc *ir_gen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node)
35083508 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);
35093509 incoming_values[0] = val1;
35103510 incoming_values[1] = val2;
3511 IrBasicBlockSrc **incoming_blocks = heap::c_allocator.allocate<IrBasicBlockSrc *>(2);
3511 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
35123512 incoming_blocks[0] = post_val1_block;
35133513 incoming_blocks[1] = post_val2_block;
35143514
......@@ -3521,7 +3521,7 @@ static IrInstSrc *ir_gen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)
35213521 IrInstSrc *val1 = ir_gen_node(ag, node->data.bin_op_expr.op1, scope);
35223522 if (val1 == ag->codegen->invalid_inst_src)
35233523 return ag->codegen->invalid_inst_src;
3524 IrBasicBlockSrc *post_val1_block = ag->current_basic_block;
3524 Stage1ZirBasicBlock *post_val1_block = ag->current_basic_block;
35253525
35263526 IrInstSrc *is_comptime;
35273527 if (ir_should_inline(ag->exec, scope)) {
......@@ -3531,9 +3531,9 @@ static IrInstSrc *ir_gen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)
35313531 }
35323532
35333533 // block for when val1 == true
3534 IrBasicBlockSrc *true_block = ir_create_basic_block(ag, scope, "BoolAndTrue");
3534 Stage1ZirBasicBlock *true_block = ir_create_basic_block(ag, scope, "BoolAndTrue");
35353535 // block for when val1 == false (don't even evaluate the second part)
3536 IrBasicBlockSrc *false_block = ir_create_basic_block(ag, scope, "BoolAndFalse");
3536 Stage1ZirBasicBlock *false_block = ir_create_basic_block(ag, scope, "BoolAndFalse");
35373537
35383538 ir_build_cond_br(ag, scope, node, val1, true_block, false_block, is_comptime);
35393539
......@@ -3541,7 +3541,7 @@ static IrInstSrc *ir_gen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)
35413541 IrInstSrc *val2 = ir_gen_node(ag, node->data.bin_op_expr.op2, scope);
35423542 if (val2 == ag->codegen->invalid_inst_src)
35433543 return ag->codegen->invalid_inst_src;
3544 IrBasicBlockSrc *post_val2_block = ag->current_basic_block;
3544 Stage1ZirBasicBlock *post_val2_block = ag->current_basic_block;
35453545
35463546 ir_build_br(ag, scope, node, false_block, is_comptime);
35473547
......@@ -3550,7 +3550,7 @@ static IrInstSrc *ir_gen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)
35503550 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);
35513551 incoming_values[0] = val1;
35523552 incoming_values[1] = val2;
3553 IrBasicBlockSrc **incoming_blocks = heap::c_allocator.allocate<IrBasicBlockSrc *>(2);
3553 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
35543554 incoming_blocks[0] = post_val1_block;
35553555 incoming_blocks[1] = post_val2_block;
35563556
......@@ -3558,7 +3558,7 @@ static IrInstSrc *ir_gen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)
35583558}
35593559
35603560static ResultLocPeerParent *ir_build_result_peers(Stage1AstGen *ag, IrInstSrc *cond_br_inst,
3561 IrBasicBlockSrc *end_block, ResultLoc *parent, IrInstSrc *is_comptime)
3561 Stage1ZirBasicBlock *end_block, ResultLoc *parent, IrInstSrc *is_comptime)
35623562{
35633563 ResultLocPeerParent *peer_parent = heap::c_allocator.create<ResultLocPeerParent>();
35643564 peer_parent->base.id = ResultLocIdPeerParent;
......@@ -3578,7 +3578,7 @@ static ResultLocPeerParent *ir_build_result_peers(Stage1AstGen *ag, IrInstSrc *c
35783578}
35793579
35803580static ResultLocPeerParent *ir_build_binary_result_peers(Stage1AstGen *ag, IrInstSrc *cond_br_inst,
3581 IrBasicBlockSrc *else_block, IrBasicBlockSrc *end_block, ResultLoc *parent, IrInstSrc *is_comptime)
3581 Stage1ZirBasicBlock *else_block, Stage1ZirBasicBlock *end_block, ResultLoc *parent, IrInstSrc *is_comptime)
35823582{
35833583 ResultLocPeerParent *peer_parent = ir_build_result_peers(ag, cond_br_inst, end_block, parent, is_comptime);
35843584
......@@ -3613,9 +3613,9 @@ static IrInstSrc *ir_gen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *
36133613 is_comptime = ir_build_test_comptime(ag, parent_scope, node, is_non_null);
36143614 }
36153615
3616 IrBasicBlockSrc *ok_block = ir_create_basic_block(ag, parent_scope, "OptionalNonNull");
3617 IrBasicBlockSrc *null_block = ir_create_basic_block(ag, parent_scope, "OptionalNull");
3618 IrBasicBlockSrc *end_block = ir_create_basic_block(ag, parent_scope, "OptionalEnd");
3616 Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, parent_scope, "OptionalNonNull");
3617 Stage1ZirBasicBlock *null_block = ir_create_basic_block(ag, parent_scope, "OptionalNull");
3618 Stage1ZirBasicBlock *end_block = ir_create_basic_block(ag, parent_scope, "OptionalEnd");
36193619 IrInstSrc *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, is_non_null, ok_block, null_block, is_comptime);
36203620
36213621 ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, ok_block, end_block,
......@@ -3626,7 +3626,7 @@ static IrInstSrc *ir_gen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *
36263626 &peer_parent->peers.at(0)->base);
36273627 if (null_result == ag->codegen->invalid_inst_src)
36283628 return ag->codegen->invalid_inst_src;
3629 IrBasicBlockSrc *after_null_block = ag->current_basic_block;
3629 Stage1ZirBasicBlock *after_null_block = ag->current_basic_block;
36303630 if (!instr_is_unreachable(null_result))
36313631 ir_mark_gen(ir_build_br(ag, parent_scope, node, end_block, is_comptime));
36323632
......@@ -3634,14 +3634,14 @@ static IrInstSrc *ir_gen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *
36343634 IrInstSrc *unwrapped_ptr = ir_build_optional_unwrap_ptr(ag, parent_scope, node, maybe_ptr, false);
36353635 IrInstSrc *unwrapped_payload = ir_build_load_ptr(ag, parent_scope, node, unwrapped_ptr);
36363636 ir_build_end_expr(ag, parent_scope, node, unwrapped_payload, &peer_parent->peers.at(1)->base);
3637 IrBasicBlockSrc *after_ok_block = ag->current_basic_block;
3637 Stage1ZirBasicBlock *after_ok_block = ag->current_basic_block;
36383638 ir_build_br(ag, parent_scope, node, end_block, is_comptime);
36393639
36403640 ir_set_cursor_at_end_and_append_block(ag, end_block);
36413641 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);
36423642 incoming_values[0] = null_result;
36433643 incoming_values[1] = unwrapped_payload;
3644 IrBasicBlockSrc **incoming_blocks = heap::c_allocator.allocate<IrBasicBlockSrc *>(2);
3644 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
36453645 incoming_blocks[0] = after_null_block;
36463646 incoming_blocks[1] = after_ok_block;
36473647 IrInstSrc *phi = ir_build_phi(ag, parent_scope, node, 2, incoming_blocks, incoming_values, peer_parent);
......@@ -5372,9 +5372,9 @@ static IrInstSrc *ir_gen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n
53725372 AstNode *then_node = node->data.if_bool_expr.then_block;
53735373 AstNode *else_node = node->data.if_bool_expr.else_node;
53745374
5375 IrBasicBlockSrc *then_block = ir_create_basic_block(ag, scope, "Then");
5376 IrBasicBlockSrc *else_block = ir_create_basic_block(ag, scope, "Else");
5377 IrBasicBlockSrc *endif_block = ir_create_basic_block(ag, scope, "EndIf");
5375 Stage1ZirBasicBlock *then_block = ir_create_basic_block(ag, scope, "Then");
5376 Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "Else");
5377 Stage1ZirBasicBlock *endif_block = ir_create_basic_block(ag, scope, "EndIf");
53785378
53795379 IrInstSrc *cond_br_inst = ir_build_cond_br(ag, scope, node, condition,
53805380 then_block, else_block, is_comptime);
......@@ -5388,7 +5388,7 @@ static IrInstSrc *ir_gen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n
53885388 &peer_parent->peers.at(0)->base);
53895389 if (then_expr_result == ag->codegen->invalid_inst_src)
53905390 return ag->codegen->invalid_inst_src;
5391 IrBasicBlockSrc *after_then_block = ag->current_basic_block;
5391 Stage1ZirBasicBlock *after_then_block = ag->current_basic_block;
53925392 if (!instr_is_unreachable(then_expr_result))
53935393 ir_mark_gen(ir_build_br(ag, scope, node, endif_block, is_comptime));
53945394
......@@ -5402,7 +5402,7 @@ static IrInstSrc *ir_gen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n
54025402 else_expr_result = ir_build_const_void(ag, scope, node);
54035403 ir_build_end_expr(ag, scope, node, else_expr_result, &peer_parent->peers.at(1)->base);
54045404 }
5405 IrBasicBlockSrc *after_else_block = ag->current_basic_block;
5405 Stage1ZirBasicBlock *after_else_block = ag->current_basic_block;
54065406 if (!instr_is_unreachable(else_expr_result))
54075407 ir_mark_gen(ir_build_br(ag, scope, node, endif_block, is_comptime));
54085408
......@@ -5410,7 +5410,7 @@ static IrInstSrc *ir_gen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n
54105410 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);
54115411 incoming_values[0] = then_expr_result;
54125412 incoming_values[1] = else_expr_result;
5413 IrBasicBlockSrc **incoming_blocks = heap::c_allocator.allocate<IrBasicBlockSrc *>(2);
5413 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
54145414 incoming_blocks[0] = after_then_block;
54155415 incoming_blocks[1] = after_else_block;
54165416
......@@ -5912,12 +5912,12 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
59125912 AstNode *continue_expr_node = node->data.while_expr.continue_expr;
59135913 AstNode *else_node = node->data.while_expr.else_node;
59145914
5915 IrBasicBlockSrc *cond_block = ir_create_basic_block(ag, scope, "WhileCond");
5916 IrBasicBlockSrc *body_block = ir_create_basic_block(ag, scope, "WhileBody");
5917 IrBasicBlockSrc *continue_block = continue_expr_node ?
5915 Stage1ZirBasicBlock *cond_block = ir_create_basic_block(ag, scope, "WhileCond");
5916 Stage1ZirBasicBlock *body_block = ir_create_basic_block(ag, scope, "WhileBody");
5917 Stage1ZirBasicBlock *continue_block = continue_expr_node ?
59185918 ir_create_basic_block(ag, scope, "WhileContinue") : cond_block;
5919 IrBasicBlockSrc *end_block = ir_create_basic_block(ag, scope, "WhileEnd");
5920 IrBasicBlockSrc *else_block = else_node ?
5919 Stage1ZirBasicBlock *end_block = ir_create_basic_block(ag, scope, "WhileEnd");
5920 Stage1ZirBasicBlock *else_block = else_node ?
59215921 ir_create_basic_block(ag, scope, "WhileElse") : end_block;
59225922
59235923 IrInstSrc *is_comptime = ir_build_const_bool(ag, scope, node,
......@@ -5948,7 +5948,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
59485948 return err_val_ptr;
59495949 IrInstSrc *is_err = ir_build_test_err_src(ag, scope, node->data.while_expr.condition, err_val_ptr,
59505950 true, false);
5951 IrBasicBlockSrc *after_cond_block = ag->current_basic_block;
5951 Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block;
59525952 IrInstSrc *void_else_result = else_node ? nullptr : ir_mark_gen(ir_build_const_void(ag, scope, node));
59535953 IrInstSrc *cond_br_inst;
59545954 if (!instr_is_unreachable(is_err)) {
......@@ -5973,7 +5973,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
59735973 }
59745974
59755975 ZigList<IrInstSrc *> incoming_values = {0};
5976 ZigList<IrBasicBlockSrc *> incoming_blocks = {0};
5976 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
59775977
59785978 if (is_duplicate_label(ag->codegen, payload_scope, node, node->data.while_expr.name))
59795979 return ag->codegen->invalid_inst_src;
......@@ -6037,7 +6037,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
60376037 return else_result;
60386038 if (!instr_is_unreachable(else_result))
60396039 ir_mark_gen(ir_build_br(ag, scope, node, end_block, is_comptime));
6040 IrBasicBlockSrc *after_else_block = ag->current_basic_block;
6040 Stage1ZirBasicBlock *after_else_block = ag->current_basic_block;
60416041 ir_set_cursor_at_end_and_append_block(ag, end_block);
60426042 if (else_result) {
60436043 incoming_blocks.append(after_else_block);
......@@ -6069,7 +6069,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
60696069 return maybe_val_ptr;
60706070 IrInstSrc *maybe_val = ir_build_load_ptr(ag, scope, node->data.while_expr.condition, maybe_val_ptr);
60716071 IrInstSrc *is_non_null = ir_build_test_non_null_src(ag, scope, node->data.while_expr.condition, maybe_val);
6072 IrBasicBlockSrc *after_cond_block = ag->current_basic_block;
6072 Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block;
60736073 IrInstSrc *void_else_result = else_node ? nullptr : ir_mark_gen(ir_build_const_void(ag, scope, node));
60746074 IrInstSrc *cond_br_inst;
60756075 if (!instr_is_unreachable(is_non_null)) {
......@@ -6091,7 +6091,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
60916091 build_decl_var_and_init(ag, child_scope, symbol_node, payload_var, var_value, buf_ptr(var_symbol), is_comptime);
60926092
60936093 ZigList<IrInstSrc *> incoming_values = {0};
6094 ZigList<IrBasicBlockSrc *> incoming_blocks = {0};
6094 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
60956095
60966096 if (is_duplicate_label(ag->codegen, child_scope, node, node->data.while_expr.name))
60976097 return ag->codegen->invalid_inst_src;
......@@ -6148,7 +6148,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
61486148 if (!instr_is_unreachable(else_result))
61496149 ir_mark_gen(ir_build_br(ag, scope, node, end_block, is_comptime));
61506150 }
6151 IrBasicBlockSrc *after_else_block = ag->current_basic_block;
6151 Stage1ZirBasicBlock *after_else_block = ag->current_basic_block;
61526152 ir_set_cursor_at_end_and_append_block(ag, end_block);
61536153 if (else_result) {
61546154 incoming_blocks.append(after_else_block);
......@@ -6169,7 +6169,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
61696169 IrInstSrc *cond_val = ir_gen_node(ag, node->data.while_expr.condition, scope);
61706170 if (cond_val == ag->codegen->invalid_inst_src)
61716171 return cond_val;
6172 IrBasicBlockSrc *after_cond_block = ag->current_basic_block;
6172 Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block;
61736173 IrInstSrc *void_else_result = else_node ? nullptr : ir_mark_gen(ir_build_const_void(ag, scope, node));
61746174 IrInstSrc *cond_br_inst;
61756175 if (!instr_is_unreachable(cond_val)) {
......@@ -6186,7 +6186,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
61866186 ir_set_cursor_at_end_and_append_block(ag, body_block);
61876187
61886188 ZigList<IrInstSrc *> incoming_values = {0};
6189 ZigList<IrBasicBlockSrc *> incoming_blocks = {0};
6189 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
61906190
61916191 Scope *subexpr_scope = create_runtime_scope(ag->codegen, node, scope, is_comptime);
61926192
......@@ -6245,7 +6245,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
62456245 if (!instr_is_unreachable(else_result))
62466246 ir_mark_gen(ir_build_br(ag, scope, node, end_block, is_comptime));
62476247 }
6248 IrBasicBlockSrc *after_else_block = ag->current_basic_block;
6248 Stage1ZirBasicBlock *after_else_block = ag->current_basic_block;
62496249 ir_set_cursor_at_end_and_append_block(ag, end_block);
62506250 if (else_result) {
62516251 incoming_blocks.append(after_else_block);
......@@ -6312,11 +6312,11 @@ static IrInstSrc *ir_gen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode
63126312 IrInstSrc *index_ptr = ir_build_var_ptr(ag, parent_scope, node, index_var);
63136313
63146314
6315 IrBasicBlockSrc *cond_block = ir_create_basic_block(ag, parent_scope, "ForCond");
6316 IrBasicBlockSrc *body_block = ir_create_basic_block(ag, parent_scope, "ForBody");
6317 IrBasicBlockSrc *end_block = ir_create_basic_block(ag, parent_scope, "ForEnd");
6318 IrBasicBlockSrc *else_block = else_node ? ir_create_basic_block(ag, parent_scope, "ForElse") : end_block;
6319 IrBasicBlockSrc *continue_block = ir_create_basic_block(ag, parent_scope, "ForContinue");
6315 Stage1ZirBasicBlock *cond_block = ir_create_basic_block(ag, parent_scope, "ForCond");
6316 Stage1ZirBasicBlock *body_block = ir_create_basic_block(ag, parent_scope, "ForBody");
6317 Stage1ZirBasicBlock *end_block = ir_create_basic_block(ag, parent_scope, "ForEnd");
6318 Stage1ZirBasicBlock *else_block = else_node ? ir_create_basic_block(ag, parent_scope, "ForElse") : end_block;
6319 Stage1ZirBasicBlock *continue_block = ir_create_basic_block(ag, parent_scope, "ForContinue");
63206320
63216321 Buf *len_field_name = buf_create_from_str("len");
63226322 IrInstSrc *len_ref = ir_build_field_ptr(ag, parent_scope, node, array_val_ptr, len_field_name, false);
......@@ -6326,7 +6326,7 @@ static IrInstSrc *ir_gen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode
63266326 ir_set_cursor_at_end_and_append_block(ag, cond_block);
63276327 IrInstSrc *index_val = ir_build_load_ptr(ag, &spill_scope->base, node, index_ptr);
63286328 IrInstSrc *cond = ir_build_bin_op(ag, parent_scope, node, IrBinOpCmpLessThan, index_val, len_val, false);
6329 IrBasicBlockSrc *after_cond_block = ag->current_basic_block;
6329 Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block;
63306330 IrInstSrc *void_else_value = else_node ? nullptr : ir_mark_gen(ir_build_const_void(ag, parent_scope, node));
63316331 IrInstSrc *cond_br_inst = ir_mark_gen(ir_build_cond_br(ag, parent_scope, node, cond,
63326332 body_block, else_block, is_comptime));
......@@ -6349,7 +6349,7 @@ static IrInstSrc *ir_gen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode
63496349 return ag->codegen->invalid_inst_src;
63506350
63516351 ZigList<IrInstSrc *> incoming_values = {0};
6352 ZigList<IrBasicBlockSrc *> incoming_blocks = {0};
6352 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
63536353 ScopeLoop *loop_scope = create_loop_scope(ag->codegen, node, child_scope);
63546354 loop_scope->break_block = end_block;
63556355 loop_scope->continue_block = continue_block;
......@@ -6396,7 +6396,7 @@ static IrInstSrc *ir_gen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode
63966396 if (!instr_is_unreachable(else_result))
63976397 ir_mark_gen(ir_build_br(ag, parent_scope, node, end_block, is_comptime));
63986398 }
6399 IrBasicBlockSrc *after_else_block = ag->current_basic_block;
6399 Stage1ZirBasicBlock *after_else_block = ag->current_basic_block;
64006400 ir_set_cursor_at_end_and_append_block(ag, end_block);
64016401
64026402 if (else_result) {
......@@ -6667,9 +6667,9 @@ static IrInstSrc *ir_gen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod
66676667 IrInstSrc *maybe_val = ir_build_load_ptr(ag, scope, node, maybe_val_ptr);
66686668 IrInstSrc *is_non_null = ir_build_test_non_null_src(ag, scope, node, maybe_val);
66696669
6670 IrBasicBlockSrc *then_block = ir_create_basic_block(ag, scope, "OptionalThen");
6671 IrBasicBlockSrc *else_block = ir_create_basic_block(ag, scope, "OptionalElse");
6672 IrBasicBlockSrc *endif_block = ir_create_basic_block(ag, scope, "OptionalEndIf");
6670 Stage1ZirBasicBlock *then_block = ir_create_basic_block(ag, scope, "OptionalThen");
6671 Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "OptionalElse");
6672 Stage1ZirBasicBlock *endif_block = ir_create_basic_block(ag, scope, "OptionalEndIf");
66736673
66746674 IrInstSrc *is_comptime;
66756675 if (ir_should_inline(ag->exec, scope)) {
......@@ -6705,7 +6705,7 @@ static IrInstSrc *ir_gen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod
67056705 &peer_parent->peers.at(0)->base);
67066706 if (then_expr_result == ag->codegen->invalid_inst_src)
67076707 return then_expr_result;
6708 IrBasicBlockSrc *after_then_block = ag->current_basic_block;
6708 Stage1ZirBasicBlock *after_then_block = ag->current_basic_block;
67096709 if (!instr_is_unreachable(then_expr_result))
67106710 ir_mark_gen(ir_build_br(ag, scope, node, endif_block, is_comptime));
67116711
......@@ -6719,7 +6719,7 @@ static IrInstSrc *ir_gen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod
67196719 else_expr_result = ir_build_const_void(ag, scope, node);
67206720 ir_build_end_expr(ag, scope, node, else_expr_result, &peer_parent->peers.at(1)->base);
67216721 }
6722 IrBasicBlockSrc *after_else_block = ag->current_basic_block;
6722 Stage1ZirBasicBlock *after_else_block = ag->current_basic_block;
67236723 if (!instr_is_unreachable(else_expr_result))
67246724 ir_mark_gen(ir_build_br(ag, scope, node, endif_block, is_comptime));
67256725
......@@ -6727,7 +6727,7 @@ static IrInstSrc *ir_gen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod
67276727 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);
67286728 incoming_values[0] = then_expr_result;
67296729 incoming_values[1] = else_expr_result;
6730 IrBasicBlockSrc **incoming_blocks = heap::c_allocator.allocate<IrBasicBlockSrc *>(2);
6730 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
67316731 incoming_blocks[0] = after_then_block;
67326732 incoming_blocks[1] = after_else_block;
67336733
......@@ -6755,9 +6755,9 @@ static IrInstSrc *ir_gen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
67556755 IrInstSrc *err_val = ir_build_load_ptr(ag, scope, node, err_val_ptr);
67566756 IrInstSrc *is_err = ir_build_test_err_src(ag, scope, node, err_val_ptr, true, false);
67576757
6758 IrBasicBlockSrc *ok_block = ir_create_basic_block(ag, scope, "TryOk");
6759 IrBasicBlockSrc *else_block = ir_create_basic_block(ag, scope, "TryElse");
6760 IrBasicBlockSrc *endif_block = ir_create_basic_block(ag, scope, "TryEnd");
6758 Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, scope, "TryOk");
6759 Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "TryElse");
6760 Stage1ZirBasicBlock *endif_block = ir_create_basic_block(ag, scope, "TryEnd");
67616761
67626762 bool force_comptime = ir_should_inline(ag->exec, scope);
67636763 IrInstSrc *is_comptime = force_comptime ? ir_build_const_bool(ag, scope, node, true) : ir_build_test_comptime(ag, scope, node, is_err);
......@@ -6788,7 +6788,7 @@ static IrInstSrc *ir_gen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
67886788 &peer_parent->peers.at(0)->base);
67896789 if (then_expr_result == ag->codegen->invalid_inst_src)
67906790 return then_expr_result;
6791 IrBasicBlockSrc *after_then_block = ag->current_basic_block;
6791 Stage1ZirBasicBlock *after_then_block = ag->current_basic_block;
67926792 if (!instr_is_unreachable(then_expr_result))
67936793 ir_mark_gen(ir_build_br(ag, scope, node, endif_block, is_comptime));
67946794
......@@ -6817,7 +6817,7 @@ static IrInstSrc *ir_gen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
68176817 else_expr_result = ir_build_const_void(ag, scope, node);
68186818 ir_build_end_expr(ag, scope, node, else_expr_result, &peer_parent->peers.at(1)->base);
68196819 }
6820 IrBasicBlockSrc *after_else_block = ag->current_basic_block;
6820 Stage1ZirBasicBlock *after_else_block = ag->current_basic_block;
68216821 if (!instr_is_unreachable(else_expr_result))
68226822 ir_mark_gen(ir_build_br(ag, scope, node, endif_block, is_comptime));
68236823
......@@ -6825,7 +6825,7 @@ static IrInstSrc *ir_gen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
68256825 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);
68266826 incoming_values[0] = then_expr_result;
68276827 incoming_values[1] = else_expr_result;
6828 IrBasicBlockSrc **incoming_blocks = heap::c_allocator.allocate<IrBasicBlockSrc *>(2);
6828 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
68296829 incoming_blocks[0] = after_then_block;
68306830 incoming_blocks[1] = after_else_block;
68316831
......@@ -6834,9 +6834,9 @@ static IrInstSrc *ir_gen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
68346834}
68356835
68366836static bool ir_gen_switch_prong_expr(Stage1AstGen *ag, Scope *scope, AstNode *switch_node, AstNode *prong_node,
6837 IrBasicBlockSrc *end_block, IrInstSrc *is_comptime, IrInstSrc *var_is_comptime,
6837 Stage1ZirBasicBlock *end_block, IrInstSrc *is_comptime, IrInstSrc *var_is_comptime,
68386838 IrInstSrc *target_value_ptr, IrInstSrc **prong_values, size_t prong_values_len,
6839 ZigList<IrBasicBlockSrc *> *incoming_blocks, ZigList<IrInstSrc *> *incoming_values,
6839 ZigList<Stage1ZirBasicBlock *> *incoming_blocks, ZigList<IrInstSrc *> *incoming_values,
68406840 IrInstSrcSwitchElseVar **out_switch_else_var, LVal lval, ResultLoc *result_loc)
68416841{
68426842 assert(switch_node->type == NodeTypeSwitchExpr);
......@@ -6898,8 +6898,8 @@ static IrInstSrc *ir_gen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
68986898 return target_value_ptr;
68996899 IrInstSrc *target_value = ir_build_switch_target(ag, scope, node, target_value_ptr);
69006900
6901 IrBasicBlockSrc *else_block = ir_create_basic_block(ag, scope, "SwitchElse");
6902 IrBasicBlockSrc *end_block = ir_create_basic_block(ag, scope, "SwitchEnd");
6901 Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "SwitchElse");
6902 Stage1ZirBasicBlock *end_block = ir_create_basic_block(ag, scope, "SwitchEnd");
69036903
69046904 size_t prong_count = node->data.switch_expr.prongs.length;
69056905 ZigList<IrInstSrcSwitchBrCase> cases = {0};
......@@ -6915,7 +6915,7 @@ static IrInstSrc *ir_gen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
69156915 }
69166916
69176917 ZigList<IrInstSrc *> incoming_values = {0};
6918 ZigList<IrBasicBlockSrc *> incoming_blocks = {0};
6918 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
69196919 ZigList<IrInstSrcCheckSwitchProngsRange> check_ranges = {0};
69206920
69216921 IrInstSrcSwitchElseVar *switch_else_var = nullptr;
......@@ -6991,8 +6991,8 @@ static IrInstSrc *ir_gen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
69916991 }
69926992 }
69936993
6994 IrBasicBlockSrc *range_block_yes = ir_create_basic_block(ag, scope, "SwitchRangeYes");
6995 IrBasicBlockSrc *range_block_no = ir_create_basic_block(ag, scope, "SwitchRangeNo");
6994 Stage1ZirBasicBlock *range_block_yes = ir_create_basic_block(ag, scope, "SwitchRangeYes");
6995 Stage1ZirBasicBlock *range_block_no = ir_create_basic_block(ag, scope, "SwitchRangeNo");
69966996
69976997 assert(ok_bit);
69986998 assert(last_item_node);
......@@ -7052,7 +7052,7 @@ static IrInstSrc *ir_gen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
70527052 }
70537053 ResultLocPeer *this_peer_result_loc = create_peer_result(peer_parent);
70547054
7055 IrBasicBlockSrc *prev_block = ag->current_basic_block;
7055 Stage1ZirBasicBlock *prev_block = ag->current_basic_block;
70567056 if (peer_parent->peers.length > 0) {
70577057 peer_parent->peers.last()->next_bb = else_block;
70587058 }
......@@ -7081,7 +7081,7 @@ static IrInstSrc *ir_gen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
70817081
70827082 ResultLocPeer *this_peer_result_loc = create_peer_result(peer_parent);
70837083
7084 IrBasicBlockSrc *prong_block = ir_create_basic_block(ag, scope, "SwitchProng");
7084 Stage1ZirBasicBlock *prong_block = ir_create_basic_block(ag, scope, "SwitchProng");
70857085 IrInstSrc **items = heap::c_allocator.allocate<IrInstSrc *>(prong_item_count);
70867086
70877087 for (size_t item_i = 0; item_i < prong_item_count; item_i += 1) {
......@@ -7103,7 +7103,7 @@ static IrInstSrc *ir_gen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
71037103 items[item_i] = item_value;
71047104 }
71057105
7106 IrBasicBlockSrc *prev_block = ag->current_basic_block;
7106 Stage1ZirBasicBlock *prev_block = ag->current_basic_block;
71077107 if (peer_parent->peers.length > 0) {
71087108 peer_parent->peers.last()->next_bb = prong_block;
71097109 }
......@@ -7202,7 +7202,7 @@ static IrInstSrc *ir_gen_return_from_block(Stage1AstGen *ag, Scope *break_scope,
72027202 result_value = ir_build_const_void(ag, break_scope, node);
72037203 }
72047204
7205 IrBasicBlockSrc *dest_block = block_scope->end_block;
7205 Stage1ZirBasicBlock *dest_block = block_scope->end_block;
72067206 if (!ir_gen_defers_for_block(ag, break_scope, dest_block->scope, nullptr, nullptr))
72077207 return ag->codegen->invalid_inst_src;
72087208
......@@ -7279,7 +7279,7 @@ static IrInstSrc *ir_gen_break(Stage1AstGen *ag, Scope *break_scope, AstNode *no
72797279 result_value = ir_build_const_void(ag, break_scope, node);
72807280 }
72817281
7282 IrBasicBlockSrc *dest_block = loop_scope->break_block;
7282 Stage1ZirBasicBlock *dest_block = loop_scope->break_block;
72837283 if (!ir_gen_defers_for_block(ag, break_scope, dest_block->scope, nullptr, nullptr))
72847284 return ag->codegen->invalid_inst_src;
72857285
......@@ -7341,7 +7341,7 @@ static IrInstSrc *ir_gen_continue(Stage1AstGen *ag, Scope *continue_scope, AstNo
73417341 }
73427342 runtime_scopes.deinit();
73437343
7344 IrBasicBlockSrc *dest_block = loop_scope->continue_block;
7344 Stage1ZirBasicBlock *dest_block = loop_scope->continue_block;
73457345 if (!ir_gen_defers_for_block(ag, continue_scope, dest_block->scope, nullptr, nullptr))
73467346 return ag->codegen->invalid_inst_src;
73477347 return ir_mark_gen(ir_build_br(ag, continue_scope, node, dest_block, is_comptime));
......@@ -7440,9 +7440,9 @@ static IrInstSrc *ir_gen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n
74407440 is_comptime = ir_build_test_comptime(ag, parent_scope, node, is_err);
74417441 }
74427442
7443 IrBasicBlockSrc *ok_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrOk");
7444 IrBasicBlockSrc *err_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrError");
7445 IrBasicBlockSrc *end_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrEnd");
7443 Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrOk");
7444 Stage1ZirBasicBlock *err_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrError");
7445 Stage1ZirBasicBlock *end_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrEnd");
74467446 IrInstSrc *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, is_err, err_block, ok_block, is_comptime);
74477447
74487448 ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, ok_block, end_block, result_loc,
......@@ -7468,7 +7468,7 @@ static IrInstSrc *ir_gen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n
74687468 IrInstSrc *err_result = ir_gen_node_extra(ag, op2_node, err_scope, LValNone, &peer_parent->peers.at(0)->base);
74697469 if (err_result == ag->codegen->invalid_inst_src)
74707470 return ag->codegen->invalid_inst_src;
7471 IrBasicBlockSrc *after_err_block = ag->current_basic_block;
7471 Stage1ZirBasicBlock *after_err_block = ag->current_basic_block;
74727472 if (!instr_is_unreachable(err_result))
74737473 ir_mark_gen(ir_build_br(ag, parent_scope, node, end_block, is_comptime));
74747474
......@@ -7476,14 +7476,14 @@ static IrInstSrc *ir_gen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n
74767476 IrInstSrc *unwrapped_ptr = ir_build_unwrap_err_payload_src(ag, parent_scope, node, err_union_ptr, false, false);
74777477 IrInstSrc *unwrapped_payload = ir_build_load_ptr(ag, parent_scope, node, unwrapped_ptr);
74787478 ir_build_end_expr(ag, parent_scope, node, unwrapped_payload, &peer_parent->peers.at(1)->base);
7479 IrBasicBlockSrc *after_ok_block = ag->current_basic_block;
7479 Stage1ZirBasicBlock *after_ok_block = ag->current_basic_block;
74807480 ir_build_br(ag, parent_scope, node, end_block, is_comptime);
74817481
74827482 ir_set_cursor_at_end_and_append_block(ag, end_block);
74837483 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);
74847484 incoming_values[0] = err_result;
74857485 incoming_values[1] = unwrapped_payload;
7486 IrBasicBlockSrc **incoming_blocks = heap::c_allocator.allocate<IrBasicBlockSrc *>(2);
7486 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
74877487 incoming_blocks[0] = after_err_block;
74887488 incoming_blocks[1] = after_ok_block;
74897489 IrInstSrc *phi = ir_build_phi(ag, parent_scope, node, 2, incoming_blocks, incoming_values, peer_parent);
......@@ -8045,7 +8045,7 @@ bool stage1_astgen(CodeGen *codegen, AstNode *node, Scope *scope, Stage1Zir *sta
80458045 ag->exec = stage1_zir;
80468046 ag->main_block_node = node;
80478047
8048 IrBasicBlockSrc *entry_block = ir_create_basic_block(ag, scope, "Entry");
8048 Stage1ZirBasicBlock *entry_block = ir_create_basic_block(ag, scope, "Entry");
80498049 ir_set_cursor_at_end_and_append_block(ag, entry_block);
80508050 // Entry block gets a reference because we enter it to begin.
80518051 ir_ref_bb(ag->current_basic_block);
src/stage1/ir.cpp+18-18
......@@ -34,7 +34,7 @@ struct IrBuilderGen {
3434struct IrAnalyze {
3535 CodeGen *codegen;
3636 Stage1Zir *zir;
37 IrBasicBlockSrc *zir_current_basic_block;
37 Stage1ZirBasicBlock *zir_current_basic_block;
3838 IrBuilderGen new_irb;
3939 size_t old_bb_index;
4040 size_t instruction_index;
......@@ -42,7 +42,7 @@ struct IrAnalyze {
4242 AstNode *explicit_return_type_source_node;
4343 ZigList<IrInstGen *> src_implicit_return_type_list;
4444 ZigList<IrSuspendPosition> resume_stack;
45 IrBasicBlockSrc *const_predecessor_bb;
45 Stage1ZirBasicBlock *const_predecessor_bb;
4646 size_t ref_count;
4747 size_t break_debug_id; // for debugging purposes
4848 IrInstGen *return_ptr;
......@@ -482,7 +482,7 @@ static void ira_deref(IrAnalyze *ira) {
482482 assert(ira->ref_count != 0);
483483
484484 for (size_t bb_i = 0; bb_i < ira->zir->basic_block_list.length; bb_i += 1) {
485 IrBasicBlockSrc *pass1_bb = ira->zir->basic_block_list.items[bb_i];
485 Stage1ZirBasicBlock *pass1_bb = ira->zir->basic_block_list.items[bb_i];
486486 for (size_t inst_i = 0; inst_i < pass1_bb->instruction_list.length; inst_i += 1) {
487487 IrInstSrc *pass1_inst = pass1_bb->instruction_list.items[inst_i];
488488 destroy_instruction_src(pass1_inst);
......@@ -742,7 +742,7 @@ static IrBasicBlockGen *ir_create_basic_block_gen(IrAnalyze *ira, Scope *scope,
742742 return result;
743743}
744744
745static IrBasicBlockGen *ir_build_bb_from(IrAnalyze *ira, IrBasicBlockSrc *other_bb) {
745static IrBasicBlockGen *ir_build_bb_from(IrAnalyze *ira, Stage1ZirBasicBlock *other_bb) {
746746 IrBasicBlockGen *new_bb = ir_create_basic_block_gen(ira, other_bb->scope, other_bb->name_hint);
747747 other_bb->child = new_bb;
748748 return new_bb;
......@@ -5261,7 +5261,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, IrInst* sourc
52615261 return ir_build_ptr_of_array_to_slice(ira, source_instr, wanted_type, array_ptr, result_loc_inst);
52625262}
52635263
5264static IrBasicBlockGen *ir_get_new_bb(IrAnalyze *ira, IrBasicBlockSrc *old_bb, IrInst *ref_old_instruction) {
5264static IrBasicBlockGen *ir_get_new_bb(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb, IrInst *ref_old_instruction) {
52655265 assert(old_bb);
52665266
52675267 if (old_bb->child) {
......@@ -5276,7 +5276,7 @@ static IrBasicBlockGen *ir_get_new_bb(IrAnalyze *ira, IrBasicBlockSrc *old_bb, I
52765276 return new_bb;
52775277}
52785278
5279static IrBasicBlockGen *ir_get_new_bb_runtime(IrAnalyze *ira, IrBasicBlockSrc *old_bb, IrInst *ref_old_instruction) {
5279static IrBasicBlockGen *ir_get_new_bb_runtime(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb, IrInst *ref_old_instruction) {
52805280 assert(ref_old_instruction != nullptr);
52815281 IrBasicBlockGen *new_bb = ir_get_new_bb(ira, old_bb, ref_old_instruction);
52825282 if (new_bb->must_be_comptime_source_instr) {
......@@ -5289,7 +5289,7 @@ static IrBasicBlockGen *ir_get_new_bb_runtime(IrAnalyze *ira, IrBasicBlockSrc *o
52895289 return new_bb;
52905290}
52915291
5292static void ir_start_bb(IrAnalyze *ira, IrBasicBlockSrc *old_bb, IrBasicBlockSrc *const_predecessor_bb) {
5292static void ir_start_bb(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb, Stage1ZirBasicBlock *const_predecessor_bb) {
52935293 ir_assert(!old_bb->suspended, (old_bb->instruction_list.length != 0) ? &old_bb->instruction_list.at(0)->base : nullptr);
52945294 ira->instruction_index = 0;
52955295 ira->zir_current_basic_block = old_bb;
......@@ -5297,7 +5297,7 @@ static void ir_start_bb(IrAnalyze *ira, IrBasicBlockSrc *old_bb, IrBasicBlockSrc
52975297 ira->old_bb_index = old_bb->index;
52985298}
52995299
5300static IrInstGen *ira_suspend(IrAnalyze *ira, IrInst *old_instruction, IrBasicBlockSrc *next_bb,
5300static IrInstGen *ira_suspend(IrAnalyze *ira, IrInst *old_instruction, Stage1ZirBasicBlock *next_bb,
53015301 IrSuspendPosition *suspend_pos)
53025302{
53035303 if (ira->codegen->verbose_ir) {
......@@ -5356,7 +5356,7 @@ static void ir_start_next_bb(IrAnalyze *ira) {
53565356 bool need_repeat = true;
53575357 for (;;) {
53585358 while (ira->old_bb_index < ira->zir->basic_block_list.length) {
5359 IrBasicBlockSrc *old_bb = ira->zir->basic_block_list.at(ira->old_bb_index);
5359 Stage1ZirBasicBlock *old_bb = ira->zir->basic_block_list.at(ira->old_bb_index);
53605360 if (old_bb->child == nullptr && old_bb->suspend_instruction_ref == nullptr) {
53615361 ira->old_bb_index += 1;
53625362 continue;
......@@ -5447,7 +5447,7 @@ static bool ir_emit_backward_branch(IrAnalyze *ira, IrInst* source_instruction)
54475447 return true;
54485448}
54495449
5450static IrInstGen *ir_inline_bb(IrAnalyze *ira, IrInst* source_instruction, IrBasicBlockSrc *old_bb) {
5450static IrInstGen *ir_inline_bb(IrAnalyze *ira, IrInst* source_instruction, Stage1ZirBasicBlock *old_bb) {
54515451 if (old_bb->debug_id <= ira->zir_current_basic_block->debug_id) {
54525452 if (!ir_emit_backward_branch(ira, source_instruction))
54535453 return ir_unreach_error(ira);
......@@ -13776,20 +13776,20 @@ static IrInstGen *ir_analyze_instruction_un_op(IrAnalyze *ira, IrInstSrcUnOp *in
1377613776}
1377713777
1377813778static void ir_push_resume(IrAnalyze *ira, IrSuspendPosition pos) {
13779 IrBasicBlockSrc *old_bb = ira->zir->basic_block_list.at(pos.basic_block_index);
13779 Stage1ZirBasicBlock *old_bb = ira->zir->basic_block_list.at(pos.basic_block_index);
1378013780 if (old_bb->in_resume_stack) return;
1378113781 ira->resume_stack.append(pos);
1378213782 old_bb->in_resume_stack = true;
1378313783}
1378413784
13785static void ir_push_resume_block(IrAnalyze *ira, IrBasicBlockSrc *old_bb) {
13785static void ir_push_resume_block(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb) {
1378613786 if (ira->resume_stack.length != 0) {
1378713787 ir_push_resume(ira, {old_bb->index, 0});
1378813788 }
1378913789}
1379013790
1379113791static IrInstGen *ir_analyze_instruction_br(IrAnalyze *ira, IrInstSrcBr *br_instruction) {
13792 IrBasicBlockSrc *old_dest_block = br_instruction->dest_block;
13792 Stage1ZirBasicBlock *old_dest_block = br_instruction->dest_block;
1379313793
1379413794 bool is_comptime;
1379513795 if (!ir_resolve_comptime(ira, br_instruction->is_comptime->child, &is_comptime))
......@@ -13827,7 +13827,7 @@ static IrInstGen *ir_analyze_instruction_cond_br(IrAnalyze *ira, IrInstSrcCondBr
1382713827 if (!ir_resolve_bool(ira, casted_condition, &cond_is_true))
1382813828 return ir_unreach_error(ira);
1382913829
13830 IrBasicBlockSrc *old_dest_block = cond_is_true ?
13830 Stage1ZirBasicBlock *old_dest_block = cond_is_true ?
1383113831 cond_br_instruction->then_block : cond_br_instruction->else_block;
1383213832
1383313833 if (is_comptime || (old_dest_block->ref_count == 1 && old_dest_block->suspend_instruction_ref == nullptr))
......@@ -13877,7 +13877,7 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
1387713877
1387813878 if (ira->const_predecessor_bb) {
1387913879 for (size_t i = 0; i < phi_instruction->incoming_count; i += 1) {
13880 IrBasicBlockSrc *predecessor = phi_instruction->incoming_blocks[i];
13880 Stage1ZirBasicBlock *predecessor = phi_instruction->incoming_blocks[i];
1388113881 if (predecessor != ira->const_predecessor_bb)
1388213882 continue;
1388313883 IrInstGen *value = phi_instruction->incoming_values[i]->child;
......@@ -13977,7 +13977,7 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
1397713977 ZigList<IrInstGen*> new_incoming_values = {0};
1397813978
1397913979 for (size_t i = 0; i < phi_instruction->incoming_count; i += 1) {
13980 IrBasicBlockSrc *predecessor = phi_instruction->incoming_blocks[i];
13980 Stage1ZirBasicBlock *predecessor = phi_instruction->incoming_blocks[i];
1398113981 if (predecessor->ref_count == 0)
1398213982 continue;
1398313983
......@@ -15996,7 +15996,7 @@ static IrInstGen *ir_analyze_instruction_switch_br(IrAnalyze *ira,
1599615996 if (!target_val)
1599715997 return ir_unreach_error(ira);
1599815998
15999 IrBasicBlockSrc *old_dest_block = switch_br_instruction->else_block;
15999 Stage1ZirBasicBlock *old_dest_block = switch_br_instruction->else_block;
1600016000 for (size_t i = 0; i < case_count; i += 1) {
1600116001 IrInstSrcSwitchBrCase *old_case = &switch_br_instruction->cases[i];
1600216002 IrInstGen *case_value = old_case->value->child;
......@@ -24488,7 +24488,7 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a
2448824488 ira->new_irb.codegen = codegen;
2448924489 ira->new_irb.exec = stage1_air;
2449024490
24491 IrBasicBlockSrc *old_entry_bb = ira->zir->basic_block_list.at(0);
24491 Stage1ZirBasicBlock *old_entry_bb = ira->zir->basic_block_list.at(0);
2449224492 IrBasicBlockGen *new_entry_bb = ir_get_new_bb(ira, old_entry_bb, nullptr);
2449324493 ira->new_irb.current_basic_block = new_entry_bb;
2449424494 ira->old_bb_index = 0;
src/stage1/ir_print.cpp+4-4
......@@ -633,7 +633,7 @@ static void ir_print_other_inst_gen(IrPrintGen *irp, IrInstGen *inst) {
633633 }
634634}
635635
636static void ir_print_other_block(IrPrintSrc *irp, IrBasicBlockSrc *bb) {
636static void ir_print_other_block(IrPrintSrc *irp, Stage1ZirBasicBlock *bb) {
637637 if (bb == nullptr) {
638638 fprintf(irp->f, "(null block)");
639639 } else {
......@@ -1006,7 +1006,7 @@ static void ir_print_phi(IrPrintSrc *irp, IrInstSrcPhi *phi_instruction) {
10061006 assert(phi_instruction->incoming_count != 0);
10071007 assert(phi_instruction->incoming_count != SIZE_MAX);
10081008 for (size_t i = 0; i < phi_instruction->incoming_count; i += 1) {
1009 IrBasicBlockSrc *incoming_block = phi_instruction->incoming_blocks[i];
1009 Stage1ZirBasicBlock *incoming_block = phi_instruction->incoming_blocks[i];
10101010 IrInstSrc *incoming_value = phi_instruction->incoming_values[i];
10111011 if (i != 0)
10121012 fprintf(irp->f, " ");
......@@ -3350,7 +3350,7 @@ static void ir_print_inst_gen(IrPrintGen *irp, IrInstGen *instruction, bool trai
33503350 fprintf(irp->f, "\n");
33513351}
33523352
3353static void irp_print_basic_block_src(IrPrintSrc *irp, IrBasicBlockSrc *current_block) {
3353static void irp_print_basic_block_src(IrPrintSrc *irp, Stage1ZirBasicBlock *current_block) {
33543354 fprintf(irp->f, "%s_%" PRIu32 ":\n", current_block->name_hint, current_block->debug_id);
33553355 for (size_t instr_i = 0; instr_i < current_block->instruction_list.length; instr_i += 1) {
33563356 IrInstSrc *instruction = current_block->instruction_list.at(instr_i);
......@@ -3370,7 +3370,7 @@ static void irp_print_basic_block_gen(IrPrintGen *irp, IrBasicBlockGen *current_
33703370 }
33713371}
33723372
3373void ir_print_basic_block_src(CodeGen *codegen, FILE *f, IrBasicBlockSrc *bb, int indent_size) {
3373void ir_print_basic_block_src(CodeGen *codegen, FILE *f, Stage1ZirBasicBlock *bb, int indent_size) {
33743374 IrPrintSrc ir_print = {};
33753375 ir_print.codegen = codegen;
33763376 ir_print.f = f;
src/stage1/ir_print.hpp+1-1
......@@ -16,7 +16,7 @@ void ir_print_src(CodeGen *codegen, FILE *f, Stage1Zir *executable, int indent_s
1616void ir_print_gen(CodeGen *codegen, FILE *f, Stage1Air *executable, int indent_size);
1717void ir_print_inst_src(CodeGen *codegen, FILE *f, IrInstSrc *inst, int indent_size);
1818void ir_print_inst_gen(CodeGen *codegen, FILE *f, IrInstGen *inst, int indent_size);
19void ir_print_basic_block_src(CodeGen *codegen, FILE *f, IrBasicBlockSrc *bb, int indent_size);
19void ir_print_basic_block_src(CodeGen *codegen, FILE *f, Stage1ZirBasicBlock *bb, int indent_size);
2020void ir_print_basic_block_gen(CodeGen *codegen, FILE *f, IrBasicBlockGen *bb, int indent_size);
2121
2222const char* ir_inst_src_type_str(IrInstSrcId id);