authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-05-27 21:27:06-07:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-05-28 12:58:40-07:00
log01e0a4b2f06d60a58b3d2df410776b164d05c1ec
tree833ada28094dd93d4ad5c04039542134bf458c0d
parent548ef780707eb2b438015c28d594a59a3f37ba3e

stage1: rename IrBasicBlockSrc to Stage1ZirBasicBlock

5 files changed, 136 insertions(+), 136 deletions(-)

src/stage1/all_types.hpp+17-17
...@@ -38,7 +38,7 @@ struct IrInstGenCast;...@@ -38,7 +38,7 @@ struct IrInstGenCast;
38struct IrInstGenAlloca;38struct IrInstGenAlloca;
39struct IrInstGenCall;39struct IrInstGenCall;
40struct IrInstGenAwait;40struct IrInstGenAwait;
41struct IrBasicBlockSrc;41struct Stage1ZirBasicBlock;
42struct IrBasicBlockGen;42struct IrBasicBlockGen;
43struct ScopeDecls;43struct ScopeDecls;
44struct ZigWindowsSDK;44struct ZigWindowsSDK;
...@@ -111,7 +111,7 @@ enum X64CABIClass {...@@ -111,7 +111,7 @@ enum X64CABIClass {
111};111};
112112
113struct Stage1Zir {113struct Stage1Zir {
114 ZigList<IrBasicBlockSrc *> basic_block_list;114 ZigList<Stage1ZirBasicBlock *> basic_block_list;
115 Buf *name;115 Buf *name;
116 ZigFn *name_fn;116 ZigFn *name_fn;
117 Scope *begin_scope;117 Scope *begin_scope;
...@@ -2255,11 +2255,11 @@ struct ScopeBlock {...@@ -2255,11 +2255,11 @@ struct ScopeBlock {
2255 Scope base;2255 Scope base;
22562256
2257 Buf *name;2257 Buf *name;
2258 IrBasicBlockSrc *end_block;2258 Stage1ZirBasicBlock *end_block;
2259 IrInstSrc *is_comptime;2259 IrInstSrc *is_comptime;
2260 ResultLocPeerParent *peer_parent;2260 ResultLocPeerParent *peer_parent;
2261 ZigList<IrInstSrc *> *incoming_values;2261 ZigList<IrInstSrc *> *incoming_values;
2262 ZigList<IrBasicBlockSrc *> *incoming_blocks;2262 ZigList<Stage1ZirBasicBlock *> *incoming_blocks;
22632263
2264 AstNode *safety_set_node;2264 AstNode *safety_set_node;
2265 AstNode *fast_math_set_node;2265 AstNode *fast_math_set_node;
...@@ -2311,11 +2311,11 @@ struct ScopeLoop {...@@ -2311,11 +2311,11 @@ struct ScopeLoop {
23112311
2312 LVal lval;2312 LVal lval;
2313 Buf *name;2313 Buf *name;
2314 IrBasicBlockSrc *break_block;2314 Stage1ZirBasicBlock *break_block;
2315 IrBasicBlockSrc *continue_block;2315 Stage1ZirBasicBlock *continue_block;
2316 IrInstSrc *is_comptime;2316 IrInstSrc *is_comptime;
2317 ZigList<IrInstSrc *> *incoming_values;2317 ZigList<IrInstSrc *> *incoming_values;
2318 ZigList<IrBasicBlockSrc *> *incoming_blocks;2318 ZigList<Stage1ZirBasicBlock *> *incoming_blocks;
2319 ResultLocPeerParent *peer_parent;2319 ResultLocPeerParent *peer_parent;
2320 ScopeExpr *spill_scope;2320 ScopeExpr *spill_scope;
23212321
...@@ -2426,7 +2426,7 @@ enum AtomicRmwOp {...@@ -2426,7 +2426,7 @@ enum AtomicRmwOp {
2426// to another basic block.2426// to another basic block.
2427// Phi instructions must be first in a basic block.2427// Phi instructions must be first in a basic block.
2428// The last instruction in a basic block must be of type unreachable.2428// The last instruction in a basic block must be of type unreachable.
2429struct IrBasicBlockSrc {2429struct Stage1ZirBasicBlock {
2430 ZigList<IrInstSrc *> instruction_list;2430 ZigList<IrInstSrc *> instruction_list;
2431 IrBasicBlockGen *child;2431 IrBasicBlockGen *child;
2432 Scope *scope;2432 Scope *scope;
...@@ -2729,7 +2729,7 @@ struct IrInstSrc {...@@ -2729,7 +2729,7 @@ struct IrInstSrc {
2729 // can find the instruction that corresponds to this value in the "new ir"2729 // can find the instruction that corresponds to this value in the "new ir"
2730 // with this child field.2730 // with this child field.
2731 IrInstGen *child;2731 IrInstGen *child;
2732 IrBasicBlockSrc *owner_bb;2732 Stage1ZirBasicBlock *owner_bb;
27332733
2734 // for debugging purposes, these are useful to call to inspect the instruction2734 // for debugging purposes, these are useful to call to inspect the instruction
2735 void dump();2735 void dump();
...@@ -2774,8 +2774,8 @@ struct IrInstSrcCondBr {...@@ -2774,8 +2774,8 @@ struct IrInstSrcCondBr {
2774 IrInstSrc base;2774 IrInstSrc base;
27752775
2776 IrInstSrc *condition;2776 IrInstSrc *condition;
2777 IrBasicBlockSrc *then_block;2777 Stage1ZirBasicBlock *then_block;
2778 IrBasicBlockSrc *else_block;2778 Stage1ZirBasicBlock *else_block;
2779 IrInstSrc *is_comptime;2779 IrInstSrc *is_comptime;
2780 ResultLoc *result_loc;2780 ResultLoc *result_loc;
2781};2781};
...@@ -2791,7 +2791,7 @@ struct IrInstGenCondBr {...@@ -2791,7 +2791,7 @@ struct IrInstGenCondBr {
2791struct IrInstSrcBr {2791struct IrInstSrcBr {
2792 IrInstSrc base;2792 IrInstSrc base;
27932793
2794 IrBasicBlockSrc *dest_block;2794 Stage1ZirBasicBlock *dest_block;
2795 IrInstSrc *is_comptime;2795 IrInstSrc *is_comptime;
2796};2796};
27972797
...@@ -2803,14 +2803,14 @@ struct IrInstGenBr {...@@ -2803,14 +2803,14 @@ struct IrInstGenBr {
28032803
2804struct IrInstSrcSwitchBrCase {2804struct IrInstSrcSwitchBrCase {
2805 IrInstSrc *value;2805 IrInstSrc *value;
2806 IrBasicBlockSrc *block;2806 Stage1ZirBasicBlock *block;
2807};2807};
28082808
2809struct IrInstSrcSwitchBr {2809struct IrInstSrcSwitchBr {
2810 IrInstSrc base;2810 IrInstSrc base;
28112811
2812 IrInstSrc *target_value;2812 IrInstSrc *target_value;
2813 IrBasicBlockSrc *else_block;2813 Stage1ZirBasicBlock *else_block;
2814 size_t case_count;2814 size_t case_count;
2815 IrInstSrcSwitchBrCase *cases;2815 IrInstSrcSwitchBrCase *cases;
2816 IrInstSrc *is_comptime;2816 IrInstSrc *is_comptime;
...@@ -2856,7 +2856,7 @@ struct IrInstSrcPhi {...@@ -2856,7 +2856,7 @@ struct IrInstSrcPhi {
2856 IrInstSrc base;2856 IrInstSrc base;
28572857
2858 size_t incoming_count;2858 size_t incoming_count;
2859 IrBasicBlockSrc **incoming_blocks;2859 Stage1ZirBasicBlock **incoming_blocks;
2860 IrInstSrc **incoming_values;2860 IrInstSrc **incoming_values;
2861 ResultLocPeerParent *peer_parent;2861 ResultLocPeerParent *peer_parent;
2862};2862};
...@@ -4520,7 +4520,7 @@ struct ResultLocPeerParent {...@@ -4520,7 +4520,7 @@ struct ResultLocPeerParent {
45204520
4521 bool skipped;4521 bool skipped;
4522 bool done_resuming;4522 bool done_resuming;
4523 IrBasicBlockSrc *end_bb;4523 Stage1ZirBasicBlock *end_bb;
4524 ResultLoc *parent;4524 ResultLoc *parent;
4525 ZigList<ResultLocPeer *> peers;4525 ZigList<ResultLocPeer *> peers;
4526 ZigType *resolved_type;4526 ZigType *resolved_type;
...@@ -4531,7 +4531,7 @@ struct ResultLocPeer {...@@ -4531,7 +4531,7 @@ struct ResultLocPeer {
4531 ResultLoc base;4531 ResultLoc base;
45324532
4533 ResultLocPeerParent *parent;4533 ResultLocPeerParent *parent;
4534 IrBasicBlockSrc *next_bb;4534 Stage1ZirBasicBlock *next_bb;
4535 IrSuspendPosition suspend_pos;4535 IrSuspendPosition suspend_pos;
4536};4536};
45374537
src/stage1/astgen.cpp+96-96
...@@ -14,7 +14,7 @@...@@ -14,7 +14,7 @@
14struct Stage1AstGen {14struct Stage1AstGen {
15 CodeGen *codegen;15 CodeGen *codegen;
16 Stage1Zir *exec;16 Stage1Zir *exec;
17 IrBasicBlockSrc *current_basic_block;17 Stage1ZirBasicBlock *current_basic_block;
18 AstNode *main_block_node;18 AstNode *main_block_node;
19 size_t next_debug_id;19 size_t next_debug_id;
20 ZigFn *fn;20 ZigFn *fn;
...@@ -358,7 +358,7 @@ bool ir_should_inline(Stage1Zir *exec, Scope *scope) {...@@ -358,7 +358,7 @@ bool ir_should_inline(Stage1Zir *exec, Scope *scope) {
358 return false;358 return false;
359}359}
360360
361static void ir_instruction_append(IrBasicBlockSrc *basic_block, IrInstSrc *instruction) {361static void ir_instruction_append(Stage1ZirBasicBlock *basic_block, IrInstSrc *instruction) {
362 assert(basic_block);362 assert(basic_block);
363 assert(instruction);363 assert(instruction);
364 basic_block->instruction_list.append(instruction);364 basic_block->instruction_list.append(instruction);
...@@ -370,11 +370,11 @@ static size_t irb_next_debug_id(Stage1AstGen *ag) {...@@ -370,11 +370,11 @@ static size_t irb_next_debug_id(Stage1AstGen *ag) {
370 return result;370 return result;
371}371}
372372
373static void ir_ref_bb(IrBasicBlockSrc *bb) {373static void ir_ref_bb(Stage1ZirBasicBlock *bb) {
374 bb->ref_count += 1;374 bb->ref_count += 1;
375}375}
376376
377static void ir_ref_instruction(IrInstSrc *instruction, IrBasicBlockSrc *cur_bb) {377static void ir_ref_instruction(IrInstSrc *instruction, Stage1ZirBasicBlock *cur_bb) {
378 assert(instruction->id != IrInstSrcIdInvalid);378 assert(instruction->id != IrInstSrcIdInvalid);
379 instruction->base.ref_count += 1;379 instruction->base.ref_count += 1;
380 if (instruction->owner_bb != cur_bb && !instr_is_unreachable(instruction)380 if (instruction->owner_bb != cur_bb && !instr_is_unreachable(instruction)
...@@ -384,8 +384,8 @@ static void ir_ref_instruction(IrInstSrc *instruction, IrBasicBlockSrc *cur_bb)...@@ -384,8 +384,8 @@ static void ir_ref_instruction(IrInstSrc *instruction, IrBasicBlockSrc *cur_bb)
384 }384 }
385}385}
386386
387static IrBasicBlockSrc *ir_create_basic_block(Stage1AstGen *ag, Scope *scope, const char *name_hint) {387static Stage1ZirBasicBlock *ir_create_basic_block(Stage1AstGen *ag, Scope *scope, const char *name_hint) {
388 IrBasicBlockSrc *result = heap::c_allocator.create<IrBasicBlockSrc>();388 Stage1ZirBasicBlock *result = heap::c_allocator.create<Stage1ZirBasicBlock>();
389 result->scope = scope;389 result->scope = scope;
390 result->name_hint = name_hint;390 result->name_hint = name_hint;
391 result->debug_id = irb_next_debug_id(ag);391 result->debug_id = irb_next_debug_id(ag);
...@@ -944,7 +944,7 @@ static T *ir_build_instruction(Stage1AstGen *ag, Scope *scope, AstNode *source_n...@@ -944,7 +944,7 @@ static T *ir_build_instruction(Stage1AstGen *ag, Scope *scope, AstNode *source_n
944}944}
945945
946static IrInstSrc *ir_build_cond_br(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *condition,946static IrInstSrc *ir_build_cond_br(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *condition,
947 IrBasicBlockSrc *then_block, IrBasicBlockSrc *else_block, IrInstSrc *is_comptime)947 Stage1ZirBasicBlock *then_block, Stage1ZirBasicBlock *else_block, IrInstSrc *is_comptime)
948{948{
949 IrInstSrcCondBr *inst = ir_build_instruction<IrInstSrcCondBr>(ag, scope, source_node);949 IrInstSrcCondBr *inst = ir_build_instruction<IrInstSrcCondBr>(ag, scope, source_node);
950 inst->base.is_noreturn = true;950 inst->base.is_noreturn = true;
...@@ -1279,7 +1279,7 @@ static IrInstSrc *ir_build_call_src(Stage1AstGen *ag, Scope *scope, AstNode *sou...@@ -1279,7 +1279,7 @@ static IrInstSrc *ir_build_call_src(Stage1AstGen *ag, Scope *scope, AstNode *sou
1279}1279}
12801280
1281static IrInstSrc *ir_build_phi(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1281static IrInstSrc *ir_build_phi(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1282 size_t incoming_count, IrBasicBlockSrc **incoming_blocks, IrInstSrc **incoming_values,1282 size_t incoming_count, Stage1ZirBasicBlock **incoming_blocks, IrInstSrc **incoming_values,
1283 ResultLocPeerParent *peer_parent)1283 ResultLocPeerParent *peer_parent)
1284{1284{
1285 assert(incoming_count != 0);1285 assert(incoming_count != 0);
...@@ -1300,7 +1300,7 @@ static IrInstSrc *ir_build_phi(Stage1AstGen *ag, Scope *scope, AstNode *source_n...@@ -1300,7 +1300,7 @@ static IrInstSrc *ir_build_phi(Stage1AstGen *ag, Scope *scope, AstNode *source_n
1300}1300}
13011301
1302static IrInstSrc *ir_build_br(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1302static IrInstSrc *ir_build_br(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1303 IrBasicBlockSrc *dest_block, IrInstSrc *is_comptime)1303 Stage1ZirBasicBlock *dest_block, IrInstSrc *is_comptime)
1304{1304{
1305 IrInstSrcBr *inst = ir_build_instruction<IrInstSrcBr>(ag, scope, source_node);1305 IrInstSrcBr *inst = ir_build_instruction<IrInstSrcBr>(ag, scope, source_node);
1306 inst->base.is_noreturn = true;1306 inst->base.is_noreturn = true;
...@@ -1714,7 +1714,7 @@ static IrInstSrc *ir_build_bit_reverse(Stage1AstGen *ag, Scope *scope, AstNode *...@@ -1714,7 +1714,7 @@ static IrInstSrc *ir_build_bit_reverse(Stage1AstGen *ag, Scope *scope, AstNode *
1714}1714}
17151715
1716static IrInstSrcSwitchBr *ir_build_switch_br_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,1716static IrInstSrcSwitchBr *ir_build_switch_br_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
1717 IrInstSrc *target_value, IrBasicBlockSrc *else_block, size_t case_count, IrInstSrcSwitchBrCase *cases,1717 IrInstSrc *target_value, Stage1ZirBasicBlock *else_block, size_t case_count, IrInstSrcSwitchBrCase *cases,
1718 IrInstSrc *is_comptime, IrInstSrc *switch_prongs_void)1718 IrInstSrc *is_comptime, IrInstSrc *switch_prongs_void)
1719{1719{
1720 IrInstSrcSwitchBr *instruction = ir_build_instruction<IrInstSrcSwitchBr>(ag, scope, source_node);1720 IrInstSrcSwitchBr *instruction = ir_build_instruction<IrInstSrcSwitchBr>(ag, scope, source_node);
...@@ -2976,12 +2976,12 @@ static bool ir_gen_defers_for_block(Stage1AstGen *ag, Scope *inner_scope, Scope...@@ -2976,12 +2976,12 @@ static bool ir_gen_defers_for_block(Stage1AstGen *ag, Scope *inner_scope, Scope
2976 return true;2976 return true;
2977}2977}
29782978
2979static void ir_set_cursor_at_end(Stage1AstGen *ag, IrBasicBlockSrc *basic_block) {2979static void ir_set_cursor_at_end(Stage1AstGen *ag, Stage1ZirBasicBlock *basic_block) {
2980 assert(basic_block);2980 assert(basic_block);
2981 ag->current_basic_block = basic_block;2981 ag->current_basic_block = basic_block;
2982}2982}
29832983
2984static void ir_set_cursor_at_end_and_append_block(Stage1AstGen *ag, IrBasicBlockSrc *basic_block) {2984static void ir_set_cursor_at_end_and_append_block(Stage1AstGen *ag, Stage1ZirBasicBlock *basic_block) {
2985 basic_block->index = ag->exec->basic_block_list.length;2985 basic_block->index = ag->exec->basic_block_list.length;
2986 ag->exec->basic_block_list.append(basic_block);2986 ag->exec->basic_block_list.append(basic_block);
2987 ir_set_cursor_at_end(ag, basic_block);2987 ir_set_cursor_at_end(ag, basic_block);
...@@ -3062,8 +3062,8 @@ static IrInstSrc *ir_gen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L...@@ -3062,8 +3062,8 @@ static IrInstSrc *ir_gen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L
3062 }3062 }
3063 bool should_inline = ir_should_inline(ag->exec, scope);3063 bool should_inline = ir_should_inline(ag->exec, scope);
30643064
3065 IrBasicBlockSrc *err_block = ir_create_basic_block(ag, scope, "ErrRetErr");3065 Stage1ZirBasicBlock *err_block = ir_create_basic_block(ag, scope, "ErrRetErr");
3066 IrBasicBlockSrc *ok_block = ir_create_basic_block(ag, scope, "ErrRetOk");3066 Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, scope, "ErrRetOk");
30673067
3068 IrInstSrc *is_err = ir_build_test_err_src(ag, scope, node, return_value, false, true);3068 IrInstSrc *is_err = ir_build_test_err_src(ag, scope, node, return_value, false, true);
30693069
...@@ -3075,7 +3075,7 @@ static IrInstSrc *ir_gen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L...@@ -3075,7 +3075,7 @@ static IrInstSrc *ir_gen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L
3075 }3075 }
30763076
3077 ir_mark_gen(ir_build_cond_br(ag, scope, node, is_err, err_block, ok_block, is_comptime));3077 ir_mark_gen(ir_build_cond_br(ag, scope, node, is_err, err_block, ok_block, is_comptime));
3078 IrBasicBlockSrc *ret_stmt_block = ir_create_basic_block(ag, scope, "RetStmt");3078 Stage1ZirBasicBlock *ret_stmt_block = ir_create_basic_block(ag, scope, "RetStmt");
30793079
3080 ir_set_cursor_at_end_and_append_block(ag, err_block);3080 ir_set_cursor_at_end_and_append_block(ag, err_block);
3081 if (!ir_gen_defers_for_block(ag, scope, outer_scope, nullptr, return_value))3081 if (!ir_gen_defers_for_block(ag, scope, outer_scope, nullptr, return_value))
...@@ -3103,8 +3103,8 @@ static IrInstSrc *ir_gen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L...@@ -3103,8 +3103,8 @@ static IrInstSrc *ir_gen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L
3103 return ag->codegen->invalid_inst_src;3103 return ag->codegen->invalid_inst_src;
3104 IrInstSrc *is_err_val = ir_build_test_err_src(ag, scope, node, err_union_ptr, true, false);3104 IrInstSrc *is_err_val = ir_build_test_err_src(ag, scope, node, err_union_ptr, true, false);
31053105
3106 IrBasicBlockSrc *return_block = ir_create_basic_block(ag, scope, "ErrRetReturn");3106 Stage1ZirBasicBlock *return_block = ir_create_basic_block(ag, scope, "ErrRetReturn");
3107 IrBasicBlockSrc *continue_block = ir_create_basic_block(ag, scope, "ErrRetContinue");3107 Stage1ZirBasicBlock *continue_block = ir_create_basic_block(ag, scope, "ErrRetContinue");
3108 IrInstSrc *is_comptime;3108 IrInstSrc *is_comptime;
3109 bool should_inline = ir_should_inline(ag->exec, scope);3109 bool should_inline = ir_should_inline(ag->exec, scope);
3110 if (should_inline) {3110 if (should_inline) {
...@@ -3266,7 +3266,7 @@ static IrInstSrc *ir_gen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *b...@@ -3266,7 +3266,7 @@ static IrInstSrc *ir_gen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *b
3266 assert(block_node->type == NodeTypeBlock);3266 assert(block_node->type == NodeTypeBlock);
32673267
3268 ZigList<IrInstSrc *> incoming_values = {0};3268 ZigList<IrInstSrc *> incoming_values = {0};
3269 ZigList<IrBasicBlockSrc *> incoming_blocks = {0};3269 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
32703270
3271 if (is_duplicate_label(ag->codegen, parent_scope, block_node, block_node->data.block.name))3271 if (is_duplicate_label(ag->codegen, parent_scope, block_node, block_node->data.block.name))
3272 return ag->codegen->invalid_inst_src;3272 return ag->codegen->invalid_inst_src;
...@@ -3479,7 +3479,7 @@ static IrInstSrc *ir_gen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -3479,7 +3479,7 @@ static IrInstSrc *ir_gen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node)
3479 IrInstSrc *val1 = ir_gen_node(ag, node->data.bin_op_expr.op1, scope);3479 IrInstSrc *val1 = ir_gen_node(ag, node->data.bin_op_expr.op1, scope);
3480 if (val1 == ag->codegen->invalid_inst_src)3480 if (val1 == ag->codegen->invalid_inst_src)
3481 return ag->codegen->invalid_inst_src;3481 return ag->codegen->invalid_inst_src;
3482 IrBasicBlockSrc *post_val1_block = ag->current_basic_block;3482 Stage1ZirBasicBlock *post_val1_block = ag->current_basic_block;
34833483
3484 IrInstSrc *is_comptime;3484 IrInstSrc *is_comptime;
3485 if (ir_should_inline(ag->exec, scope)) {3485 if (ir_should_inline(ag->exec, scope)) {
...@@ -3489,9 +3489,9 @@ static IrInstSrc *ir_gen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -3489,9 +3489,9 @@ static IrInstSrc *ir_gen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node)
3489 }3489 }
34903490
3491 // block for when val1 == false3491 // block for when val1 == false
3492 IrBasicBlockSrc *false_block = ir_create_basic_block(ag, scope, "BoolOrFalse");3492 Stage1ZirBasicBlock *false_block = ir_create_basic_block(ag, scope, "BoolOrFalse");
3493 // block for when val1 == true (don't even evaluate the second part)3493 // block for when val1 == true (don't even evaluate the second part)
3494 IrBasicBlockSrc *true_block = ir_create_basic_block(ag, scope, "BoolOrTrue");3494 Stage1ZirBasicBlock *true_block = ir_create_basic_block(ag, scope, "BoolOrTrue");
34953495
3496 ir_build_cond_br(ag, scope, node, val1, true_block, false_block, is_comptime);3496 ir_build_cond_br(ag, scope, node, val1, true_block, false_block, is_comptime);
34973497
...@@ -3499,7 +3499,7 @@ static IrInstSrc *ir_gen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -3499,7 +3499,7 @@ static IrInstSrc *ir_gen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node)
3499 IrInstSrc *val2 = ir_gen_node(ag, node->data.bin_op_expr.op2, scope);3499 IrInstSrc *val2 = ir_gen_node(ag, node->data.bin_op_expr.op2, scope);
3500 if (val2 == ag->codegen->invalid_inst_src)3500 if (val2 == ag->codegen->invalid_inst_src)
3501 return ag->codegen->invalid_inst_src;3501 return ag->codegen->invalid_inst_src;
3502 IrBasicBlockSrc *post_val2_block = ag->current_basic_block;3502 Stage1ZirBasicBlock *post_val2_block = ag->current_basic_block;
35033503
3504 ir_build_br(ag, scope, node, true_block, is_comptime);3504 ir_build_br(ag, scope, node, true_block, is_comptime);
35053505
...@@ -3508,7 +3508,7 @@ static IrInstSrc *ir_gen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -3508,7 +3508,7 @@ static IrInstSrc *ir_gen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node)
3508 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);3508 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);
3509 incoming_values[0] = val1;3509 incoming_values[0] = val1;
3510 incoming_values[1] = val2;3510 incoming_values[1] = val2;
3511 IrBasicBlockSrc **incoming_blocks = heap::c_allocator.allocate<IrBasicBlockSrc *>(2);3511 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
3512 incoming_blocks[0] = post_val1_block;3512 incoming_blocks[0] = post_val1_block;
3513 incoming_blocks[1] = post_val2_block;3513 incoming_blocks[1] = post_val2_block;
35143514
...@@ -3521,7 +3521,7 @@ static IrInstSrc *ir_gen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -3521,7 +3521,7 @@ static IrInstSrc *ir_gen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)
3521 IrInstSrc *val1 = ir_gen_node(ag, node->data.bin_op_expr.op1, scope);3521 IrInstSrc *val1 = ir_gen_node(ag, node->data.bin_op_expr.op1, scope);
3522 if (val1 == ag->codegen->invalid_inst_src)3522 if (val1 == ag->codegen->invalid_inst_src)
3523 return ag->codegen->invalid_inst_src;3523 return ag->codegen->invalid_inst_src;
3524 IrBasicBlockSrc *post_val1_block = ag->current_basic_block;3524 Stage1ZirBasicBlock *post_val1_block = ag->current_basic_block;
35253525
3526 IrInstSrc *is_comptime;3526 IrInstSrc *is_comptime;
3527 if (ir_should_inline(ag->exec, scope)) {3527 if (ir_should_inline(ag->exec, scope)) {
...@@ -3531,9 +3531,9 @@ static IrInstSrc *ir_gen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -3531,9 +3531,9 @@ static IrInstSrc *ir_gen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)
3531 }3531 }
35323532
3533 // block for when val1 == true3533 // block for when val1 == true
3534 IrBasicBlockSrc *true_block = ir_create_basic_block(ag, scope, "BoolAndTrue");3534 Stage1ZirBasicBlock *true_block = ir_create_basic_block(ag, scope, "BoolAndTrue");
3535 // block for when val1 == false (don't even evaluate the second part)3535 // block for when val1 == false (don't even evaluate the second part)
3536 IrBasicBlockSrc *false_block = ir_create_basic_block(ag, scope, "BoolAndFalse");3536 Stage1ZirBasicBlock *false_block = ir_create_basic_block(ag, scope, "BoolAndFalse");
35373537
3538 ir_build_cond_br(ag, scope, node, val1, true_block, false_block, is_comptime);3538 ir_build_cond_br(ag, scope, node, val1, true_block, false_block, is_comptime);
35393539
...@@ -3541,7 +3541,7 @@ static IrInstSrc *ir_gen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -3541,7 +3541,7 @@ static IrInstSrc *ir_gen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)
3541 IrInstSrc *val2 = ir_gen_node(ag, node->data.bin_op_expr.op2, scope);3541 IrInstSrc *val2 = ir_gen_node(ag, node->data.bin_op_expr.op2, scope);
3542 if (val2 == ag->codegen->invalid_inst_src)3542 if (val2 == ag->codegen->invalid_inst_src)
3543 return ag->codegen->invalid_inst_src;3543 return ag->codegen->invalid_inst_src;
3544 IrBasicBlockSrc *post_val2_block = ag->current_basic_block;3544 Stage1ZirBasicBlock *post_val2_block = ag->current_basic_block;
35453545
3546 ir_build_br(ag, scope, node, false_block, is_comptime);3546 ir_build_br(ag, scope, node, false_block, is_comptime);
35473547
...@@ -3550,7 +3550,7 @@ static IrInstSrc *ir_gen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -3550,7 +3550,7 @@ static IrInstSrc *ir_gen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)
3550 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);3550 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);
3551 incoming_values[0] = val1;3551 incoming_values[0] = val1;
3552 incoming_values[1] = val2;3552 incoming_values[1] = val2;
3553 IrBasicBlockSrc **incoming_blocks = heap::c_allocator.allocate<IrBasicBlockSrc *>(2);3553 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
3554 incoming_blocks[0] = post_val1_block;3554 incoming_blocks[0] = post_val1_block;
3555 incoming_blocks[1] = post_val2_block;3555 incoming_blocks[1] = post_val2_block;
35563556
...@@ -3558,7 +3558,7 @@ static IrInstSrc *ir_gen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)...@@ -3558,7 +3558,7 @@ static IrInstSrc *ir_gen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node)
3558}3558}
35593559
3560static ResultLocPeerParent *ir_build_result_peers(Stage1AstGen *ag, IrInstSrc *cond_br_inst,3560static ResultLocPeerParent *ir_build_result_peers(Stage1AstGen *ag, IrInstSrc *cond_br_inst,
3561 IrBasicBlockSrc *end_block, ResultLoc *parent, IrInstSrc *is_comptime)3561 Stage1ZirBasicBlock *end_block, ResultLoc *parent, IrInstSrc *is_comptime)
3562{3562{
3563 ResultLocPeerParent *peer_parent = heap::c_allocator.create<ResultLocPeerParent>();3563 ResultLocPeerParent *peer_parent = heap::c_allocator.create<ResultLocPeerParent>();
3564 peer_parent->base.id = ResultLocIdPeerParent;3564 peer_parent->base.id = ResultLocIdPeerParent;
...@@ -3578,7 +3578,7 @@ static ResultLocPeerParent *ir_build_result_peers(Stage1AstGen *ag, IrInstSrc *c...@@ -3578,7 +3578,7 @@ static ResultLocPeerParent *ir_build_result_peers(Stage1AstGen *ag, IrInstSrc *c
3578}3578}
35793579
3580static ResultLocPeerParent *ir_build_binary_result_peers(Stage1AstGen *ag, IrInstSrc *cond_br_inst,3580static ResultLocPeerParent *ir_build_binary_result_peers(Stage1AstGen *ag, IrInstSrc *cond_br_inst,
3581 IrBasicBlockSrc *else_block, IrBasicBlockSrc *end_block, ResultLoc *parent, IrInstSrc *is_comptime)3581 Stage1ZirBasicBlock *else_block, Stage1ZirBasicBlock *end_block, ResultLoc *parent, IrInstSrc *is_comptime)
3582{3582{
3583 ResultLocPeerParent *peer_parent = ir_build_result_peers(ag, cond_br_inst, end_block, parent, is_comptime);3583 ResultLocPeerParent *peer_parent = ir_build_result_peers(ag, cond_br_inst, end_block, parent, is_comptime);
35843584
...@@ -3613,9 +3613,9 @@ static IrInstSrc *ir_gen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *...@@ -3613,9 +3613,9 @@ static IrInstSrc *ir_gen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *
3613 is_comptime = ir_build_test_comptime(ag, parent_scope, node, is_non_null);3613 is_comptime = ir_build_test_comptime(ag, parent_scope, node, is_non_null);
3614 }3614 }
36153615
3616 IrBasicBlockSrc *ok_block = ir_create_basic_block(ag, parent_scope, "OptionalNonNull");3616 Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, parent_scope, "OptionalNonNull");
3617 IrBasicBlockSrc *null_block = ir_create_basic_block(ag, parent_scope, "OptionalNull");3617 Stage1ZirBasicBlock *null_block = ir_create_basic_block(ag, parent_scope, "OptionalNull");
3618 IrBasicBlockSrc *end_block = ir_create_basic_block(ag, parent_scope, "OptionalEnd");3618 Stage1ZirBasicBlock *end_block = ir_create_basic_block(ag, parent_scope, "OptionalEnd");
3619 IrInstSrc *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, is_non_null, ok_block, null_block, is_comptime);3619 IrInstSrc *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, is_non_null, ok_block, null_block, is_comptime);
36203620
3621 ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, ok_block, end_block,3621 ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, ok_block, end_block,
...@@ -3626,7 +3626,7 @@ static IrInstSrc *ir_gen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *...@@ -3626,7 +3626,7 @@ static IrInstSrc *ir_gen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *
3626 &peer_parent->peers.at(0)->base);3626 &peer_parent->peers.at(0)->base);
3627 if (null_result == ag->codegen->invalid_inst_src)3627 if (null_result == ag->codegen->invalid_inst_src)
3628 return ag->codegen->invalid_inst_src;3628 return ag->codegen->invalid_inst_src;
3629 IrBasicBlockSrc *after_null_block = ag->current_basic_block;3629 Stage1ZirBasicBlock *after_null_block = ag->current_basic_block;
3630 if (!instr_is_unreachable(null_result))3630 if (!instr_is_unreachable(null_result))
3631 ir_mark_gen(ir_build_br(ag, parent_scope, node, end_block, is_comptime));3631 ir_mark_gen(ir_build_br(ag, parent_scope, node, end_block, is_comptime));
36323632
...@@ -3634,14 +3634,14 @@ static IrInstSrc *ir_gen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *...@@ -3634,14 +3634,14 @@ static IrInstSrc *ir_gen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *
3634 IrInstSrc *unwrapped_ptr = ir_build_optional_unwrap_ptr(ag, parent_scope, node, maybe_ptr, false);3634 IrInstSrc *unwrapped_ptr = ir_build_optional_unwrap_ptr(ag, parent_scope, node, maybe_ptr, false);
3635 IrInstSrc *unwrapped_payload = ir_build_load_ptr(ag, parent_scope, node, unwrapped_ptr);3635 IrInstSrc *unwrapped_payload = ir_build_load_ptr(ag, parent_scope, node, unwrapped_ptr);
3636 ir_build_end_expr(ag, parent_scope, node, unwrapped_payload, &peer_parent->peers.at(1)->base);3636 ir_build_end_expr(ag, parent_scope, node, unwrapped_payload, &peer_parent->peers.at(1)->base);
3637 IrBasicBlockSrc *after_ok_block = ag->current_basic_block;3637 Stage1ZirBasicBlock *after_ok_block = ag->current_basic_block;
3638 ir_build_br(ag, parent_scope, node, end_block, is_comptime);3638 ir_build_br(ag, parent_scope, node, end_block, is_comptime);
36393639
3640 ir_set_cursor_at_end_and_append_block(ag, end_block);3640 ir_set_cursor_at_end_and_append_block(ag, end_block);
3641 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);3641 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);
3642 incoming_values[0] = null_result;3642 incoming_values[0] = null_result;
3643 incoming_values[1] = unwrapped_payload;3643 incoming_values[1] = unwrapped_payload;
3644 IrBasicBlockSrc **incoming_blocks = heap::c_allocator.allocate<IrBasicBlockSrc *>(2);3644 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
3645 incoming_blocks[0] = after_null_block;3645 incoming_blocks[0] = after_null_block;
3646 incoming_blocks[1] = after_ok_block;3646 incoming_blocks[1] = after_ok_block;
3647 IrInstSrc *phi = ir_build_phi(ag, parent_scope, node, 2, incoming_blocks, incoming_values, peer_parent);3647 IrInstSrc *phi = ir_build_phi(ag, parent_scope, node, 2, incoming_blocks, incoming_values, peer_parent);
...@@ -5372,9 +5372,9 @@ static IrInstSrc *ir_gen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n...@@ -5372,9 +5372,9 @@ static IrInstSrc *ir_gen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n
5372 AstNode *then_node = node->data.if_bool_expr.then_block;5372 AstNode *then_node = node->data.if_bool_expr.then_block;
5373 AstNode *else_node = node->data.if_bool_expr.else_node;5373 AstNode *else_node = node->data.if_bool_expr.else_node;
53745374
5375 IrBasicBlockSrc *then_block = ir_create_basic_block(ag, scope, "Then");5375 Stage1ZirBasicBlock *then_block = ir_create_basic_block(ag, scope, "Then");
5376 IrBasicBlockSrc *else_block = ir_create_basic_block(ag, scope, "Else");5376 Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "Else");
5377 IrBasicBlockSrc *endif_block = ir_create_basic_block(ag, scope, "EndIf");5377 Stage1ZirBasicBlock *endif_block = ir_create_basic_block(ag, scope, "EndIf");
53785378
5379 IrInstSrc *cond_br_inst = ir_build_cond_br(ag, scope, node, condition,5379 IrInstSrc *cond_br_inst = ir_build_cond_br(ag, scope, node, condition,
5380 then_block, else_block, is_comptime);5380 then_block, else_block, is_comptime);
...@@ -5388,7 +5388,7 @@ static IrInstSrc *ir_gen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n...@@ -5388,7 +5388,7 @@ static IrInstSrc *ir_gen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n
5388 &peer_parent->peers.at(0)->base);5388 &peer_parent->peers.at(0)->base);
5389 if (then_expr_result == ag->codegen->invalid_inst_src)5389 if (then_expr_result == ag->codegen->invalid_inst_src)
5390 return ag->codegen->invalid_inst_src;5390 return ag->codegen->invalid_inst_src;
5391 IrBasicBlockSrc *after_then_block = ag->current_basic_block;5391 Stage1ZirBasicBlock *after_then_block = ag->current_basic_block;
5392 if (!instr_is_unreachable(then_expr_result))5392 if (!instr_is_unreachable(then_expr_result))
5393 ir_mark_gen(ir_build_br(ag, scope, node, endif_block, is_comptime));5393 ir_mark_gen(ir_build_br(ag, scope, node, endif_block, is_comptime));
53945394
...@@ -5402,7 +5402,7 @@ static IrInstSrc *ir_gen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n...@@ -5402,7 +5402,7 @@ static IrInstSrc *ir_gen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n
5402 else_expr_result = ir_build_const_void(ag, scope, node);5402 else_expr_result = ir_build_const_void(ag, scope, node);
5403 ir_build_end_expr(ag, scope, node, else_expr_result, &peer_parent->peers.at(1)->base);5403 ir_build_end_expr(ag, scope, node, else_expr_result, &peer_parent->peers.at(1)->base);
5404 }5404 }
5405 IrBasicBlockSrc *after_else_block = ag->current_basic_block;5405 Stage1ZirBasicBlock *after_else_block = ag->current_basic_block;
5406 if (!instr_is_unreachable(else_expr_result))5406 if (!instr_is_unreachable(else_expr_result))
5407 ir_mark_gen(ir_build_br(ag, scope, node, endif_block, is_comptime));5407 ir_mark_gen(ir_build_br(ag, scope, node, endif_block, is_comptime));
54085408
...@@ -5410,7 +5410,7 @@ static IrInstSrc *ir_gen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n...@@ -5410,7 +5410,7 @@ static IrInstSrc *ir_gen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n
5410 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);5410 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);
5411 incoming_values[0] = then_expr_result;5411 incoming_values[0] = then_expr_result;
5412 incoming_values[1] = else_expr_result;5412 incoming_values[1] = else_expr_result;
5413 IrBasicBlockSrc **incoming_blocks = heap::c_allocator.allocate<IrBasicBlockSrc *>(2);5413 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
5414 incoming_blocks[0] = after_then_block;5414 incoming_blocks[0] = after_then_block;
5415 incoming_blocks[1] = after_else_block;5415 incoming_blocks[1] = after_else_block;
54165416
...@@ -5912,12 +5912,12 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -5912,12 +5912,12 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
5912 AstNode *continue_expr_node = node->data.while_expr.continue_expr;5912 AstNode *continue_expr_node = node->data.while_expr.continue_expr;
5913 AstNode *else_node = node->data.while_expr.else_node;5913 AstNode *else_node = node->data.while_expr.else_node;
59145914
5915 IrBasicBlockSrc *cond_block = ir_create_basic_block(ag, scope, "WhileCond");5915 Stage1ZirBasicBlock *cond_block = ir_create_basic_block(ag, scope, "WhileCond");
5916 IrBasicBlockSrc *body_block = ir_create_basic_block(ag, scope, "WhileBody");5916 Stage1ZirBasicBlock *body_block = ir_create_basic_block(ag, scope, "WhileBody");
5917 IrBasicBlockSrc *continue_block = continue_expr_node ?5917 Stage1ZirBasicBlock *continue_block = continue_expr_node ?
5918 ir_create_basic_block(ag, scope, "WhileContinue") : cond_block;5918 ir_create_basic_block(ag, scope, "WhileContinue") : cond_block;
5919 IrBasicBlockSrc *end_block = ir_create_basic_block(ag, scope, "WhileEnd");5919 Stage1ZirBasicBlock *end_block = ir_create_basic_block(ag, scope, "WhileEnd");
5920 IrBasicBlockSrc *else_block = else_node ?5920 Stage1ZirBasicBlock *else_block = else_node ?
5921 ir_create_basic_block(ag, scope, "WhileElse") : end_block;5921 ir_create_basic_block(ag, scope, "WhileElse") : end_block;
59225922
5923 IrInstSrc *is_comptime = ir_build_const_bool(ag, scope, node,5923 IrInstSrc *is_comptime = ir_build_const_bool(ag, scope, node,
...@@ -5948,7 +5948,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -5948,7 +5948,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
5948 return err_val_ptr;5948 return err_val_ptr;
5949 IrInstSrc *is_err = ir_build_test_err_src(ag, scope, node->data.while_expr.condition, err_val_ptr,5949 IrInstSrc *is_err = ir_build_test_err_src(ag, scope, node->data.while_expr.condition, err_val_ptr,
5950 true, false);5950 true, false);
5951 IrBasicBlockSrc *after_cond_block = ag->current_basic_block;5951 Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block;
5952 IrInstSrc *void_else_result = else_node ? nullptr : ir_mark_gen(ir_build_const_void(ag, scope, node));5952 IrInstSrc *void_else_result = else_node ? nullptr : ir_mark_gen(ir_build_const_void(ag, scope, node));
5953 IrInstSrc *cond_br_inst;5953 IrInstSrc *cond_br_inst;
5954 if (!instr_is_unreachable(is_err)) {5954 if (!instr_is_unreachable(is_err)) {
...@@ -5973,7 +5973,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -5973,7 +5973,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
5973 }5973 }
59745974
5975 ZigList<IrInstSrc *> incoming_values = {0};5975 ZigList<IrInstSrc *> incoming_values = {0};
5976 ZigList<IrBasicBlockSrc *> incoming_blocks = {0};5976 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
59775977
5978 if (is_duplicate_label(ag->codegen, payload_scope, node, node->data.while_expr.name))5978 if (is_duplicate_label(ag->codegen, payload_scope, node, node->data.while_expr.name))
5979 return ag->codegen->invalid_inst_src;5979 return ag->codegen->invalid_inst_src;
...@@ -6037,7 +6037,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6037,7 +6037,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
6037 return else_result;6037 return else_result;
6038 if (!instr_is_unreachable(else_result))6038 if (!instr_is_unreachable(else_result))
6039 ir_mark_gen(ir_build_br(ag, scope, node, end_block, is_comptime));6039 ir_mark_gen(ir_build_br(ag, scope, node, end_block, is_comptime));
6040 IrBasicBlockSrc *after_else_block = ag->current_basic_block;6040 Stage1ZirBasicBlock *after_else_block = ag->current_basic_block;
6041 ir_set_cursor_at_end_and_append_block(ag, end_block);6041 ir_set_cursor_at_end_and_append_block(ag, end_block);
6042 if (else_result) {6042 if (else_result) {
6043 incoming_blocks.append(after_else_block);6043 incoming_blocks.append(after_else_block);
...@@ -6069,7 +6069,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6069,7 +6069,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
6069 return maybe_val_ptr;6069 return maybe_val_ptr;
6070 IrInstSrc *maybe_val = ir_build_load_ptr(ag, scope, node->data.while_expr.condition, maybe_val_ptr);6070 IrInstSrc *maybe_val = ir_build_load_ptr(ag, scope, node->data.while_expr.condition, maybe_val_ptr);
6071 IrInstSrc *is_non_null = ir_build_test_non_null_src(ag, scope, node->data.while_expr.condition, maybe_val);6071 IrInstSrc *is_non_null = ir_build_test_non_null_src(ag, scope, node->data.while_expr.condition, maybe_val);
6072 IrBasicBlockSrc *after_cond_block = ag->current_basic_block;6072 Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block;
6073 IrInstSrc *void_else_result = else_node ? nullptr : ir_mark_gen(ir_build_const_void(ag, scope, node));6073 IrInstSrc *void_else_result = else_node ? nullptr : ir_mark_gen(ir_build_const_void(ag, scope, node));
6074 IrInstSrc *cond_br_inst;6074 IrInstSrc *cond_br_inst;
6075 if (!instr_is_unreachable(is_non_null)) {6075 if (!instr_is_unreachable(is_non_null)) {
...@@ -6091,7 +6091,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6091,7 +6091,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
6091 build_decl_var_and_init(ag, child_scope, symbol_node, payload_var, var_value, buf_ptr(var_symbol), is_comptime);6091 build_decl_var_and_init(ag, child_scope, symbol_node, payload_var, var_value, buf_ptr(var_symbol), is_comptime);
60926092
6093 ZigList<IrInstSrc *> incoming_values = {0};6093 ZigList<IrInstSrc *> incoming_values = {0};
6094 ZigList<IrBasicBlockSrc *> incoming_blocks = {0};6094 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
60956095
6096 if (is_duplicate_label(ag->codegen, child_scope, node, node->data.while_expr.name))6096 if (is_duplicate_label(ag->codegen, child_scope, node, node->data.while_expr.name))
6097 return ag->codegen->invalid_inst_src;6097 return ag->codegen->invalid_inst_src;
...@@ -6148,7 +6148,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6148,7 +6148,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
6148 if (!instr_is_unreachable(else_result))6148 if (!instr_is_unreachable(else_result))
6149 ir_mark_gen(ir_build_br(ag, scope, node, end_block, is_comptime));6149 ir_mark_gen(ir_build_br(ag, scope, node, end_block, is_comptime));
6150 }6150 }
6151 IrBasicBlockSrc *after_else_block = ag->current_basic_block;6151 Stage1ZirBasicBlock *after_else_block = ag->current_basic_block;
6152 ir_set_cursor_at_end_and_append_block(ag, end_block);6152 ir_set_cursor_at_end_and_append_block(ag, end_block);
6153 if (else_result) {6153 if (else_result) {
6154 incoming_blocks.append(after_else_block);6154 incoming_blocks.append(after_else_block);
...@@ -6169,7 +6169,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6169,7 +6169,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
6169 IrInstSrc *cond_val = ir_gen_node(ag, node->data.while_expr.condition, scope);6169 IrInstSrc *cond_val = ir_gen_node(ag, node->data.while_expr.condition, scope);
6170 if (cond_val == ag->codegen->invalid_inst_src)6170 if (cond_val == ag->codegen->invalid_inst_src)
6171 return cond_val;6171 return cond_val;
6172 IrBasicBlockSrc *after_cond_block = ag->current_basic_block;6172 Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block;
6173 IrInstSrc *void_else_result = else_node ? nullptr : ir_mark_gen(ir_build_const_void(ag, scope, node));6173 IrInstSrc *void_else_result = else_node ? nullptr : ir_mark_gen(ir_build_const_void(ag, scope, node));
6174 IrInstSrc *cond_br_inst;6174 IrInstSrc *cond_br_inst;
6175 if (!instr_is_unreachable(cond_val)) {6175 if (!instr_is_unreachable(cond_val)) {
...@@ -6186,7 +6186,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6186,7 +6186,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
6186 ir_set_cursor_at_end_and_append_block(ag, body_block);6186 ir_set_cursor_at_end_and_append_block(ag, body_block);
61876187
6188 ZigList<IrInstSrc *> incoming_values = {0};6188 ZigList<IrInstSrc *> incoming_values = {0};
6189 ZigList<IrBasicBlockSrc *> incoming_blocks = {0};6189 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
61906190
6191 Scope *subexpr_scope = create_runtime_scope(ag->codegen, node, scope, is_comptime);6191 Scope *subexpr_scope = create_runtime_scope(ag->codegen, node, scope, is_comptime);
61926192
...@@ -6245,7 +6245,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod...@@ -6245,7 +6245,7 @@ static IrInstSrc *ir_gen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod
6245 if (!instr_is_unreachable(else_result))6245 if (!instr_is_unreachable(else_result))
6246 ir_mark_gen(ir_build_br(ag, scope, node, end_block, is_comptime));6246 ir_mark_gen(ir_build_br(ag, scope, node, end_block, is_comptime));
6247 }6247 }
6248 IrBasicBlockSrc *after_else_block = ag->current_basic_block;6248 Stage1ZirBasicBlock *after_else_block = ag->current_basic_block;
6249 ir_set_cursor_at_end_and_append_block(ag, end_block);6249 ir_set_cursor_at_end_and_append_block(ag, end_block);
6250 if (else_result) {6250 if (else_result) {
6251 incoming_blocks.append(after_else_block);6251 incoming_blocks.append(after_else_block);
...@@ -6312,11 +6312,11 @@ static IrInstSrc *ir_gen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode...@@ -6312,11 +6312,11 @@ static IrInstSrc *ir_gen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode
6312 IrInstSrc *index_ptr = ir_build_var_ptr(ag, parent_scope, node, index_var);6312 IrInstSrc *index_ptr = ir_build_var_ptr(ag, parent_scope, node, index_var);
63136313
63146314
6315 IrBasicBlockSrc *cond_block = ir_create_basic_block(ag, parent_scope, "ForCond");6315 Stage1ZirBasicBlock *cond_block = ir_create_basic_block(ag, parent_scope, "ForCond");
6316 IrBasicBlockSrc *body_block = ir_create_basic_block(ag, parent_scope, "ForBody");6316 Stage1ZirBasicBlock *body_block = ir_create_basic_block(ag, parent_scope, "ForBody");
6317 IrBasicBlockSrc *end_block = ir_create_basic_block(ag, parent_scope, "ForEnd");6317 Stage1ZirBasicBlock *end_block = ir_create_basic_block(ag, parent_scope, "ForEnd");
6318 IrBasicBlockSrc *else_block = else_node ? ir_create_basic_block(ag, parent_scope, "ForElse") : end_block;6318 Stage1ZirBasicBlock *else_block = else_node ? ir_create_basic_block(ag, parent_scope, "ForElse") : end_block;
6319 IrBasicBlockSrc *continue_block = ir_create_basic_block(ag, parent_scope, "ForContinue");6319 Stage1ZirBasicBlock *continue_block = ir_create_basic_block(ag, parent_scope, "ForContinue");
63206320
6321 Buf *len_field_name = buf_create_from_str("len");6321 Buf *len_field_name = buf_create_from_str("len");
6322 IrInstSrc *len_ref = ir_build_field_ptr(ag, parent_scope, node, array_val_ptr, len_field_name, false);6322 IrInstSrc *len_ref = ir_build_field_ptr(ag, parent_scope, node, array_val_ptr, len_field_name, false);
...@@ -6326,7 +6326,7 @@ static IrInstSrc *ir_gen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode...@@ -6326,7 +6326,7 @@ static IrInstSrc *ir_gen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode
6326 ir_set_cursor_at_end_and_append_block(ag, cond_block);6326 ir_set_cursor_at_end_and_append_block(ag, cond_block);
6327 IrInstSrc *index_val = ir_build_load_ptr(ag, &spill_scope->base, node, index_ptr);6327 IrInstSrc *index_val = ir_build_load_ptr(ag, &spill_scope->base, node, index_ptr);
6328 IrInstSrc *cond = ir_build_bin_op(ag, parent_scope, node, IrBinOpCmpLessThan, index_val, len_val, false);6328 IrInstSrc *cond = ir_build_bin_op(ag, parent_scope, node, IrBinOpCmpLessThan, index_val, len_val, false);
6329 IrBasicBlockSrc *after_cond_block = ag->current_basic_block;6329 Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block;
6330 IrInstSrc *void_else_value = else_node ? nullptr : ir_mark_gen(ir_build_const_void(ag, parent_scope, node));6330 IrInstSrc *void_else_value = else_node ? nullptr : ir_mark_gen(ir_build_const_void(ag, parent_scope, node));
6331 IrInstSrc *cond_br_inst = ir_mark_gen(ir_build_cond_br(ag, parent_scope, node, cond,6331 IrInstSrc *cond_br_inst = ir_mark_gen(ir_build_cond_br(ag, parent_scope, node, cond,
6332 body_block, else_block, is_comptime));6332 body_block, else_block, is_comptime));
...@@ -6349,7 +6349,7 @@ static IrInstSrc *ir_gen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode...@@ -6349,7 +6349,7 @@ static IrInstSrc *ir_gen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode
6349 return ag->codegen->invalid_inst_src;6349 return ag->codegen->invalid_inst_src;
63506350
6351 ZigList<IrInstSrc *> incoming_values = {0};6351 ZigList<IrInstSrc *> incoming_values = {0};
6352 ZigList<IrBasicBlockSrc *> incoming_blocks = {0};6352 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
6353 ScopeLoop *loop_scope = create_loop_scope(ag->codegen, node, child_scope);6353 ScopeLoop *loop_scope = create_loop_scope(ag->codegen, node, child_scope);
6354 loop_scope->break_block = end_block;6354 loop_scope->break_block = end_block;
6355 loop_scope->continue_block = continue_block;6355 loop_scope->continue_block = continue_block;
...@@ -6396,7 +6396,7 @@ static IrInstSrc *ir_gen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode...@@ -6396,7 +6396,7 @@ static IrInstSrc *ir_gen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode
6396 if (!instr_is_unreachable(else_result))6396 if (!instr_is_unreachable(else_result))
6397 ir_mark_gen(ir_build_br(ag, parent_scope, node, end_block, is_comptime));6397 ir_mark_gen(ir_build_br(ag, parent_scope, node, end_block, is_comptime));
6398 }6398 }
6399 IrBasicBlockSrc *after_else_block = ag->current_basic_block;6399 Stage1ZirBasicBlock *after_else_block = ag->current_basic_block;
6400 ir_set_cursor_at_end_and_append_block(ag, end_block);6400 ir_set_cursor_at_end_and_append_block(ag, end_block);
64016401
6402 if (else_result) {6402 if (else_result) {
...@@ -6667,9 +6667,9 @@ static IrInstSrc *ir_gen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod...@@ -6667,9 +6667,9 @@ static IrInstSrc *ir_gen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod
6667 IrInstSrc *maybe_val = ir_build_load_ptr(ag, scope, node, maybe_val_ptr);6667 IrInstSrc *maybe_val = ir_build_load_ptr(ag, scope, node, maybe_val_ptr);
6668 IrInstSrc *is_non_null = ir_build_test_non_null_src(ag, scope, node, maybe_val);6668 IrInstSrc *is_non_null = ir_build_test_non_null_src(ag, scope, node, maybe_val);
66696669
6670 IrBasicBlockSrc *then_block = ir_create_basic_block(ag, scope, "OptionalThen");6670 Stage1ZirBasicBlock *then_block = ir_create_basic_block(ag, scope, "OptionalThen");
6671 IrBasicBlockSrc *else_block = ir_create_basic_block(ag, scope, "OptionalElse");6671 Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "OptionalElse");
6672 IrBasicBlockSrc *endif_block = ir_create_basic_block(ag, scope, "OptionalEndIf");6672 Stage1ZirBasicBlock *endif_block = ir_create_basic_block(ag, scope, "OptionalEndIf");
66736673
6674 IrInstSrc *is_comptime;6674 IrInstSrc *is_comptime;
6675 if (ir_should_inline(ag->exec, scope)) {6675 if (ir_should_inline(ag->exec, scope)) {
...@@ -6705,7 +6705,7 @@ static IrInstSrc *ir_gen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod...@@ -6705,7 +6705,7 @@ static IrInstSrc *ir_gen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod
6705 &peer_parent->peers.at(0)->base);6705 &peer_parent->peers.at(0)->base);
6706 if (then_expr_result == ag->codegen->invalid_inst_src)6706 if (then_expr_result == ag->codegen->invalid_inst_src)
6707 return then_expr_result;6707 return then_expr_result;
6708 IrBasicBlockSrc *after_then_block = ag->current_basic_block;6708 Stage1ZirBasicBlock *after_then_block = ag->current_basic_block;
6709 if (!instr_is_unreachable(then_expr_result))6709 if (!instr_is_unreachable(then_expr_result))
6710 ir_mark_gen(ir_build_br(ag, scope, node, endif_block, is_comptime));6710 ir_mark_gen(ir_build_br(ag, scope, node, endif_block, is_comptime));
67116711
...@@ -6719,7 +6719,7 @@ static IrInstSrc *ir_gen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod...@@ -6719,7 +6719,7 @@ static IrInstSrc *ir_gen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod
6719 else_expr_result = ir_build_const_void(ag, scope, node);6719 else_expr_result = ir_build_const_void(ag, scope, node);
6720 ir_build_end_expr(ag, scope, node, else_expr_result, &peer_parent->peers.at(1)->base);6720 ir_build_end_expr(ag, scope, node, else_expr_result, &peer_parent->peers.at(1)->base);
6721 }6721 }
6722 IrBasicBlockSrc *after_else_block = ag->current_basic_block;6722 Stage1ZirBasicBlock *after_else_block = ag->current_basic_block;
6723 if (!instr_is_unreachable(else_expr_result))6723 if (!instr_is_unreachable(else_expr_result))
6724 ir_mark_gen(ir_build_br(ag, scope, node, endif_block, is_comptime));6724 ir_mark_gen(ir_build_br(ag, scope, node, endif_block, is_comptime));
67256725
...@@ -6727,7 +6727,7 @@ static IrInstSrc *ir_gen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod...@@ -6727,7 +6727,7 @@ static IrInstSrc *ir_gen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod
6727 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);6727 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);
6728 incoming_values[0] = then_expr_result;6728 incoming_values[0] = then_expr_result;
6729 incoming_values[1] = else_expr_result;6729 incoming_values[1] = else_expr_result;
6730 IrBasicBlockSrc **incoming_blocks = heap::c_allocator.allocate<IrBasicBlockSrc *>(2);6730 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
6731 incoming_blocks[0] = after_then_block;6731 incoming_blocks[0] = after_then_block;
6732 incoming_blocks[1] = after_else_block;6732 incoming_blocks[1] = after_else_block;
67336733
...@@ -6755,9 +6755,9 @@ static IrInstSrc *ir_gen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -6755,9 +6755,9 @@ static IrInstSrc *ir_gen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
6755 IrInstSrc *err_val = ir_build_load_ptr(ag, scope, node, err_val_ptr);6755 IrInstSrc *err_val = ir_build_load_ptr(ag, scope, node, err_val_ptr);
6756 IrInstSrc *is_err = ir_build_test_err_src(ag, scope, node, err_val_ptr, true, false);6756 IrInstSrc *is_err = ir_build_test_err_src(ag, scope, node, err_val_ptr, true, false);
67576757
6758 IrBasicBlockSrc *ok_block = ir_create_basic_block(ag, scope, "TryOk");6758 Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, scope, "TryOk");
6759 IrBasicBlockSrc *else_block = ir_create_basic_block(ag, scope, "TryElse");6759 Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "TryElse");
6760 IrBasicBlockSrc *endif_block = ir_create_basic_block(ag, scope, "TryEnd");6760 Stage1ZirBasicBlock *endif_block = ir_create_basic_block(ag, scope, "TryEnd");
67616761
6762 bool force_comptime = ir_should_inline(ag->exec, scope);6762 bool force_comptime = ir_should_inline(ag->exec, scope);
6763 IrInstSrc *is_comptime = force_comptime ? ir_build_const_bool(ag, scope, node, true) : ir_build_test_comptime(ag, scope, node, is_err);6763 IrInstSrc *is_comptime = force_comptime ? ir_build_const_bool(ag, scope, node, true) : ir_build_test_comptime(ag, scope, node, is_err);
...@@ -6788,7 +6788,7 @@ static IrInstSrc *ir_gen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -6788,7 +6788,7 @@ static IrInstSrc *ir_gen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
6788 &peer_parent->peers.at(0)->base);6788 &peer_parent->peers.at(0)->base);
6789 if (then_expr_result == ag->codegen->invalid_inst_src)6789 if (then_expr_result == ag->codegen->invalid_inst_src)
6790 return then_expr_result;6790 return then_expr_result;
6791 IrBasicBlockSrc *after_then_block = ag->current_basic_block;6791 Stage1ZirBasicBlock *after_then_block = ag->current_basic_block;
6792 if (!instr_is_unreachable(then_expr_result))6792 if (!instr_is_unreachable(then_expr_result))
6793 ir_mark_gen(ir_build_br(ag, scope, node, endif_block, is_comptime));6793 ir_mark_gen(ir_build_br(ag, scope, node, endif_block, is_comptime));
67946794
...@@ -6817,7 +6817,7 @@ static IrInstSrc *ir_gen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -6817,7 +6817,7 @@ static IrInstSrc *ir_gen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
6817 else_expr_result = ir_build_const_void(ag, scope, node);6817 else_expr_result = ir_build_const_void(ag, scope, node);
6818 ir_build_end_expr(ag, scope, node, else_expr_result, &peer_parent->peers.at(1)->base);6818 ir_build_end_expr(ag, scope, node, else_expr_result, &peer_parent->peers.at(1)->base);
6819 }6819 }
6820 IrBasicBlockSrc *after_else_block = ag->current_basic_block;6820 Stage1ZirBasicBlock *after_else_block = ag->current_basic_block;
6821 if (!instr_is_unreachable(else_expr_result))6821 if (!instr_is_unreachable(else_expr_result))
6822 ir_mark_gen(ir_build_br(ag, scope, node, endif_block, is_comptime));6822 ir_mark_gen(ir_build_br(ag, scope, node, endif_block, is_comptime));
68236823
...@@ -6825,7 +6825,7 @@ static IrInstSrc *ir_gen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -6825,7 +6825,7 @@ static IrInstSrc *ir_gen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
6825 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);6825 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);
6826 incoming_values[0] = then_expr_result;6826 incoming_values[0] = then_expr_result;
6827 incoming_values[1] = else_expr_result;6827 incoming_values[1] = else_expr_result;
6828 IrBasicBlockSrc **incoming_blocks = heap::c_allocator.allocate<IrBasicBlockSrc *>(2);6828 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
6829 incoming_blocks[0] = after_then_block;6829 incoming_blocks[0] = after_then_block;
6830 incoming_blocks[1] = after_else_block;6830 incoming_blocks[1] = after_else_block;
68316831
...@@ -6834,9 +6834,9 @@ static IrInstSrc *ir_gen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -6834,9 +6834,9 @@ static IrInstSrc *ir_gen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
6834}6834}
68356835
6836static bool ir_gen_switch_prong_expr(Stage1AstGen *ag, Scope *scope, AstNode *switch_node, AstNode *prong_node,6836static bool ir_gen_switch_prong_expr(Stage1AstGen *ag, Scope *scope, AstNode *switch_node, AstNode *prong_node,
6837 IrBasicBlockSrc *end_block, IrInstSrc *is_comptime, IrInstSrc *var_is_comptime,6837 Stage1ZirBasicBlock *end_block, IrInstSrc *is_comptime, IrInstSrc *var_is_comptime,
6838 IrInstSrc *target_value_ptr, IrInstSrc **prong_values, size_t prong_values_len,6838 IrInstSrc *target_value_ptr, IrInstSrc **prong_values, size_t prong_values_len,
6839 ZigList<IrBasicBlockSrc *> *incoming_blocks, ZigList<IrInstSrc *> *incoming_values,6839 ZigList<Stage1ZirBasicBlock *> *incoming_blocks, ZigList<IrInstSrc *> *incoming_values,
6840 IrInstSrcSwitchElseVar **out_switch_else_var, LVal lval, ResultLoc *result_loc)6840 IrInstSrcSwitchElseVar **out_switch_else_var, LVal lval, ResultLoc *result_loc)
6841{6841{
6842 assert(switch_node->type == NodeTypeSwitchExpr);6842 assert(switch_node->type == NodeTypeSwitchExpr);
...@@ -6898,8 +6898,8 @@ static IrInstSrc *ir_gen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -6898,8 +6898,8 @@ static IrInstSrc *ir_gen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
6898 return target_value_ptr;6898 return target_value_ptr;
6899 IrInstSrc *target_value = ir_build_switch_target(ag, scope, node, target_value_ptr);6899 IrInstSrc *target_value = ir_build_switch_target(ag, scope, node, target_value_ptr);
69006900
6901 IrBasicBlockSrc *else_block = ir_create_basic_block(ag, scope, "SwitchElse");6901 Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "SwitchElse");
6902 IrBasicBlockSrc *end_block = ir_create_basic_block(ag, scope, "SwitchEnd");6902 Stage1ZirBasicBlock *end_block = ir_create_basic_block(ag, scope, "SwitchEnd");
69036903
6904 size_t prong_count = node->data.switch_expr.prongs.length;6904 size_t prong_count = node->data.switch_expr.prongs.length;
6905 ZigList<IrInstSrcSwitchBrCase> cases = {0};6905 ZigList<IrInstSrcSwitchBrCase> cases = {0};
...@@ -6915,7 +6915,7 @@ static IrInstSrc *ir_gen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -6915,7 +6915,7 @@ static IrInstSrc *ir_gen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
6915 }6915 }
69166916
6917 ZigList<IrInstSrc *> incoming_values = {0};6917 ZigList<IrInstSrc *> incoming_values = {0};
6918 ZigList<IrBasicBlockSrc *> incoming_blocks = {0};6918 ZigList<Stage1ZirBasicBlock *> incoming_blocks = {0};
6919 ZigList<IrInstSrcCheckSwitchProngsRange> check_ranges = {0};6919 ZigList<IrInstSrcCheckSwitchProngsRange> check_ranges = {0};
69206920
6921 IrInstSrcSwitchElseVar *switch_else_var = nullptr;6921 IrInstSrcSwitchElseVar *switch_else_var = nullptr;
...@@ -6991,8 +6991,8 @@ static IrInstSrc *ir_gen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -6991,8 +6991,8 @@ static IrInstSrc *ir_gen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
6991 }6991 }
6992 }6992 }
69936993
6994 IrBasicBlockSrc *range_block_yes = ir_create_basic_block(ag, scope, "SwitchRangeYes");6994 Stage1ZirBasicBlock *range_block_yes = ir_create_basic_block(ag, scope, "SwitchRangeYes");
6995 IrBasicBlockSrc *range_block_no = ir_create_basic_block(ag, scope, "SwitchRangeNo");6995 Stage1ZirBasicBlock *range_block_no = ir_create_basic_block(ag, scope, "SwitchRangeNo");
69966996
6997 assert(ok_bit);6997 assert(ok_bit);
6998 assert(last_item_node);6998 assert(last_item_node);
...@@ -7052,7 +7052,7 @@ static IrInstSrc *ir_gen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -7052,7 +7052,7 @@ static IrInstSrc *ir_gen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
7052 }7052 }
7053 ResultLocPeer *this_peer_result_loc = create_peer_result(peer_parent);7053 ResultLocPeer *this_peer_result_loc = create_peer_result(peer_parent);
70547054
7055 IrBasicBlockSrc *prev_block = ag->current_basic_block;7055 Stage1ZirBasicBlock *prev_block = ag->current_basic_block;
7056 if (peer_parent->peers.length > 0) {7056 if (peer_parent->peers.length > 0) {
7057 peer_parent->peers.last()->next_bb = else_block;7057 peer_parent->peers.last()->next_bb = else_block;
7058 }7058 }
...@@ -7081,7 +7081,7 @@ static IrInstSrc *ir_gen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -7081,7 +7081,7 @@ static IrInstSrc *ir_gen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
70817081
7082 ResultLocPeer *this_peer_result_loc = create_peer_result(peer_parent);7082 ResultLocPeer *this_peer_result_loc = create_peer_result(peer_parent);
70837083
7084 IrBasicBlockSrc *prong_block = ir_create_basic_block(ag, scope, "SwitchProng");7084 Stage1ZirBasicBlock *prong_block = ir_create_basic_block(ag, scope, "SwitchProng");
7085 IrInstSrc **items = heap::c_allocator.allocate<IrInstSrc *>(prong_item_count);7085 IrInstSrc **items = heap::c_allocator.allocate<IrInstSrc *>(prong_item_count);
70867086
7087 for (size_t item_i = 0; item_i < prong_item_count; item_i += 1) {7087 for (size_t item_i = 0; item_i < prong_item_count; item_i += 1) {
...@@ -7103,7 +7103,7 @@ static IrInstSrc *ir_gen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no...@@ -7103,7 +7103,7 @@ static IrInstSrc *ir_gen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no
7103 items[item_i] = item_value;7103 items[item_i] = item_value;
7104 }7104 }
71057105
7106 IrBasicBlockSrc *prev_block = ag->current_basic_block;7106 Stage1ZirBasicBlock *prev_block = ag->current_basic_block;
7107 if (peer_parent->peers.length > 0) {7107 if (peer_parent->peers.length > 0) {
7108 peer_parent->peers.last()->next_bb = prong_block;7108 peer_parent->peers.last()->next_bb = prong_block;
7109 }7109 }
...@@ -7202,7 +7202,7 @@ static IrInstSrc *ir_gen_return_from_block(Stage1AstGen *ag, Scope *break_scope,...@@ -7202,7 +7202,7 @@ static IrInstSrc *ir_gen_return_from_block(Stage1AstGen *ag, Scope *break_scope,
7202 result_value = ir_build_const_void(ag, break_scope, node);7202 result_value = ir_build_const_void(ag, break_scope, node);
7203 }7203 }
72047204
7205 IrBasicBlockSrc *dest_block = block_scope->end_block;7205 Stage1ZirBasicBlock *dest_block = block_scope->end_block;
7206 if (!ir_gen_defers_for_block(ag, break_scope, dest_block->scope, nullptr, nullptr))7206 if (!ir_gen_defers_for_block(ag, break_scope, dest_block->scope, nullptr, nullptr))
7207 return ag->codegen->invalid_inst_src;7207 return ag->codegen->invalid_inst_src;
72087208
...@@ -7279,7 +7279,7 @@ static IrInstSrc *ir_gen_break(Stage1AstGen *ag, Scope *break_scope, AstNode *no...@@ -7279,7 +7279,7 @@ static IrInstSrc *ir_gen_break(Stage1AstGen *ag, Scope *break_scope, AstNode *no
7279 result_value = ir_build_const_void(ag, break_scope, node);7279 result_value = ir_build_const_void(ag, break_scope, node);
7280 }7280 }
72817281
7282 IrBasicBlockSrc *dest_block = loop_scope->break_block;7282 Stage1ZirBasicBlock *dest_block = loop_scope->break_block;
7283 if (!ir_gen_defers_for_block(ag, break_scope, dest_block->scope, nullptr, nullptr))7283 if (!ir_gen_defers_for_block(ag, break_scope, dest_block->scope, nullptr, nullptr))
7284 return ag->codegen->invalid_inst_src;7284 return ag->codegen->invalid_inst_src;
72857285
...@@ -7341,7 +7341,7 @@ static IrInstSrc *ir_gen_continue(Stage1AstGen *ag, Scope *continue_scope, AstNo...@@ -7341,7 +7341,7 @@ static IrInstSrc *ir_gen_continue(Stage1AstGen *ag, Scope *continue_scope, AstNo
7341 }7341 }
7342 runtime_scopes.deinit();7342 runtime_scopes.deinit();
73437343
7344 IrBasicBlockSrc *dest_block = loop_scope->continue_block;7344 Stage1ZirBasicBlock *dest_block = loop_scope->continue_block;
7345 if (!ir_gen_defers_for_block(ag, continue_scope, dest_block->scope, nullptr, nullptr))7345 if (!ir_gen_defers_for_block(ag, continue_scope, dest_block->scope, nullptr, nullptr))
7346 return ag->codegen->invalid_inst_src;7346 return ag->codegen->invalid_inst_src;
7347 return ir_mark_gen(ir_build_br(ag, continue_scope, node, dest_block, is_comptime));7347 return ir_mark_gen(ir_build_br(ag, continue_scope, node, dest_block, is_comptime));
...@@ -7440,9 +7440,9 @@ static IrInstSrc *ir_gen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n...@@ -7440,9 +7440,9 @@ static IrInstSrc *ir_gen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n
7440 is_comptime = ir_build_test_comptime(ag, parent_scope, node, is_err);7440 is_comptime = ir_build_test_comptime(ag, parent_scope, node, is_err);
7441 }7441 }
74427442
7443 IrBasicBlockSrc *ok_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrOk");7443 Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrOk");
7444 IrBasicBlockSrc *err_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrError");7444 Stage1ZirBasicBlock *err_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrError");
7445 IrBasicBlockSrc *end_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrEnd");7445 Stage1ZirBasicBlock *end_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrEnd");
7446 IrInstSrc *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, is_err, err_block, ok_block, is_comptime);7446 IrInstSrc *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, is_err, err_block, ok_block, is_comptime);
74477447
7448 ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, ok_block, end_block, result_loc,7448 ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, ok_block, end_block, result_loc,
...@@ -7468,7 +7468,7 @@ static IrInstSrc *ir_gen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n...@@ -7468,7 +7468,7 @@ static IrInstSrc *ir_gen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n
7468 IrInstSrc *err_result = ir_gen_node_extra(ag, op2_node, err_scope, LValNone, &peer_parent->peers.at(0)->base);7468 IrInstSrc *err_result = ir_gen_node_extra(ag, op2_node, err_scope, LValNone, &peer_parent->peers.at(0)->base);
7469 if (err_result == ag->codegen->invalid_inst_src)7469 if (err_result == ag->codegen->invalid_inst_src)
7470 return ag->codegen->invalid_inst_src;7470 return ag->codegen->invalid_inst_src;
7471 IrBasicBlockSrc *after_err_block = ag->current_basic_block;7471 Stage1ZirBasicBlock *after_err_block = ag->current_basic_block;
7472 if (!instr_is_unreachable(err_result))7472 if (!instr_is_unreachable(err_result))
7473 ir_mark_gen(ir_build_br(ag, parent_scope, node, end_block, is_comptime));7473 ir_mark_gen(ir_build_br(ag, parent_scope, node, end_block, is_comptime));
74747474
...@@ -7476,14 +7476,14 @@ static IrInstSrc *ir_gen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n...@@ -7476,14 +7476,14 @@ static IrInstSrc *ir_gen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n
7476 IrInstSrc *unwrapped_ptr = ir_build_unwrap_err_payload_src(ag, parent_scope, node, err_union_ptr, false, false);7476 IrInstSrc *unwrapped_ptr = ir_build_unwrap_err_payload_src(ag, parent_scope, node, err_union_ptr, false, false);
7477 IrInstSrc *unwrapped_payload = ir_build_load_ptr(ag, parent_scope, node, unwrapped_ptr);7477 IrInstSrc *unwrapped_payload = ir_build_load_ptr(ag, parent_scope, node, unwrapped_ptr);
7478 ir_build_end_expr(ag, parent_scope, node, unwrapped_payload, &peer_parent->peers.at(1)->base);7478 ir_build_end_expr(ag, parent_scope, node, unwrapped_payload, &peer_parent->peers.at(1)->base);
7479 IrBasicBlockSrc *after_ok_block = ag->current_basic_block;7479 Stage1ZirBasicBlock *after_ok_block = ag->current_basic_block;
7480 ir_build_br(ag, parent_scope, node, end_block, is_comptime);7480 ir_build_br(ag, parent_scope, node, end_block, is_comptime);
74817481
7482 ir_set_cursor_at_end_and_append_block(ag, end_block);7482 ir_set_cursor_at_end_and_append_block(ag, end_block);
7483 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);7483 IrInstSrc **incoming_values = heap::c_allocator.allocate<IrInstSrc *>(2);
7484 incoming_values[0] = err_result;7484 incoming_values[0] = err_result;
7485 incoming_values[1] = unwrapped_payload;7485 incoming_values[1] = unwrapped_payload;
7486 IrBasicBlockSrc **incoming_blocks = heap::c_allocator.allocate<IrBasicBlockSrc *>(2);7486 Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate<Stage1ZirBasicBlock *>(2);
7487 incoming_blocks[0] = after_err_block;7487 incoming_blocks[0] = after_err_block;
7488 incoming_blocks[1] = after_ok_block;7488 incoming_blocks[1] = after_ok_block;
7489 IrInstSrc *phi = ir_build_phi(ag, parent_scope, node, 2, incoming_blocks, incoming_values, peer_parent);7489 IrInstSrc *phi = ir_build_phi(ag, parent_scope, node, 2, incoming_blocks, incoming_values, peer_parent);
...@@ -8045,7 +8045,7 @@ bool stage1_astgen(CodeGen *codegen, AstNode *node, Scope *scope, Stage1Zir *sta...@@ -8045,7 +8045,7 @@ bool stage1_astgen(CodeGen *codegen, AstNode *node, Scope *scope, Stage1Zir *sta
8045 ag->exec = stage1_zir;8045 ag->exec = stage1_zir;
8046 ag->main_block_node = node;8046 ag->main_block_node = node;
80478047
8048 IrBasicBlockSrc *entry_block = ir_create_basic_block(ag, scope, "Entry");8048 Stage1ZirBasicBlock *entry_block = ir_create_basic_block(ag, scope, "Entry");
8049 ir_set_cursor_at_end_and_append_block(ag, entry_block);8049 ir_set_cursor_at_end_and_append_block(ag, entry_block);
8050 // Entry block gets a reference because we enter it to begin.8050 // Entry block gets a reference because we enter it to begin.
8051 ir_ref_bb(ag->current_basic_block);8051 ir_ref_bb(ag->current_basic_block);
src/stage1/ir.cpp+18-18
...@@ -34,7 +34,7 @@ struct IrBuilderGen {...@@ -34,7 +34,7 @@ struct IrBuilderGen {
34struct IrAnalyze {34struct IrAnalyze {
35 CodeGen *codegen;35 CodeGen *codegen;
36 Stage1Zir *zir;36 Stage1Zir *zir;
37 IrBasicBlockSrc *zir_current_basic_block;37 Stage1ZirBasicBlock *zir_current_basic_block;
38 IrBuilderGen new_irb;38 IrBuilderGen new_irb;
39 size_t old_bb_index;39 size_t old_bb_index;
40 size_t instruction_index;40 size_t instruction_index;
...@@ -42,7 +42,7 @@ struct IrAnalyze {...@@ -42,7 +42,7 @@ struct IrAnalyze {
42 AstNode *explicit_return_type_source_node;42 AstNode *explicit_return_type_source_node;
43 ZigList<IrInstGen *> src_implicit_return_type_list;43 ZigList<IrInstGen *> src_implicit_return_type_list;
44 ZigList<IrSuspendPosition> resume_stack;44 ZigList<IrSuspendPosition> resume_stack;
45 IrBasicBlockSrc *const_predecessor_bb;45 Stage1ZirBasicBlock *const_predecessor_bb;
46 size_t ref_count;46 size_t ref_count;
47 size_t break_debug_id; // for debugging purposes47 size_t break_debug_id; // for debugging purposes
48 IrInstGen *return_ptr;48 IrInstGen *return_ptr;
...@@ -482,7 +482,7 @@ static void ira_deref(IrAnalyze *ira) {...@@ -482,7 +482,7 @@ static void ira_deref(IrAnalyze *ira) {
482 assert(ira->ref_count != 0);482 assert(ira->ref_count != 0);
483483
484 for (size_t bb_i = 0; bb_i < ira->zir->basic_block_list.length; bb_i += 1) {484 for (size_t bb_i = 0; bb_i < ira->zir->basic_block_list.length; bb_i += 1) {
485 IrBasicBlockSrc *pass1_bb = ira->zir->basic_block_list.items[bb_i];485 Stage1ZirBasicBlock *pass1_bb = ira->zir->basic_block_list.items[bb_i];
486 for (size_t inst_i = 0; inst_i < pass1_bb->instruction_list.length; inst_i += 1) {486 for (size_t inst_i = 0; inst_i < pass1_bb->instruction_list.length; inst_i += 1) {
487 IrInstSrc *pass1_inst = pass1_bb->instruction_list.items[inst_i];487 IrInstSrc *pass1_inst = pass1_bb->instruction_list.items[inst_i];
488 destroy_instruction_src(pass1_inst);488 destroy_instruction_src(pass1_inst);
...@@ -742,7 +742,7 @@ static IrBasicBlockGen *ir_create_basic_block_gen(IrAnalyze *ira, Scope *scope,...@@ -742,7 +742,7 @@ static IrBasicBlockGen *ir_create_basic_block_gen(IrAnalyze *ira, Scope *scope,
742 return result;742 return result;
743}743}
744744
745static IrBasicBlockGen *ir_build_bb_from(IrAnalyze *ira, IrBasicBlockSrc *other_bb) {745static IrBasicBlockGen *ir_build_bb_from(IrAnalyze *ira, Stage1ZirBasicBlock *other_bb) {
746 IrBasicBlockGen *new_bb = ir_create_basic_block_gen(ira, other_bb->scope, other_bb->name_hint);746 IrBasicBlockGen *new_bb = ir_create_basic_block_gen(ira, other_bb->scope, other_bb->name_hint);
747 other_bb->child = new_bb;747 other_bb->child = new_bb;
748 return new_bb;748 return new_bb;
...@@ -5261,7 +5261,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, IrInst* sourc...@@ -5261,7 +5261,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, IrInst* sourc
5261 return ir_build_ptr_of_array_to_slice(ira, source_instr, wanted_type, array_ptr, result_loc_inst);5261 return ir_build_ptr_of_array_to_slice(ira, source_instr, wanted_type, array_ptr, result_loc_inst);
5262}5262}
52635263
5264static IrBasicBlockGen *ir_get_new_bb(IrAnalyze *ira, IrBasicBlockSrc *old_bb, IrInst *ref_old_instruction) {5264static IrBasicBlockGen *ir_get_new_bb(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb, IrInst *ref_old_instruction) {
5265 assert(old_bb);5265 assert(old_bb);
52665266
5267 if (old_bb->child) {5267 if (old_bb->child) {
...@@ -5276,7 +5276,7 @@ static IrBasicBlockGen *ir_get_new_bb(IrAnalyze *ira, IrBasicBlockSrc *old_bb, I...@@ -5276,7 +5276,7 @@ static IrBasicBlockGen *ir_get_new_bb(IrAnalyze *ira, IrBasicBlockSrc *old_bb, I
5276 return new_bb;5276 return new_bb;
5277}5277}
52785278
5279static IrBasicBlockGen *ir_get_new_bb_runtime(IrAnalyze *ira, IrBasicBlockSrc *old_bb, IrInst *ref_old_instruction) {5279static IrBasicBlockGen *ir_get_new_bb_runtime(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb, IrInst *ref_old_instruction) {
5280 assert(ref_old_instruction != nullptr);5280 assert(ref_old_instruction != nullptr);
5281 IrBasicBlockGen *new_bb = ir_get_new_bb(ira, old_bb, ref_old_instruction);5281 IrBasicBlockGen *new_bb = ir_get_new_bb(ira, old_bb, ref_old_instruction);
5282 if (new_bb->must_be_comptime_source_instr) {5282 if (new_bb->must_be_comptime_source_instr) {
...@@ -5289,7 +5289,7 @@ static IrBasicBlockGen *ir_get_new_bb_runtime(IrAnalyze *ira, IrBasicBlockSrc *o...@@ -5289,7 +5289,7 @@ static IrBasicBlockGen *ir_get_new_bb_runtime(IrAnalyze *ira, IrBasicBlockSrc *o
5289 return new_bb;5289 return new_bb;
5290}5290}
52915291
5292static void ir_start_bb(IrAnalyze *ira, IrBasicBlockSrc *old_bb, IrBasicBlockSrc *const_predecessor_bb) {5292static void ir_start_bb(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb, Stage1ZirBasicBlock *const_predecessor_bb) {
5293 ir_assert(!old_bb->suspended, (old_bb->instruction_list.length != 0) ? &old_bb->instruction_list.at(0)->base : nullptr);5293 ir_assert(!old_bb->suspended, (old_bb->instruction_list.length != 0) ? &old_bb->instruction_list.at(0)->base : nullptr);
5294 ira->instruction_index = 0;5294 ira->instruction_index = 0;
5295 ira->zir_current_basic_block = old_bb;5295 ira->zir_current_basic_block = old_bb;
...@@ -5297,7 +5297,7 @@ static void ir_start_bb(IrAnalyze *ira, IrBasicBlockSrc *old_bb, IrBasicBlockSrc...@@ -5297,7 +5297,7 @@ static void ir_start_bb(IrAnalyze *ira, IrBasicBlockSrc *old_bb, IrBasicBlockSrc
5297 ira->old_bb_index = old_bb->index;5297 ira->old_bb_index = old_bb->index;
5298}5298}
52995299
5300static IrInstGen *ira_suspend(IrAnalyze *ira, IrInst *old_instruction, IrBasicBlockSrc *next_bb,5300static IrInstGen *ira_suspend(IrAnalyze *ira, IrInst *old_instruction, Stage1ZirBasicBlock *next_bb,
5301 IrSuspendPosition *suspend_pos)5301 IrSuspendPosition *suspend_pos)
5302{5302{
5303 if (ira->codegen->verbose_ir) {5303 if (ira->codegen->verbose_ir) {
...@@ -5356,7 +5356,7 @@ static void ir_start_next_bb(IrAnalyze *ira) {...@@ -5356,7 +5356,7 @@ static void ir_start_next_bb(IrAnalyze *ira) {
5356 bool need_repeat = true;5356 bool need_repeat = true;
5357 for (;;) {5357 for (;;) {
5358 while (ira->old_bb_index < ira->zir->basic_block_list.length) {5358 while (ira->old_bb_index < ira->zir->basic_block_list.length) {
5359 IrBasicBlockSrc *old_bb = ira->zir->basic_block_list.at(ira->old_bb_index);5359 Stage1ZirBasicBlock *old_bb = ira->zir->basic_block_list.at(ira->old_bb_index);
5360 if (old_bb->child == nullptr && old_bb->suspend_instruction_ref == nullptr) {5360 if (old_bb->child == nullptr && old_bb->suspend_instruction_ref == nullptr) {
5361 ira->old_bb_index += 1;5361 ira->old_bb_index += 1;
5362 continue;5362 continue;
...@@ -5447,7 +5447,7 @@ static bool ir_emit_backward_branch(IrAnalyze *ira, IrInst* source_instruction)...@@ -5447,7 +5447,7 @@ static bool ir_emit_backward_branch(IrAnalyze *ira, IrInst* source_instruction)
5447 return true;5447 return true;
5448}5448}
54495449
5450static IrInstGen *ir_inline_bb(IrAnalyze *ira, IrInst* source_instruction, IrBasicBlockSrc *old_bb) {5450static IrInstGen *ir_inline_bb(IrAnalyze *ira, IrInst* source_instruction, Stage1ZirBasicBlock *old_bb) {
5451 if (old_bb->debug_id <= ira->zir_current_basic_block->debug_id) {5451 if (old_bb->debug_id <= ira->zir_current_basic_block->debug_id) {
5452 if (!ir_emit_backward_branch(ira, source_instruction))5452 if (!ir_emit_backward_branch(ira, source_instruction))
5453 return ir_unreach_error(ira);5453 return ir_unreach_error(ira);
...@@ -13776,20 +13776,20 @@ static IrInstGen *ir_analyze_instruction_un_op(IrAnalyze *ira, IrInstSrcUnOp *in...@@ -13776,20 +13776,20 @@ static IrInstGen *ir_analyze_instruction_un_op(IrAnalyze *ira, IrInstSrcUnOp *in
13776}13776}
1377713777
13778static void ir_push_resume(IrAnalyze *ira, IrSuspendPosition pos) {13778static void ir_push_resume(IrAnalyze *ira, IrSuspendPosition pos) {
13779 IrBasicBlockSrc *old_bb = ira->zir->basic_block_list.at(pos.basic_block_index);13779 Stage1ZirBasicBlock *old_bb = ira->zir->basic_block_list.at(pos.basic_block_index);
13780 if (old_bb->in_resume_stack) return;13780 if (old_bb->in_resume_stack) return;
13781 ira->resume_stack.append(pos);13781 ira->resume_stack.append(pos);
13782 old_bb->in_resume_stack = true;13782 old_bb->in_resume_stack = true;
13783}13783}
1378413784
13785static void ir_push_resume_block(IrAnalyze *ira, IrBasicBlockSrc *old_bb) {13785static void ir_push_resume_block(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb) {
13786 if (ira->resume_stack.length != 0) {13786 if (ira->resume_stack.length != 0) {
13787 ir_push_resume(ira, {old_bb->index, 0});13787 ir_push_resume(ira, {old_bb->index, 0});
13788 }13788 }
13789}13789}
1379013790
13791static IrInstGen *ir_analyze_instruction_br(IrAnalyze *ira, IrInstSrcBr *br_instruction) {13791static IrInstGen *ir_analyze_instruction_br(IrAnalyze *ira, IrInstSrcBr *br_instruction) {
13792 IrBasicBlockSrc *old_dest_block = br_instruction->dest_block;13792 Stage1ZirBasicBlock *old_dest_block = br_instruction->dest_block;
1379313793
13794 bool is_comptime;13794 bool is_comptime;
13795 if (!ir_resolve_comptime(ira, br_instruction->is_comptime->child, &is_comptime))13795 if (!ir_resolve_comptime(ira, br_instruction->is_comptime->child, &is_comptime))
...@@ -13827,7 +13827,7 @@ static IrInstGen *ir_analyze_instruction_cond_br(IrAnalyze *ira, IrInstSrcCondBr...@@ -13827,7 +13827,7 @@ static IrInstGen *ir_analyze_instruction_cond_br(IrAnalyze *ira, IrInstSrcCondBr
13827 if (!ir_resolve_bool(ira, casted_condition, &cond_is_true))13827 if (!ir_resolve_bool(ira, casted_condition, &cond_is_true))
13828 return ir_unreach_error(ira);13828 return ir_unreach_error(ira);
1382913829
13830 IrBasicBlockSrc *old_dest_block = cond_is_true ?13830 Stage1ZirBasicBlock *old_dest_block = cond_is_true ?
13831 cond_br_instruction->then_block : cond_br_instruction->else_block;13831 cond_br_instruction->then_block : cond_br_instruction->else_block;
1383213832
13833 if (is_comptime || (old_dest_block->ref_count == 1 && old_dest_block->suspend_instruction_ref == nullptr))13833 if (is_comptime || (old_dest_block->ref_count == 1 && old_dest_block->suspend_instruction_ref == nullptr))
...@@ -13877,7 +13877,7 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i...@@ -13877,7 +13877,7 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
1387713877
13878 if (ira->const_predecessor_bb) {13878 if (ira->const_predecessor_bb) {
13879 for (size_t i = 0; i < phi_instruction->incoming_count; i += 1) {13879 for (size_t i = 0; i < phi_instruction->incoming_count; i += 1) {
13880 IrBasicBlockSrc *predecessor = phi_instruction->incoming_blocks[i];13880 Stage1ZirBasicBlock *predecessor = phi_instruction->incoming_blocks[i];
13881 if (predecessor != ira->const_predecessor_bb)13881 if (predecessor != ira->const_predecessor_bb)
13882 continue;13882 continue;
13883 IrInstGen *value = phi_instruction->incoming_values[i]->child;13883 IrInstGen *value = phi_instruction->incoming_values[i]->child;
...@@ -13977,7 +13977,7 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i...@@ -13977,7 +13977,7 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i
13977 ZigList<IrInstGen*> new_incoming_values = {0};13977 ZigList<IrInstGen*> new_incoming_values = {0};
1397813978
13979 for (size_t i = 0; i < phi_instruction->incoming_count; i += 1) {13979 for (size_t i = 0; i < phi_instruction->incoming_count; i += 1) {
13980 IrBasicBlockSrc *predecessor = phi_instruction->incoming_blocks[i];13980 Stage1ZirBasicBlock *predecessor = phi_instruction->incoming_blocks[i];
13981 if (predecessor->ref_count == 0)13981 if (predecessor->ref_count == 0)
13982 continue;13982 continue;
1398313983
...@@ -15996,7 +15996,7 @@ static IrInstGen *ir_analyze_instruction_switch_br(IrAnalyze *ira,...@@ -15996,7 +15996,7 @@ static IrInstGen *ir_analyze_instruction_switch_br(IrAnalyze *ira,
15996 if (!target_val)15996 if (!target_val)
15997 return ir_unreach_error(ira);15997 return ir_unreach_error(ira);
1599815998
15999 IrBasicBlockSrc *old_dest_block = switch_br_instruction->else_block;15999 Stage1ZirBasicBlock *old_dest_block = switch_br_instruction->else_block;
16000 for (size_t i = 0; i < case_count; i += 1) {16000 for (size_t i = 0; i < case_count; i += 1) {
16001 IrInstSrcSwitchBrCase *old_case = &switch_br_instruction->cases[i];16001 IrInstSrcSwitchBrCase *old_case = &switch_br_instruction->cases[i];
16002 IrInstGen *case_value = old_case->value->child;16002 IrInstGen *case_value = old_case->value->child;
...@@ -24488,7 +24488,7 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a...@@ -24488,7 +24488,7 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a
24488 ira->new_irb.codegen = codegen;24488 ira->new_irb.codegen = codegen;
24489 ira->new_irb.exec = stage1_air;24489 ira->new_irb.exec = stage1_air;
2449024490
24491 IrBasicBlockSrc *old_entry_bb = ira->zir->basic_block_list.at(0);24491 Stage1ZirBasicBlock *old_entry_bb = ira->zir->basic_block_list.at(0);
24492 IrBasicBlockGen *new_entry_bb = ir_get_new_bb(ira, old_entry_bb, nullptr);24492 IrBasicBlockGen *new_entry_bb = ir_get_new_bb(ira, old_entry_bb, nullptr);
24493 ira->new_irb.current_basic_block = new_entry_bb;24493 ira->new_irb.current_basic_block = new_entry_bb;
24494 ira->old_bb_index = 0;24494 ira->old_bb_index = 0;
src/stage1/ir_print.cpp+4-4
...@@ -633,7 +633,7 @@ static void ir_print_other_inst_gen(IrPrintGen *irp, IrInstGen *inst) {...@@ -633,7 +633,7 @@ static void ir_print_other_inst_gen(IrPrintGen *irp, IrInstGen *inst) {
633 }633 }
634}634}
635635
636static void ir_print_other_block(IrPrintSrc *irp, IrBasicBlockSrc *bb) {636static void ir_print_other_block(IrPrintSrc *irp, Stage1ZirBasicBlock *bb) {
637 if (bb == nullptr) {637 if (bb == nullptr) {
638 fprintf(irp->f, "(null block)");638 fprintf(irp->f, "(null block)");
639 } else {639 } else {
...@@ -1006,7 +1006,7 @@ static void ir_print_phi(IrPrintSrc *irp, IrInstSrcPhi *phi_instruction) {...@@ -1006,7 +1006,7 @@ static void ir_print_phi(IrPrintSrc *irp, IrInstSrcPhi *phi_instruction) {
1006 assert(phi_instruction->incoming_count != 0);1006 assert(phi_instruction->incoming_count != 0);
1007 assert(phi_instruction->incoming_count != SIZE_MAX);1007 assert(phi_instruction->incoming_count != SIZE_MAX);
1008 for (size_t i = 0; i < phi_instruction->incoming_count; i += 1) {1008 for (size_t i = 0; i < phi_instruction->incoming_count; i += 1) {
1009 IrBasicBlockSrc *incoming_block = phi_instruction->incoming_blocks[i];1009 Stage1ZirBasicBlock *incoming_block = phi_instruction->incoming_blocks[i];
1010 IrInstSrc *incoming_value = phi_instruction->incoming_values[i];1010 IrInstSrc *incoming_value = phi_instruction->incoming_values[i];
1011 if (i != 0)1011 if (i != 0)
1012 fprintf(irp->f, " ");1012 fprintf(irp->f, " ");
...@@ -3350,7 +3350,7 @@ static void ir_print_inst_gen(IrPrintGen *irp, IrInstGen *instruction, bool trai...@@ -3350,7 +3350,7 @@ static void ir_print_inst_gen(IrPrintGen *irp, IrInstGen *instruction, bool trai
3350 fprintf(irp->f, "\n");3350 fprintf(irp->f, "\n");
3351}3351}
33523352
3353static void irp_print_basic_block_src(IrPrintSrc *irp, IrBasicBlockSrc *current_block) {3353static void irp_print_basic_block_src(IrPrintSrc *irp, Stage1ZirBasicBlock *current_block) {
3354 fprintf(irp->f, "%s_%" PRIu32 ":\n", current_block->name_hint, current_block->debug_id);3354 fprintf(irp->f, "%s_%" PRIu32 ":\n", current_block->name_hint, current_block->debug_id);
3355 for (size_t instr_i = 0; instr_i < current_block->instruction_list.length; instr_i += 1) {3355 for (size_t instr_i = 0; instr_i < current_block->instruction_list.length; instr_i += 1) {
3356 IrInstSrc *instruction = current_block->instruction_list.at(instr_i);3356 IrInstSrc *instruction = current_block->instruction_list.at(instr_i);
...@@ -3370,7 +3370,7 @@ static void irp_print_basic_block_gen(IrPrintGen *irp, IrBasicBlockGen *current_...@@ -3370,7 +3370,7 @@ static void irp_print_basic_block_gen(IrPrintGen *irp, IrBasicBlockGen *current_
3370 }3370 }
3371}3371}
33723372
3373void ir_print_basic_block_src(CodeGen *codegen, FILE *f, IrBasicBlockSrc *bb, int indent_size) {3373void ir_print_basic_block_src(CodeGen *codegen, FILE *f, Stage1ZirBasicBlock *bb, int indent_size) {
3374 IrPrintSrc ir_print = {};3374 IrPrintSrc ir_print = {};
3375 ir_print.codegen = codegen;3375 ir_print.codegen = codegen;
3376 ir_print.f = f;3376 ir_print.f = f;
src/stage1/ir_print.hpp+1-1
...@@ -16,7 +16,7 @@ void ir_print_src(CodeGen *codegen, FILE *f, Stage1Zir *executable, int indent_s...@@ -16,7 +16,7 @@ void ir_print_src(CodeGen *codegen, FILE *f, Stage1Zir *executable, int indent_s
16void ir_print_gen(CodeGen *codegen, FILE *f, Stage1Air *executable, int indent_size);16void ir_print_gen(CodeGen *codegen, FILE *f, Stage1Air *executable, int indent_size);
17void ir_print_inst_src(CodeGen *codegen, FILE *f, IrInstSrc *inst, int indent_size);17void ir_print_inst_src(CodeGen *codegen, FILE *f, IrInstSrc *inst, int indent_size);
18void ir_print_inst_gen(CodeGen *codegen, FILE *f, IrInstGen *inst, int indent_size);18void ir_print_inst_gen(CodeGen *codegen, FILE *f, IrInstGen *inst, int indent_size);
19void ir_print_basic_block_src(CodeGen *codegen, FILE *f, IrBasicBlockSrc *bb, int indent_size);19void ir_print_basic_block_src(CodeGen *codegen, FILE *f, Stage1ZirBasicBlock *bb, int indent_size);
20void ir_print_basic_block_gen(CodeGen *codegen, FILE *f, IrBasicBlockGen *bb, int indent_size);20void ir_print_basic_block_gen(CodeGen *codegen, FILE *f, IrBasicBlockGen *bb, int indent_size);
2121
22const char* ir_inst_src_type_str(IrInstSrcId id);22const char* ir_inst_src_type_str(IrInstSrcId id);