| author |  Alex Rønne Petersen <alex@alexrp.com> 2025-01-06 16:47:40+01:00 |
| committer | Alex Rønne Petersen <alex@alexrp.com> 2025-01-06 16:47:40+01:00 |
| log | 03ac40d5709060168e10c9c3187ffb5a161e773b |
| tree | 9f7a4db33a7e56ceea0c8ed69bb91ca5484b2293 |
| parent | c1ae99efb30b1dcc86b3f41b419685a62413378e |
| signature |  Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM |
std: Disable some tests affected by #22060 for thumbeb too.
2 files changed, 2 insertions(+), 2 deletions(-)
lib/std/fmt.zig+1-1
| ... | ... | @@ -2596,7 +2596,7 @@ test "positional/alignment/width/precision" { |
| 2596 | 2596 | } |
| 2597 | 2597 | |
| 2598 | 2598 | test "vector" { |
| 2599 | if (builtin.cpu.arch == .armeb and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/22060 | |
| 2599 | if ((builtin.cpu.arch == .armeb or builtin.cpu.arch == .thumbeb) and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/22060 | |
| 2600 | 2600 | if (builtin.target.cpu.arch == .riscv64) { |
| 2601 | 2601 | // https://github.com/ziglang/zig/issues/4486 |
| 2602 | 2602 | return error.SkipZigTest; |
lib/std/simd.zig+1-1
| ... | ... | @@ -462,7 +462,7 @@ pub fn prefixScan(comptime op: std.builtin.ReduceOp, comptime hop: isize, vec: a |
| 462 | 462 | |
| 463 | 463 | test "vector prefix scan" { |
| 464 | 464 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; |
| 465 | if (builtin.cpu.arch == .armeb and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/22060 | |
| 465 | if ((builtin.cpu.arch == .armeb or builtin.cpu.arch == .thumbeb) and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/22060 | |
| 466 | 466 | if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/21893 |
| 467 | 467 | |
| 468 | 468 | if (comptime builtin.cpu.arch.isMIPS()) { |