authorgravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-05-07 03:14:31-04:00
committergravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-05-08 07:36:20-04:00
log05580b9453e4ae2d9b62fe4178651937d8b73989
treeb04b981c4a17c1df0ba17d9d0c703e21b220b9e0
parent1c53f0a6b0b1866663346c473da310203a317e90

x86_64: implement float cast from `f16` to `f64`

7 files changed, 292 insertions(+), 211 deletions(-)

src/arch/x86_64/CodeGen.zig+67-28
......@@ -2287,26 +2287,46 @@ fn airFptrunc(self: *Self, inst: Air.Inst.Index) !void {
22872287 src_mcv
22882288 else
22892289 try self.copyToRegisterWithInstTracking(inst, dst_ty, src_mcv);
2290 const dst_lock = self.register_manager.lockReg(dst_mcv.register);
2290 const dst_reg = dst_mcv.getReg().?.to128();
2291 const dst_lock = self.register_manager.lockReg(dst_reg);
22912292 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
22922293
2293 if (src_bits == 32 and dst_bits == 16 and self.hasFeature(.f16c))
2294 try self.asmRegisterRegisterImmediate(
2295 .vcvtps2ph,
2296 dst_mcv.register,
2297 if (src_mcv.isRegister()) src_mcv.getReg().? else src_reg: {
2298 const src_reg = dst_mcv.register;
2299 try self.genSetReg(src_reg, src_ty, src_mcv);
2300 break :src_reg src_reg;
2294 if (dst_bits == 16 and self.hasFeature(.f16c)) {
2295 switch (src_bits) {
2296 32 => {
2297 const mat_src_reg = if (src_mcv.isRegister())
2298 src_mcv.getReg().?
2299 else
2300 try self.copyToTmpRegister(src_ty, src_mcv);
2301 try self.asmRegisterRegisterImmediate(
2302 .vcvtps2ph,
2303 dst_reg,
2304 mat_src_reg.to128(),
2305 Immediate.u(0b1_00),
2306 );
23012307 },
2302 Immediate.u(0b1_00),
2303 )
2304 else if (src_bits == 64 and dst_bits == 32)
2305 try self.genBinOpMir(.cvtsd2ss, src_ty, dst_mcv, src_mcv)
2306 else
2307 return self.fail("TODO implement airFptrunc from {} to {}", .{
2308 src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
2309 });
2308 else => return self.fail("TODO implement airFptrunc from {} to {}", .{
2309 src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
2310 }),
2311 }
2312 } else if (src_bits == 64 and dst_bits == 32) {
2313 if (self.hasFeature(.avx)) if (src_mcv.isRegister()) try self.asmRegisterRegisterRegister(
2314 .vcvtsd2ss,
2315 dst_reg,
2316 dst_reg,
2317 src_mcv.getReg().?.to128(),
2318 ) else try self.asmRegisterRegisterMemory(
2319 .vcvtsd2ss,
2320 dst_reg,
2321 dst_reg,
2322 src_mcv.mem(.qword),
2323 ) else if (src_mcv.isRegister())
2324 try self.asmRegisterRegister(.cvtsd2ss, dst_reg, src_mcv.getReg().?.to128())
2325 else
2326 try self.asmRegisterMemory(.cvtsd2ss, dst_reg, src_mcv.mem(.qword));
2327 } else return self.fail("TODO implement airFptrunc from {} to {}", .{
2328 src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
2329 });
23102330 return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });
23112331}
23122332
......@@ -2322,22 +2342,41 @@ fn airFpext(self: *Self, inst: Air.Inst.Index) !void {
23222342 src_mcv
23232343 else
23242344 try self.copyToRegisterWithInstTracking(inst, dst_ty, src_mcv);
2325 const dst_lock = self.register_manager.lockReg(dst_mcv.register);
2345 const dst_reg = dst_mcv.getReg().?.to128();
2346 const dst_lock = self.register_manager.lockReg(dst_reg);
23262347 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
23272348
2328 try self.genBinOpMir(
2329 if (src_bits == 16 and dst_bits == 32 and self.hasFeature(.f16c))
2330 .vcvtph2ps
2331 else if (src_bits == 32 and dst_bits == 64)
2332 .cvtss2sd
2349 if (src_bits == 16 and self.hasFeature(.f16c)) {
2350 const mat_src_reg = if (src_mcv.isRegister())
2351 src_mcv.getReg().?
23332352 else
2334 return self.fail("TODO implement airFpext from {} to {}", .{
2353 try self.copyToTmpRegister(src_ty, src_mcv);
2354 try self.asmRegisterRegister(.vcvtph2ps, dst_reg, mat_src_reg.to128());
2355 switch (dst_bits) {
2356 32 => {},
2357 64 => try self.asmRegisterRegisterRegister(.vcvtss2sd, dst_reg, dst_reg, dst_reg),
2358 else => return self.fail("TODO implement airFpext from {} to {}", .{
23352359 src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
23362360 }),
2337 src_ty,
2338 dst_mcv,
2339 src_mcv,
2340 );
2361 }
2362 } else if (src_bits == 32 and dst_bits == 64) {
2363 if (self.hasFeature(.avx)) if (src_mcv.isRegister()) try self.asmRegisterRegisterRegister(
2364 .vcvtss2sd,
2365 dst_reg,
2366 dst_reg,
2367 src_mcv.getReg().?.to128(),
2368 ) else try self.asmRegisterRegisterMemory(
2369 .vcvtss2sd,
2370 dst_reg,
2371 dst_reg,
2372 src_mcv.mem(.dword),
2373 ) else if (src_mcv.isRegister())
2374 try self.asmRegisterRegister(.cvtss2sd, dst_reg, src_mcv.getReg().?.to128())
2375 else
2376 try self.asmRegisterMemory(.cvtss2sd, dst_reg, src_mcv.mem(.dword));
2377 } else return self.fail("TODO implement airFpext from {} to {}", .{
2378 src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
2379 });
23412380 return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });
23422381}
23432382
src/arch/x86_64/Encoding.zig+96-69
......@@ -89,30 +89,13 @@ pub fn findByOpcode(opc: []const u8, prefixes: struct {
8989 if (modrm_ext) |ext| if (ext != data.modrm_ext) continue;
9090 if (!std.mem.eql(u8, opc, enc.opcode())) continue;
9191 if (prefixes.rex.w) {
92 switch (data.mode) {
93 .none, .short, .rex, .rex_short, .vex_128, .vex_256 => continue,
94 .long, .vex_128_long, .vex_256_long => {},
95 }
92 if (!data.mode.isLong()) continue;
9693 } else if (prefixes.rex.present and !prefixes.rex.isSet()) {
97 switch (data.mode) {
98 .rex, .rex_short => {},
99 else => continue,
100 }
94 if (!data.mode.isRex()) continue;
10195 } else if (prefixes.legacy.prefix_66) {
102 switch (data.mode) {
103 .short, .rex_short => {},
104 .none, .rex, .vex_128, .vex_256 => continue,
105 .long, .vex_128_long, .vex_256_long => continue,
106 }
96 if (!data.mode.isShort()) continue;
10797 } else {
108 switch (data.mode) {
109 .none => switch (data.mode) {
110 .short, .rex_short => continue,
111 .none, .rex, .vex_128, .vex_256 => {},
112 .long, .vex_128_long, .vex_256_long => {},
113 },
114 else => continue,
115 }
98 if (data.mode.isShort()) continue;
11699 }
117100 return enc;
118101 };
......@@ -148,50 +131,39 @@ pub fn format(
148131 _ = fmt;
149132
150133 var opc = encoding.opcode();
151 switch (encoding.data.mode) {
152 else => {},
153 .long => try writer.writeAll("REX.W + "),
154 .vex_128, .vex_128_long, .vex_256, .vex_256_long => {
155 try writer.writeAll("VEX.");
156
157 switch (encoding.data.mode) {
158 .vex_128, .vex_128_long => try writer.writeAll("128"),
159 .vex_256, .vex_256_long => try writer.writeAll("256"),
160 else => unreachable,
161 }
162
163 switch (opc[0]) {
164 else => {},
165 0x66, 0xf3, 0xf2 => {
166 try writer.print(".{X:0>2}", .{opc[0]});
167 opc = opc[1..];
168 },
169 }
134 if (encoding.data.mode.isVex()) {
135 try writer.writeAll("VEX.");
136
137 try writer.writeAll(switch (encoding.data.mode) {
138 .vex_128_w0, .vex_128_w1, .vex_128_wig => "128",
139 .vex_256_w0, .vex_256_w1, .vex_256_wig => "256",
140 .vex_lig_w0, .vex_lig_w1, .vex_lig_wig => "LIG",
141 .vex_lz_w0, .vex_lz_w1, .vex_lz_wig => "LZ",
142 else => unreachable,
143 });
170144
171 try writer.print(".{X:0>2}", .{opc[0]});
172 opc = opc[1..];
145 switch (opc[0]) {
146 else => {},
147 0x66, 0xf3, 0xf2 => {
148 try writer.print(".{X:0>2}", .{opc[0]});
149 opc = opc[1..];
150 },
151 }
173152
174 switch (opc[0]) {
175 else => {},
176 0x38, 0x3A => {
177 try writer.print("{X:0>2}", .{opc[0]});
178 opc = opc[1..];
179 },
180 }
153 try writer.print(".{}", .{std.fmt.fmtSliceHexUpper(opc[0 .. opc.len - 1])});
154 opc = opc[opc.len - 1 ..];
181155
182 try writer.writeByte('.');
183 try writer.writeAll(switch (encoding.data.mode) {
184 .vex_128, .vex_256 => "W0",
185 .vex_128_long, .vex_256_long => "W1",
186 else => unreachable,
187 });
188 try writer.writeByte(' ');
189 },
190 }
156 try writer.writeAll(".W");
157 try writer.writeAll(switch (encoding.data.mode) {
158 .vex_128_w0, .vex_256_w0, .vex_lig_w0, .vex_lz_w0 => "0",
159 .vex_128_w1, .vex_256_w1, .vex_lig_w1, .vex_lz_w1 => "1",
160 .vex_128_wig, .vex_256_wig, .vex_lig_wig, .vex_lz_wig => "IG",
161 else => unreachable,
162 });
191163
192 for (opc) |byte| {
193 try writer.print("{x:0>2} ", .{byte});
194 }
164 try writer.writeByte(' ');
165 } else if (encoding.data.mode.isLong()) try writer.writeAll("REX.W + ");
166 for (opc) |byte| try writer.print("{x:0>2} ", .{byte});
195167
196168 switch (encoding.data.op_en) {
197169 .np, .fd, .td, .i, .zi, .d => {},
......@@ -332,6 +304,7 @@ pub const Mnemonic = enum {
332304 // SSE4.1
333305 roundsd, roundss,
334306 // AVX
307 vcvtsd2ss, vcvtsi2sd, vcvtsi2ss, vcvtss2sd,
335308 vmovapd, vmovaps,
336309 vmovddup,
337310 vmovsd,
......@@ -629,20 +602,74 @@ pub const Op = enum {
629602};
630603
631604pub const Mode = enum {
605 // zig fmt: off
632606 none,
633 short,
634 long,
635 rex,
636 rex_short,
637 vex_128,
638 vex_128_long,
639 vex_256,
640 vex_256_long,
607 short, long,
608 rex, rex_short,
609 vex_128_w0, vex_128_w1, vex_128_wig,
610 vex_256_w0, vex_256_w1, vex_256_wig,
611 vex_lig_w0, vex_lig_w1, vex_lig_wig,
612 vex_lz_w0, vex_lz_w1, vex_lz_wig,
613 // zig fmt: on
614
615 pub fn isShort(mode: Mode) bool {
616 return switch (mode) {
617 .short, .rex_short => true,
618 else => false,
619 };
620 }
621
622 pub fn isLong(mode: Mode) bool {
623 return switch (mode) {
624 .long,
625 .vex_128_w1,
626 .vex_256_w1,
627 .vex_lig_w1,
628 .vex_lz_w1,
629 => true,
630 else => false,
631 };
632 }
633
634 pub fn isRex(mode: Mode) bool {
635 return switch (mode) {
636 else => false,
637 .rex, .rex_short => true,
638 };
639 }
640
641 pub fn isVex(mode: Mode) bool {
642 return switch (mode) {
643 // zig fmt: off
644 else => false,
645 .vex_128_w0, .vex_128_w1, .vex_128_wig,
646 .vex_256_w0, .vex_256_w1, .vex_256_wig,
647 .vex_lig_w0, .vex_lig_w1, .vex_lig_wig,
648 .vex_lz_w0, .vex_lz_w1, .vex_lz_wig,
649 => true,
650 // zig fmt: on
651 };
652 }
653
654 pub fn isVecLong(mode: Mode) bool {
655 return switch (mode) {
656 // zig fmt: off
657 else => unreachable,
658 .vex_128_w0, .vex_128_w1, .vex_128_wig,
659 .vex_lig_w0, .vex_lig_w1, .vex_lig_wig,
660 .vex_lz_w0, .vex_lz_w1, .vex_lz_wig,
661 => false,
662 .vex_256_w0, .vex_256_w1, .vex_256_wig,
663 => true,
664 // zig fmt: on
665 };
666 }
641667};
642668
643669pub const Feature = enum {
644670 none,
645671 avx,
672 avx2,
646673 f16c,
647674 fma,
648675 sse,
src/arch/x86_64/Lower.zig+4
......@@ -184,6 +184,10 @@ pub fn lowerMir(lower: *Lower, index: Mir.Inst.Index) Error!struct {
184184 .roundsd,
185185 .roundss,
186186
187 .vcvtsd2ss,
188 .vcvtsi2sd,
189 .vcvtsi2ss,
190 .vcvtss2sd,
187191 .vmovapd,
188192 .vmovaps,
189193 .vmovddup,
src/arch/x86_64/Mir.zig+8
......@@ -282,6 +282,14 @@ pub const Inst = struct {
282282 /// Round scalar single-precision floating-point values
283283 roundss,
284284
285 /// Convert scalar double-precision floating-point value to scalar single-precision floating-point value
286 vcvtsd2ss,
287 /// Convert doubleword integer to scalar double-precision floating-point value
288 vcvtsi2sd,
289 /// Convert doubleword integer to scalar single-precision floating-point value
290 vcvtsi2ss,
291 /// Convert scalar single-precision floating-point value to scalar double-precision floating-point value
292 vcvtss2sd,
285293 /// Move aligned packed double-precision floating-point values
286294 vmovapd,
287295 /// Move aligned packed single-precision floating-point values
src/arch/x86_64/encoder.zig+11-22
......@@ -206,18 +206,15 @@ pub const Instruction = struct {
206206 const enc = inst.encoding;
207207 const data = enc.data;
208208
209 switch (data.mode) {
210 .none, .short, .long, .rex, .rex_short => {
211 try inst.encodeLegacyPrefixes(encoder);
212 try inst.encodeMandatoryPrefix(encoder);
213 try inst.encodeRexPrefix(encoder);
214 try inst.encodeOpcode(encoder);
215 },
216 .vex_128, .vex_128_long, .vex_256, .vex_256_long => {
217 try inst.encodeVexPrefix(encoder);
218 const opc = inst.encoding.opcode();
219 try encoder.opcode_1byte(opc[opc.len - 1]);
220 },
209 if (data.mode.isVex()) {
210 try inst.encodeVexPrefix(encoder);
211 const opc = inst.encoding.opcode();
212 try encoder.opcode_1byte(opc[opc.len - 1]);
213 } else {
214 try inst.encodeLegacyPrefixes(encoder);
215 try inst.encodeMandatoryPrefix(encoder);
216 try inst.encodeRexPrefix(encoder);
217 try inst.encodeOpcode(encoder);
221218 }
222219
223220 switch (data.op_en) {
......@@ -365,11 +362,7 @@ pub const Instruction = struct {
365362
366363 var vex = Vex{};
367364
368 vex.w = switch (inst.encoding.data.mode) {
369 .vex_128, .vex_256 => false,
370 .vex_128_long, .vex_256_long => true,
371 else => unreachable,
372 };
365 vex.w = inst.encoding.data.mode.isLong();
373366
374367 switch (op_en) {
375368 .np, .i, .zi, .fd, .td, .d => {},
......@@ -395,11 +388,7 @@ pub const Instruction = struct {
395388 },
396389 }
397390
398 vex.l = switch (inst.encoding.data.mode) {
399 .vex_128, .vex_128_long => false,
400 .vex_256, .vex_256_long => true,
401 else => unreachable,
402 };
391 vex.l = inst.encoding.data.mode.isVecLong();
403392
404393 vex.p = if (mand_pre) |mand| switch (mand) {
405394 0x66 => .@"66",
src/arch/x86_64/encodings.zig+104-91
......@@ -918,7 +918,6 @@ pub const table = [_]Entry{
918918 .{ .orpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x56 }, 0, .none, .sse2 },
919919
920920 .{ .pextrw, .rmi, &.{ .r32, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0xc5 }, 0, .none, .sse2 },
921 .{ .pextrw, .rmi, &.{ .r64, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0xc5 }, 0, .long, .sse2 },
922921
923922 .{ .pinsrw, .rmi, &.{ .xmm, .r32_m16, .imm8 }, &.{ 0x66, 0x0f, 0xc4 }, 0, .none, .sse2 },
924923
......@@ -926,31 +925,23 @@ pub const table = [_]Entry{
926925
927926 .{ .pshuflw, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0xf2, 0x0f, 0x70 }, 0, .none, .sse2 },
928927
928 .{ .psrlw, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd1 }, 0, .none, .sse2 },
929 .{ .psrlw, .mi, &.{ .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 2, .none, .sse2 },
929930 .{ .psrld, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd2 }, 0, .none, .sse2 },
930931 .{ .psrld, .mi, &.{ .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x72 }, 2, .none, .sse2 },
931
932932 .{ .psrlq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd3 }, 0, .none, .sse2 },
933933 .{ .psrlq, .mi, &.{ .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x73 }, 2, .none, .sse2 },
934934
935 .{ .psrlw, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd1 }, 0, .none, .sse2 },
936 .{ .psrlw, .mi, &.{ .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 2, .none, .sse2 },
937
938 .{ .punpckhbw, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x68 }, 0, .none, .sse2 },
939
940 .{ .punpckhdq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6a }, 0, .none, .sse2 },
941
935 .{ .punpckhbw, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x68 }, 0, .none, .sse2 },
936 .{ .punpckhwd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x69 }, 0, .none, .sse2 },
937 .{ .punpckhdq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6a }, 0, .none, .sse2 },
942938 .{ .punpckhqdq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6d }, 0, .none, .sse2 },
943939
944 .{ .punpckhwd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x69 }, 0, .none, .sse2 },
945
946 .{ .punpcklbw, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x60 }, 0, .none, .sse2 },
947
948 .{ .punpckldq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x62 }, 0, .none, .sse2 },
949
940 .{ .punpcklbw, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x60 }, 0, .none, .sse2 },
941 .{ .punpcklwd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x61 }, 0, .none, .sse2 },
942 .{ .punpckldq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x62 }, 0, .none, .sse2 },
950943 .{ .punpcklqdq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6c }, 0, .none, .sse2 },
951944
952 .{ .punpcklwd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x61 }, 0, .none, .sse2 },
953
954945 .{ .sqrtpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x51 }, 0, .none, .sse2 },
955946 .{ .sqrtsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x51 }, 0, .none, .sse2 },
956947
......@@ -972,106 +963,128 @@ pub const table = [_]Entry{
972963
973964 // SSE4.1
974965 .{ .pextrw, .mri, &.{ .r32_m16, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x15 }, 0, .none, .sse4_1 },
975 .{ .pextrw, .mri, &.{ .r64_m16, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x15 }, 0, .long, .sse4_1 },
976966
977967 .{ .roundss, .rmi, &.{ .xmm, .xmm_m32, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0a }, 0, .none, .sse4_1 },
978968 .{ .roundsd, .rmi, &.{ .xmm, .xmm_m64, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0b }, 0, .none, .sse4_1 },
979969
980970 // AVX
981 .{ .vmovapd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x28 }, 0, .vex_128, .avx },
982 .{ .vmovapd, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x66, 0x0f, 0x29 }, 0, .vex_128, .avx },
983 .{ .vmovapd, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x28 }, 0, .vex_256, .avx },
984 .{ .vmovapd, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x66, 0x0f, 0x29 }, 0, .vex_256, .avx },
985
986 .{ .vmovaps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x28 }, 0, .vex_128, .avx },
987 .{ .vmovaps, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x0f, 0x29 }, 0, .vex_128, .avx },
988 .{ .vmovaps, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x0f, 0x28 }, 0, .vex_256, .avx },
989 .{ .vmovaps, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x0f, 0x29 }, 0, .vex_256, .avx },
990
991 .{ .vmovddup, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x12 }, 0, .vex_128, .avx },
992
993 .{ .vmovsd, .rvm, &.{ .xmm, .xmm, .xmm }, &.{ 0xf2, 0x0f, 0x10 }, 0, .vex_128, .avx },
994 .{ .vmovsd, .rm, &.{ .xmm, .m64 }, &.{ 0xf2, 0x0f, 0x10 }, 0, .vex_128, .avx },
995 .{ .vmovsd, .mvr, &.{ .xmm, .xmm, .xmm }, &.{ 0xf2, 0x0f, 0x11 }, 0, .vex_128, .avx },
996 .{ .vmovsd, .mr, &.{ .m64, .xmm }, &.{ 0xf2, 0x0f, 0x11 }, 0, .vex_128, .avx },
997
998 .{ .vmovshdup, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0xf3, 0x0f, 0x16 }, 0, .vex_128, .avx },
971 .{ .vcvtsd2ss, .rvm, &.{ .xmm, .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x5a }, 0, .vex_lig_wig, .avx },
999972
1000 .{ .vmovsldup, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0xf3, 0x0f, 0x12 }, 0, .vex_128, .avx },
973 .{ .vcvtsi2sd, .rvm, &.{ .xmm, .xmm, .rm32 }, &.{ 0xf2, 0x0f, 0x2a }, 0, .vex_lig_w0, .avx },
974 .{ .vcvtsi2sd, .rvm, &.{ .xmm, .xmm, .rm64 }, &.{ 0xf2, 0x0f, 0x2a }, 0, .vex_lig_w1, .avx },
1001975
1002 .{ .vmovss, .rvm, &.{ .xmm, .xmm, .xmm }, &.{ 0xf3, 0x0f, 0x10 }, 0, .vex_128, .avx },
1003 .{ .vmovss, .rm, &.{ .xmm, .m32 }, &.{ 0xf3, 0x0f, 0x10 }, 0, .vex_128, .avx },
1004 .{ .vmovss, .mvr, &.{ .xmm, .xmm, .xmm }, &.{ 0xf3, 0x0f, 0x11 }, 0, .vex_128, .avx },
1005 .{ .vmovss, .mr, &.{ .m32, .xmm }, &.{ 0xf3, 0x0f, 0x11 }, 0, .vex_128, .avx },
976 .{ .vcvtsi2ss, .rvm, &.{ .xmm, .xmm, .rm32 }, &.{ 0xf2, 0x0f, 0x2a }, 0, .vex_lig_w0, .avx },
977 .{ .vcvtsi2ss, .rvm, &.{ .xmm, .xmm, .rm64 }, &.{ 0xf2, 0x0f, 0x2a }, 0, .vex_lig_w1, .avx },
1006978
1007 .{ .vmovupd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x10 }, 0, .vex_128, .avx },
1008 .{ .vmovupd, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x66, 0x0f, 0x11 }, 0, .vex_128, .avx },
1009 .{ .vmovupd, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x10 }, 0, .vex_256, .avx },
1010 .{ .vmovupd, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x66, 0x0f, 0x11 }, 0, .vex_256, .avx },
979 .{ .vcvtss2sd, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0xf2, 0x0f, 0x5a }, 0, .vex_lig_wig, .avx },
1011980
1012 .{ .vmovups, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x10 }, 0, .vex_128, .avx },
1013 .{ .vmovups, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x0f, 0x11 }, 0, .vex_128, .avx },
1014 .{ .vmovups, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x0f, 0x10 }, 0, .vex_256, .avx },
1015 .{ .vmovups, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x0f, 0x11 }, 0, .vex_256, .avx },
981 .{ .vmovapd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x28 }, 0, .vex_128_wig, .avx },
982 .{ .vmovapd, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x66, 0x0f, 0x29 }, 0, .vex_128_wig, .avx },
983 .{ .vmovapd, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x28 }, 0, .vex_256_wig, .avx },
984 .{ .vmovapd, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x66, 0x0f, 0x29 }, 0, .vex_256_wig, .avx },
1016985
1017 .{ .vpextrw, .mri, &.{ .r32, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x15 }, 0, .vex_128, .avx },
1018 .{ .vpextrw, .mri, &.{ .r64, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x15 }, 0, .vex_128_long, .avx },
1019 .{ .vpextrw, .mri, &.{ .r32_m16, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x15 }, 0, .vex_128, .avx },
1020 .{ .vpextrw, .mri, &.{ .r64_m16, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x15 }, 0, .vex_128_long, .avx },
986 .{ .vmovaps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x28 }, 0, .vex_128_wig, .avx },
987 .{ .vmovaps, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x0f, 0x29 }, 0, .vex_128_wig, .avx },
988 .{ .vmovaps, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x0f, 0x28 }, 0, .vex_256_wig, .avx },
989 .{ .vmovaps, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x0f, 0x29 }, 0, .vex_256_wig, .avx },
1021990
1022 .{ .vpinsrw, .rvmi, &.{ .xmm, .xmm, .r32_m16, .imm8 }, &.{ 0x66, 0x0f, 0xc4 }, 0, .vex_128, .avx },
991 .{ .vmovddup, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x12 }, 0, .vex_128_wig, .avx },
992 .{ .vmovddup, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0xf2, 0x0f, 0x12 }, 0, .vex_256_wig, .avx },
1023993
1024 .{ .vpsrld, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd2 }, 0, .vex_128, .avx },
1025 .{ .vpsrld, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x72 }, 2, .vex_128, .avx },
994 .{ .vmovsd, .rvm, &.{ .xmm, .xmm, .xmm }, &.{ 0xf2, 0x0f, 0x10 }, 0, .vex_lig_wig, .avx },
995 .{ .vmovsd, .rm, &.{ .xmm, .m64 }, &.{ 0xf2, 0x0f, 0x10 }, 0, .vex_lig_wig, .avx },
996 .{ .vmovsd, .mvr, &.{ .xmm, .xmm, .xmm }, &.{ 0xf2, 0x0f, 0x11 }, 0, .vex_lig_wig, .avx },
997 .{ .vmovsd, .mr, &.{ .m64, .xmm }, &.{ 0xf2, 0x0f, 0x11 }, 0, .vex_lig_wig, .avx },
1026998
1027 .{ .vpsrlq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd3 }, 0, .vex_128, .avx },
1028 .{ .vpsrlq, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x73 }, 2, .vex_128, .avx },
999 .{ .vmovshdup, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0xf3, 0x0f, 0x16 }, 0, .vex_128_wig, .avx },
1000 .{ .vmovshdup, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0xf3, 0x0f, 0x16 }, 0, .vex_256_wig, .avx },
10291001
1030 .{ .vpsrlw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd1 }, 0, .vex_128, .avx },
1031 .{ .vpsrlw, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 2, .vex_128, .avx },
1002 .{ .vmovsldup, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0xf3, 0x0f, 0x12 }, 0, .vex_128_wig, .avx },
1003 .{ .vmovsldup, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0xf3, 0x0f, 0x12 }, 0, .vex_256_wig, .avx },
10321004
1033 .{ .vpunpckhbw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x68 }, 0, .vex_128, .avx },
1005 .{ .vmovss, .rvm, &.{ .xmm, .xmm, .xmm }, &.{ 0xf3, 0x0f, 0x10 }, 0, .vex_lig_wig, .avx },
1006 .{ .vmovss, .rm, &.{ .xmm, .m32 }, &.{ 0xf3, 0x0f, 0x10 }, 0, .vex_lig_wig, .avx },
1007 .{ .vmovss, .mvr, &.{ .xmm, .xmm, .xmm }, &.{ 0xf3, 0x0f, 0x11 }, 0, .vex_lig_wig, .avx },
1008 .{ .vmovss, .mr, &.{ .m32, .xmm }, &.{ 0xf3, 0x0f, 0x11 }, 0, .vex_lig_wig, .avx },
10341009
1035 .{ .vpunpckhdq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6a }, 0, .vex_128, .avx },
1010 .{ .vmovupd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x10 }, 0, .vex_128_wig, .avx },
1011 .{ .vmovupd, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x66, 0x0f, 0x11 }, 0, .vex_128_wig, .avx },
1012 .{ .vmovupd, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x10 }, 0, .vex_256_wig, .avx },
1013 .{ .vmovupd, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x66, 0x0f, 0x11 }, 0, .vex_256_wig, .avx },
10361014
1037 .{ .vpunpckhqdq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6d }, 0, .vex_128, .avx },
1015 .{ .vmovups, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x10 }, 0, .vex_128_wig, .avx },
1016 .{ .vmovups, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x0f, 0x11 }, 0, .vex_128_wig, .avx },
1017 .{ .vmovups, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x0f, 0x10 }, 0, .vex_256_wig, .avx },
1018 .{ .vmovups, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x0f, 0x11 }, 0, .vex_256_wig, .avx },
10381019
1039 .{ .vpunpckhwd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x69 }, 0, .vex_128, .avx },
1020 .{ .vpextrw, .rmi, &.{ .r32, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x15 }, 0, .vex_128_wig, .avx },
1021 .{ .vpextrw, .mri, &.{ .r32_m16, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x15 }, 0, .vex_128_wig, .avx },
10401022
1041 .{ .vpunpcklbw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x60 }, 0, .vex_128, .avx },
1023 .{ .vpinsrw, .rvmi, &.{ .xmm, .xmm, .r32_m16, .imm8 }, &.{ 0x66, 0x0f, 0xc4 }, 0, .vex_128_wig, .avx },
10421024
1043 .{ .vpunpckldq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x62 }, 0, .vex_128, .avx },
1025 .{ .vpsrlw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd1 }, 0, .vex_128_wig, .avx },
1026 .{ .vpsrlw, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 2, .vex_128_wig, .avx },
1027 .{ .vpsrld, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd2 }, 0, .vex_128_wig, .avx },
1028 .{ .vpsrld, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x72 }, 2, .vex_128_wig, .avx },
1029 .{ .vpsrlq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd3 }, 0, .vex_128_wig, .avx },
1030 .{ .vpsrlq, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x73 }, 2, .vex_128_wig, .avx },
10441031
1045 .{ .vpunpcklqdq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6c }, 0, .vex_128, .avx },
1032 .{ .vpunpckhbw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x68 }, 0, .vex_128_wig, .avx },
1033 .{ .vpunpckhwd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x69 }, 0, .vex_128_wig, .avx },
1034 .{ .vpunpckhdq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6a }, 0, .vex_128_wig, .avx },
1035 .{ .vpunpckhqdq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6d }, 0, .vex_128_wig, .avx },
10461036
1047 .{ .vpunpcklwd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x61 }, 0, .vex_128, .avx },
1037 .{ .vpunpcklbw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x60 }, 0, .vex_128_wig, .avx },
1038 .{ .vpunpcklwd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x61 }, 0, .vex_128_wig, .avx },
1039 .{ .vpunpckldq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x62 }, 0, .vex_128_wig, .avx },
1040 .{ .vpunpcklqdq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6c }, 0, .vex_128_wig, .avx },
10481041
10491042 // F16C
1050 .{ .vcvtph2ps, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0x66, 0x0f, 0x38, 0x13 }, 0, .vex_128, .f16c },
1043 .{ .vcvtph2ps, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0x66, 0x0f, 0x38, 0x13 }, 0, .vex_128_w0, .f16c },
1044 .{ .vcvtph2ps, .rm, &.{ .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x13 }, 0, .vex_256_w0, .f16c },
10511045
1052 .{ .vcvtps2ph, .mri, &.{ .xmm_m64, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x1d }, 0, .vex_128, .f16c },
1046 .{ .vcvtps2ph, .mri, &.{ .xmm_m64, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x1d }, 0, .vex_128_w0, .f16c },
1047 .{ .vcvtps2ph, .mri, &.{ .xmm_m128, .ymm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x1d }, 0, .vex_256_w0, .f16c },
10531048
10541049 // FMA
1055 .{ .vfmadd132pd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x98 }, 0, .vex_128_long, .fma },
1056 .{ .vfmadd132pd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0x98 }, 0, .vex_256_long, .fma },
1057 .{ .vfmadd213pd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xa8 }, 0, .vex_128_long, .fma },
1058 .{ .vfmadd213pd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0xa8 }, 0, .vex_256_long, .fma },
1059 .{ .vfmadd231pd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xb8 }, 0, .vex_128_long, .fma },
1060 .{ .vfmadd231pd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0xb8 }, 0, .vex_256_long, .fma },
1061
1062 .{ .vfmadd132ps, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x98 }, 0, .vex_128, .fma },
1063 .{ .vfmadd132ps, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0x98 }, 0, .vex_256, .fma },
1064 .{ .vfmadd213ps, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xa8 }, 0, .vex_128, .fma },
1065 .{ .vfmadd213ps, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0xa8 }, 0, .vex_256, .fma },
1066 .{ .vfmadd231ps, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xb8 }, 0, .vex_128, .fma },
1067 .{ .vfmadd231ps, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0xb8 }, 0, .vex_256, .fma },
1068
1069 .{ .vfmadd132sd, .rvm, &.{ .xmm, .xmm, .xmm_m64 }, &.{ 0x66, 0x0f, 0x38, 0x99 }, 0, .vex_128_long, .fma },
1070 .{ .vfmadd213sd, .rvm, &.{ .xmm, .xmm, .xmm_m64 }, &.{ 0x66, 0x0f, 0x38, 0xa9 }, 0, .vex_128_long, .fma },
1071 .{ .vfmadd231sd, .rvm, &.{ .xmm, .xmm, .xmm_m64 }, &.{ 0x66, 0x0f, 0x38, 0xb9 }, 0, .vex_128_long, .fma },
1072
1073 .{ .vfmadd132ss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0x66, 0x0f, 0x38, 0x99 }, 0, .vex_128, .fma },
1074 .{ .vfmadd213ss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0x66, 0x0f, 0x38, 0xa9 }, 0, .vex_128, .fma },
1075 .{ .vfmadd231ss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0x66, 0x0f, 0x38, 0xb9 }, 0, .vex_128, .fma },
1050 .{ .vfmadd132pd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x98 }, 0, .vex_128_w1, .fma },
1051 .{ .vfmadd213pd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xa8 }, 0, .vex_128_w1, .fma },
1052 .{ .vfmadd231pd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xb8 }, 0, .vex_128_w1, .fma },
1053 .{ .vfmadd132pd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0x98 }, 0, .vex_256_w1, .fma },
1054 .{ .vfmadd213pd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0xa8 }, 0, .vex_256_w1, .fma },
1055 .{ .vfmadd231pd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0xb8 }, 0, .vex_256_w1, .fma },
1056
1057 .{ .vfmadd132ps, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x98 }, 0, .vex_128_w0, .fma },
1058 .{ .vfmadd213ps, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xa8 }, 0, .vex_128_w0, .fma },
1059 .{ .vfmadd231ps, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xb8 }, 0, .vex_128_w0, .fma },
1060 .{ .vfmadd132ps, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0x98 }, 0, .vex_256_w0, .fma },
1061 .{ .vfmadd213ps, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0xa8 }, 0, .vex_256_w0, .fma },
1062 .{ .vfmadd231ps, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0xb8 }, 0, .vex_256_w0, .fma },
1063
1064 .{ .vfmadd132sd, .rvm, &.{ .xmm, .xmm, .xmm_m64 }, &.{ 0x66, 0x0f, 0x38, 0x99 }, 0, .vex_lig_w1, .fma },
1065 .{ .vfmadd213sd, .rvm, &.{ .xmm, .xmm, .xmm_m64 }, &.{ 0x66, 0x0f, 0x38, 0xa9 }, 0, .vex_lig_w1, .fma },
1066 .{ .vfmadd231sd, .rvm, &.{ .xmm, .xmm, .xmm_m64 }, &.{ 0x66, 0x0f, 0x38, 0xb9 }, 0, .vex_lig_w1, .fma },
1067
1068 .{ .vfmadd132ss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0x66, 0x0f, 0x38, 0x99 }, 0, .vex_lig_w0, .fma },
1069 .{ .vfmadd213ss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0x66, 0x0f, 0x38, 0xa9 }, 0, .vex_lig_w0, .fma },
1070 .{ .vfmadd231ss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0x66, 0x0f, 0x38, 0xb9 }, 0, .vex_lig_w0, .fma },
1071
1072 // AVX2
1073 .{ .vpsrlw, .rvm, &.{ .ymm, .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd1 }, 0, .vex_256_wig, .avx2 },
1074 .{ .vpsrlw, .vmi, &.{ .ymm, .ymm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 2, .vex_256_wig, .avx2 },
1075 .{ .vpsrld, .rvm, &.{ .ymm, .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd2 }, 0, .vex_256_wig, .avx2 },
1076 .{ .vpsrld, .vmi, &.{ .ymm, .ymm, .imm8 }, &.{ 0x66, 0x0f, 0x72 }, 2, .vex_256_wig, .avx2 },
1077 .{ .vpsrlq, .rvm, &.{ .ymm, .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd3 }, 0, .vex_256_wig, .avx2 },
1078 .{ .vpsrlq, .vmi, &.{ .ymm, .ymm, .imm8 }, &.{ 0x66, 0x0f, 0x73 }, 2, .vex_256_wig, .avx2 },
1079
1080 .{ .vpunpckhbw, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x68 }, 0, .vex_256_wig, .avx2 },
1081 .{ .vpunpckhwd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x69 }, 0, .vex_256_wig, .avx2 },
1082 .{ .vpunpckhdq, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x6a }, 0, .vex_256_wig, .avx2 },
1083 .{ .vpunpckhqdq, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x6d }, 0, .vex_256_wig, .avx2 },
1084
1085 .{ .vpunpcklbw, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x60 }, 0, .vex_256_wig, .avx2 },
1086 .{ .vpunpcklwd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x61 }, 0, .vex_256_wig, .avx2 },
1087 .{ .vpunpckldq, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x62 }, 0, .vex_256_wig, .avx2 },
1088 .{ .vpunpcklqdq, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x6c }, 0, .vex_256_wig, .avx2 },
10761089};
10771090// zig fmt: on
test/behavior/floatop.zig+2-1
......@@ -52,7 +52,8 @@ fn testFloatComparisons() !void {
5252}
5353
5454test "different sized float comparisons" {
55 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
55 if (builtin.zig_backend == .stage2_x86_64 and
56 !comptime std.Target.x86.featureSetHas(builtin.cpu.features, .f16c)) return error.SkipZigTest; // TODO
5657 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
5758 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
5859 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO