Commit 05580b9453e4ae2d9b62fe4178651937d8b73989 | zig

author	Jacob Young <jacobly@ziglang.org> 2023-05-07 03:14:31-04:00
committer	Jacob Young <jacobly@ziglang.org> 2023-05-08 07:36:20-04:00
log	05580b9453e4ae2d9b62fe4178651937d8b73989
tree	b04b981c4a17c1df0ba17d9d0c703e21b220b9e0
parent	1c53f0a6b0b1866663346c473da310203a317e90

x86_64: implement float cast from `f16` to `f64`

7 files changed, 292 insertions(+), 211 deletions(-)

src
- arch
  - x86_64
    CodeGen.zig
    Encoding.zig
    Lower.zig
    Mir.zig
    encoder.zig
    encodings.zig
test
- behavior
  - floatop.zig

src/arch/x86_64/CodeGen.zig+67-28

 @@ -2287,26 +2287,46 @@ fn airFptrunc(self: *Self, inst: Air.Inst.Index) !void {
         src_mcv
     else
         try self.copyToRegisterWithInstTracking(inst, dst_ty, src_mcv);
-    const dst_lock = self.register_manager.lockReg(dst_mcv.register);
+    const dst_reg = dst_mcv.getReg().?.to128();
+    const dst_lock = self.register_manager.lockReg(dst_reg);
     defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
-    if (src_bits == 32 and dst_bits == 16 and self.hasFeature(.f16c))
+    if (dst_bits == 16 and self.hasFeature(.f16c)) {
-        try self.asmRegisterRegisterImmediate(
+        switch (src_bits) {
-            .vcvtps2ph,
+            32 => {
-            dst_mcv.register,
+                const mat_src_reg = if (src_mcv.isRegister())
-            if (src_mcv.isRegister()) src_mcv.getReg().? else src_reg: {
+                    src_mcv.getReg().?
-                const src_reg = dst_mcv.register;
+                else
-                try self.genSetReg(src_reg, src_ty, src_mcv);
+                    try self.copyToTmpRegister(src_ty, src_mcv);
-                break :src_reg src_reg;
+                try self.asmRegisterRegisterImmediate(
+                    .vcvtps2ph,
+                    dst_reg,
+                    mat_src_reg.to128(),
+                    Immediate.u(0b1_00),
+                );
             },
-            Immediate.u(0b1_00),
+            else => return self.fail("TODO implement airFptrunc from {} to {}", .{
-        )
+                src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
-    else if (src_bits == 64 and dst_bits == 32)
+            }),
-        try self.genBinOpMir(.cvtsd2ss, src_ty, dst_mcv, src_mcv)
+        }
-    else
+    } else if (src_bits == 64 and dst_bits == 32) {
-        return self.fail("TODO implement airFptrunc from {} to {}", .{
+        if (self.hasFeature(.avx)) if (src_mcv.isRegister()) try self.asmRegisterRegisterRegister(
-            src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
+            .vcvtsd2ss,
-        });
+            dst_reg,
+            dst_reg,
+            src_mcv.getReg().?.to128(),
+        ) else try self.asmRegisterRegisterMemory(
+            .vcvtsd2ss,
+            dst_reg,
+            dst_reg,
+            src_mcv.mem(.qword),
+        ) else if (src_mcv.isRegister())
+            try self.asmRegisterRegister(.cvtsd2ss, dst_reg, src_mcv.getReg().?.to128())
+        else
+            try self.asmRegisterMemory(.cvtsd2ss, dst_reg, src_mcv.mem(.qword));
+    } else return self.fail("TODO implement airFptrunc from {} to {}", .{
+        src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
+    });
     return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });
 }
 @@ -2322,22 +2342,41 @@ fn airFpext(self: *Self, inst: Air.Inst.Index) !void {
         src_mcv
     else
         try self.copyToRegisterWithInstTracking(inst, dst_ty, src_mcv);
-    const dst_lock = self.register_manager.lockReg(dst_mcv.register);
+    const dst_reg = dst_mcv.getReg().?.to128();
+    const dst_lock = self.register_manager.lockReg(dst_reg);
     defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
-    try self.genBinOpMir(
+    if (src_bits == 16 and self.hasFeature(.f16c)) {
-        if (src_bits == 16 and dst_bits == 32 and self.hasFeature(.f16c))
+        const mat_src_reg = if (src_mcv.isRegister())
-            .vcvtph2ps
+            src_mcv.getReg().?
-        else if (src_bits == 32 and dst_bits == 64)
-            .cvtss2sd
         else
-            return self.fail("TODO implement airFpext from {} to {}", .{
+            try self.copyToTmpRegister(src_ty, src_mcv);
+        try self.asmRegisterRegister(.vcvtph2ps, dst_reg, mat_src_reg.to128());
+        switch (dst_bits) {
+            32 => {},
+            64 => try self.asmRegisterRegisterRegister(.vcvtss2sd, dst_reg, dst_reg, dst_reg),
+            else => return self.fail("TODO implement airFpext from {} to {}", .{
                 src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
             }),
-        src_ty,
+        }
-        dst_mcv,
+    } else if (src_bits == 32 and dst_bits == 64) {
-        src_mcv,
+        if (self.hasFeature(.avx)) if (src_mcv.isRegister()) try self.asmRegisterRegisterRegister(
-    );
+            .vcvtss2sd,
+            dst_reg,
+            dst_reg,
+            src_mcv.getReg().?.to128(),
+        ) else try self.asmRegisterRegisterMemory(
+            .vcvtss2sd,
+            dst_reg,
+            dst_reg,
+            src_mcv.mem(.dword),
+        ) else if (src_mcv.isRegister())
+            try self.asmRegisterRegister(.cvtss2sd, dst_reg, src_mcv.getReg().?.to128())
+        else
+            try self.asmRegisterMemory(.cvtss2sd, dst_reg, src_mcv.mem(.dword));
+    } else return self.fail("TODO implement airFpext from {} to {}", .{
+        src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
+    });
     return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });
 }

src/arch/x86_64/Encoding.zig+96-69

...	@@ -89,30 +89,13 @@ pub fn findByOpcode(opc: []const u8, prefixes: struct {	...	@@ -89,30 +89,13 @@ pub fn findByOpcode(opc: []const u8, prefixes: struct {
89	if (modrm_ext) \|ext\| if (ext != data.modrm_ext) continue;	89	if (modrm_ext) \|ext\| if (ext != data.modrm_ext) continue;
90	if (!std.mem.eql(u8, opc, enc.opcode())) continue;	90	if (!std.mem.eql(u8, opc, enc.opcode())) continue;
91	if (prefixes.rex.w) {	91	if (prefixes.rex.w) {
92	switch (data.mode) {	92	if (!data.mode.isLong()) continue;
93	.none, .short, .rex, .rex_short, .vex_128, .vex_256 => continue,
94	.long, .vex_128_long, .vex_256_long => {},
95	}
96	} else if (prefixes.rex.present and !prefixes.rex.isSet()) {	93	} else if (prefixes.rex.present and !prefixes.rex.isSet()) {
97	switch (data.mode) {	94	if (!data.mode.isRex()) continue;
98	.rex, .rex_short => {},
99	else => continue,
100	}
101	} else if (prefixes.legacy.prefix_66) {	95	} else if (prefixes.legacy.prefix_66) {
102	switch (data.mode) {	96	if (!data.mode.isShort()) continue;
103	.short, .rex_short => {},
104	.none, .rex, .vex_128, .vex_256 => continue,
105	.long, .vex_128_long, .vex_256_long => continue,
106	}
107	} else {	97	} else {
108	switch (data.mode) {	98	if (data.mode.isShort()) continue;
109	.none => switch (data.mode) {
110	.short, .rex_short => continue,
111	.none, .rex, .vex_128, .vex_256 => {},
112	.long, .vex_128_long, .vex_256_long => {},
113	},
114	else => continue,
115	}
116	}	99	}
117	return enc;	100	return enc;
118	};	101	};
...	@@ -148,50 +131,39 @@ pub fn format(	...	@@ -148,50 +131,39 @@ pub fn format(
148	_ = fmt;	131	_ = fmt;
149		132
150	var opc = encoding.opcode();	133	var opc = encoding.opcode();
151	switch (encoding.data.mode) {	134	if (encoding.data.mode.isVex()) {
152	else => {},	135	try writer.writeAll("VEX.");
153	.long => try writer.writeAll("REX.W + "),	136
154	.vex_128, .vex_128_long, .vex_256, .vex_256_long => {	137	try writer.writeAll(switch (encoding.data.mode) {
155	try writer.writeAll("VEX.");	138	.vex_128_w0, .vex_128_w1, .vex_128_wig => "128",
156		139	.vex_256_w0, .vex_256_w1, .vex_256_wig => "256",
157	switch (encoding.data.mode) {	140	.vex_lig_w0, .vex_lig_w1, .vex_lig_wig => "LIG",
158	.vex_128, .vex_128_long => try writer.writeAll("128"),	141	.vex_lz_w0, .vex_lz_w1, .vex_lz_wig => "LZ",
159	.vex_256, .vex_256_long => try writer.writeAll("256"),	142	else => unreachable,
160	else => unreachable,	143	});
161	}
162
163	switch (opc[0]) {
164	else => {},
165	0x66, 0xf3, 0xf2 => {
166	try writer.print(".{X:0>2}", .{opc[0]});
167	opc = opc[1..];
168	},
169	}
170		144
171	try writer.print(".{X:0>2}", .{opc[0]});	145	switch (opc[0]) {
172	opc = opc[1..];	146	else => {},
		147	0x66, 0xf3, 0xf2 => {
		148	try writer.print(".{X:0>2}", .{opc[0]});
		149	opc = opc[1..];
		150	},
		151	}
173		152
174	switch (opc[0]) {	153	try writer.print(".{}", .{std.fmt.fmtSliceHexUpper(opc[0 .. opc.len - 1])});
175	else => {},	154	opc = opc[opc.len - 1 ..];
176	0x38, 0x3A => {
177	try writer.print("{X:0>2}", .{opc[0]});
178	opc = opc[1..];
179	},
180	}
181		155
182	try writer.writeByte('.');	156	try writer.writeAll(".W");
183	try writer.writeAll(switch (encoding.data.mode) {	157	try writer.writeAll(switch (encoding.data.mode) {
184	.vex_128, .vex_256 => "W0",	158	.vex_128_w0, .vex_256_w0, .vex_lig_w0, .vex_lz_w0 => "0",
185	.vex_128_long, .vex_256_long => "W1",	159	.vex_128_w1, .vex_256_w1, .vex_lig_w1, .vex_lz_w1 => "1",
186	else => unreachable,	160	.vex_128_wig, .vex_256_wig, .vex_lig_wig, .vex_lz_wig => "IG",
187	});	161	else => unreachable,
188	try writer.writeByte(' ');	162	});
189	},
190	}
191		163
192	for (opc) \|byte\| {	164	try writer.writeByte(' ');
193	try writer.print("{x:0>2} ", .{byte});	165	} else if (encoding.data.mode.isLong()) try writer.writeAll("REX.W + ");
194	}	166	for (opc) \|byte\| try writer.print("{x:0>2} ", .{byte});
195		167
196	switch (encoding.data.op_en) {	168	switch (encoding.data.op_en) {
197	.np, .fd, .td, .i, .zi, .d => {},	169	.np, .fd, .td, .i, .zi, .d => {},
...	@@ -332,6 +304,7 @@ pub const Mnemonic = enum {	...	@@ -332,6 +304,7 @@ pub const Mnemonic = enum {
332	// SSE4.1	304	// SSE4.1
333	roundsd, roundss,	305	roundsd, roundss,
334	// AVX	306	// AVX
		307	vcvtsd2ss, vcvtsi2sd, vcvtsi2ss, vcvtss2sd,
335	vmovapd, vmovaps,	308	vmovapd, vmovaps,
336	vmovddup,	309	vmovddup,
337	vmovsd,	310	vmovsd,
...	@@ -629,20 +602,74 @@ pub const Op = enum {	...	@@ -629,20 +602,74 @@ pub const Op = enum {
629	};	602	};
630		603
631	pub const Mode = enum {	604	pub const Mode = enum {
		605	// zig fmt: off
632	none,	606	none,
633	short,	607	short, long,
634	long,	608	rex, rex_short,
635	rex,	609	vex_128_w0, vex_128_w1, vex_128_wig,
636	rex_short,	610	vex_256_w0, vex_256_w1, vex_256_wig,
637	vex_128,	611	vex_lig_w0, vex_lig_w1, vex_lig_wig,
638	vex_128_long,	612	vex_lz_w0, vex_lz_w1, vex_lz_wig,
639	vex_256,	613	// zig fmt: on
640	vex_256_long,	614
		615	pub fn isShort(mode: Mode) bool {
		616	return switch (mode) {
		617	.short, .rex_short => true,
		618	else => false,
		619	};
		620	}
		621
		622	pub fn isLong(mode: Mode) bool {
		623	return switch (mode) {
		624	.long,
		625	.vex_128_w1,
		626	.vex_256_w1,
		627	.vex_lig_w1,
		628	.vex_lz_w1,
		629	=> true,
		630	else => false,
		631	};
		632	}
		633
		634	pub fn isRex(mode: Mode) bool {
		635	return switch (mode) {
		636	else => false,
		637	.rex, .rex_short => true,
		638	};
		639	}
		640
		641	pub fn isVex(mode: Mode) bool {
		642	return switch (mode) {
		643	// zig fmt: off
		644	else => false,
		645	.vex_128_w0, .vex_128_w1, .vex_128_wig,
		646	.vex_256_w0, .vex_256_w1, .vex_256_wig,
		647	.vex_lig_w0, .vex_lig_w1, .vex_lig_wig,
		648	.vex_lz_w0, .vex_lz_w1, .vex_lz_wig,
		649	=> true,
		650	// zig fmt: on
		651	};
		652	}
		653
		654	pub fn isVecLong(mode: Mode) bool {
		655	return switch (mode) {
		656	// zig fmt: off
		657	else => unreachable,
		658	.vex_128_w0, .vex_128_w1, .vex_128_wig,
		659	.vex_lig_w0, .vex_lig_w1, .vex_lig_wig,
		660	.vex_lz_w0, .vex_lz_w1, .vex_lz_wig,
		661	=> false,
		662	.vex_256_w0, .vex_256_w1, .vex_256_wig,
		663	=> true,
		664	// zig fmt: on
		665	};
		666	}
641	};	667	};
642		668
643	pub const Feature = enum {	669	pub const Feature = enum {
644	none,	670	none,
645	avx,	671	avx,
		672	avx2,
646	f16c,	673	f16c,
647	fma,	674	fma,
648	sse,	675	sse,

src/arch/x86_64/Lower.zig+4

 @@ -184,6 +184,10 @@ pub fn lowerMir(lower: *Lower, index: Mir.Inst.Index) Error!struct {
         .roundsd,
         .roundss,
+        .vcvtsd2ss,
+        .vcvtsi2sd,
+        .vcvtsi2ss,
+        .vcvtss2sd,
         .vmovapd,
         .vmovaps,
         .vmovddup,

src/arch/x86_64/Mir.zig+8

...	@@ -282,6 +282,14 @@ pub const Inst = struct {	...	@@ -282,6 +282,14 @@ pub const Inst = struct {
282	/// Round scalar single-precision floating-point values	282	/// Round scalar single-precision floating-point values
283	roundss,	283	roundss,
284		284
		285	/// Convert scalar double-precision floating-point value to scalar single-precision floating-point value
		286	vcvtsd2ss,
		287	/// Convert doubleword integer to scalar double-precision floating-point value
		288	vcvtsi2sd,
		289	/// Convert doubleword integer to scalar single-precision floating-point value
		290	vcvtsi2ss,
		291	/// Convert scalar single-precision floating-point value to scalar double-precision floating-point value
		292	vcvtss2sd,
285	/// Move aligned packed double-precision floating-point values	293	/// Move aligned packed double-precision floating-point values
286	vmovapd,	294	vmovapd,
287	/// Move aligned packed single-precision floating-point values	295	/// Move aligned packed single-precision floating-point values

src/arch/x86_64/encoder.zig+11-22

 @@ -206,18 +206,15 @@ pub const Instruction = struct {
         const enc = inst.encoding;
         const data = enc.data;
-        switch (data.mode) {
+        if (data.mode.isVex()) {
-            .none, .short, .long, .rex, .rex_short => {
+            try inst.encodeVexPrefix(encoder);
-                try inst.encodeLegacyPrefixes(encoder);
+            const opc = inst.encoding.opcode();
-                try inst.encodeMandatoryPrefix(encoder);
+            try encoder.opcode_1byte(opc[opc.len - 1]);
-                try inst.encodeRexPrefix(encoder);
+        } else {
-                try inst.encodeOpcode(encoder);
+            try inst.encodeLegacyPrefixes(encoder);
-            },
+            try inst.encodeMandatoryPrefix(encoder);
-            .vex_128, .vex_128_long, .vex_256, .vex_256_long => {
+            try inst.encodeRexPrefix(encoder);
-                try inst.encodeVexPrefix(encoder);
+            try inst.encodeOpcode(encoder);
-                const opc = inst.encoding.opcode();
-                try encoder.opcode_1byte(opc[opc.len - 1]);
-            },
         }
         switch (data.op_en) {
 @@ -365,11 +362,7 @@ pub const Instruction = struct {
         var vex = Vex{};
-        vex.w = switch (inst.encoding.data.mode) {
+        vex.w = inst.encoding.data.mode.isLong();
-            .vex_128, .vex_256 => false,
-            .vex_128_long, .vex_256_long => true,
-            else => unreachable,
-        };
         switch (op_en) {
             .np, .i, .zi, .fd, .td, .d => {},
 @@ -395,11 +388,7 @@ pub const Instruction = struct {
             },
         }
-        vex.l = switch (inst.encoding.data.mode) {
+        vex.l = inst.encoding.data.mode.isVecLong();
-            .vex_128, .vex_128_long => false,
-            .vex_256, .vex_256_long => true,
-            else => unreachable,
-        };
         vex.p = if (mand_pre) |mand| switch (mand) {
             0x66 => .@"66",

src/arch/x86_64/encodings.zig+104-91

...	@@ -918,7 +918,6 @@ pub const table = [_]Entry{	...	@@ -918,7 +918,6 @@ pub const table = [_]Entry{
918	.{ .orpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x56 }, 0, .none, .sse2 },	918	.{ .orpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x56 }, 0, .none, .sse2 },
919		919
920	.{ .pextrw, .rmi, &.{ .r32, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0xc5 }, 0, .none, .sse2 },	920	.{ .pextrw, .rmi, &.{ .r32, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0xc5 }, 0, .none, .sse2 },
921	.{ .pextrw, .rmi, &.{ .r64, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0xc5 }, 0, .long, .sse2 },
922		921
923	.{ .pinsrw, .rmi, &.{ .xmm, .r32_m16, .imm8 }, &.{ 0x66, 0x0f, 0xc4 }, 0, .none, .sse2 },	922	.{ .pinsrw, .rmi, &.{ .xmm, .r32_m16, .imm8 }, &.{ 0x66, 0x0f, 0xc4 }, 0, .none, .sse2 },
924		923
...	@@ -926,31 +925,23 @@ pub const table = [_]Entry{	...	@@ -926,31 +925,23 @@ pub const table = [_]Entry{
926		925
927	.{ .pshuflw, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0xf2, 0x0f, 0x70 }, 0, .none, .sse2 },	926	.{ .pshuflw, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0xf2, 0x0f, 0x70 }, 0, .none, .sse2 },
928		927
		928	.{ .psrlw, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd1 }, 0, .none, .sse2 },
		929	.{ .psrlw, .mi, &.{ .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 2, .none, .sse2 },
929	.{ .psrld, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd2 }, 0, .none, .sse2 },	930	.{ .psrld, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd2 }, 0, .none, .sse2 },
930	.{ .psrld, .mi, &.{ .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x72 }, 2, .none, .sse2 },	931	.{ .psrld, .mi, &.{ .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x72 }, 2, .none, .sse2 },
931
932	.{ .psrlq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd3 }, 0, .none, .sse2 },	932	.{ .psrlq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd3 }, 0, .none, .sse2 },
933	.{ .psrlq, .mi, &.{ .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x73 }, 2, .none, .sse2 },	933	.{ .psrlq, .mi, &.{ .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x73 }, 2, .none, .sse2 },
934		934
935	.{ .psrlw, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd1 }, 0, .none, .sse2 },	935	.{ .punpckhbw, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x68 }, 0, .none, .sse2 },
936	.{ .psrlw, .mi, &.{ .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 2, .none, .sse2 },	936	.{ .punpckhwd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x69 }, 0, .none, .sse2 },
937		937	.{ .punpckhdq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6a }, 0, .none, .sse2 },
938	.{ .punpckhbw, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x68 }, 0, .none, .sse2 },
939
940	.{ .punpckhdq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6a }, 0, .none, .sse2 },
941
942	.{ .punpckhqdq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6d }, 0, .none, .sse2 },	938	.{ .punpckhqdq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6d }, 0, .none, .sse2 },
943		939
944	.{ .punpckhwd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x69 }, 0, .none, .sse2 },	940	.{ .punpcklbw, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x60 }, 0, .none, .sse2 },
945		941	.{ .punpcklwd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x61 }, 0, .none, .sse2 },
946	.{ .punpcklbw, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x60 }, 0, .none, .sse2 },	942	.{ .punpckldq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x62 }, 0, .none, .sse2 },
947
948	.{ .punpckldq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x62 }, 0, .none, .sse2 },
949
950	.{ .punpcklqdq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6c }, 0, .none, .sse2 },	943	.{ .punpcklqdq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6c }, 0, .none, .sse2 },
951		944
952	.{ .punpcklwd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x61 }, 0, .none, .sse2 },
953
954	.{ .sqrtpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x51 }, 0, .none, .sse2 },	945	.{ .sqrtpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x51 }, 0, .none, .sse2 },
955	.{ .sqrtsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x51 }, 0, .none, .sse2 },	946	.{ .sqrtsd, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x51 }, 0, .none, .sse2 },
956		947
...	@@ -972,106 +963,128 @@ pub const table = [_]Entry{	...	@@ -972,106 +963,128 @@ pub const table = [_]Entry{
972		963
973	// SSE4.1	964	// SSE4.1
974	.{ .pextrw, .mri, &.{ .r32_m16, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x15 }, 0, .none, .sse4_1 },	965	.{ .pextrw, .mri, &.{ .r32_m16, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x15 }, 0, .none, .sse4_1 },
975	.{ .pextrw, .mri, &.{ .r64_m16, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x15 }, 0, .long, .sse4_1 },
976		966
977	.{ .roundss, .rmi, &.{ .xmm, .xmm_m32, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0a }, 0, .none, .sse4_1 },	967	.{ .roundss, .rmi, &.{ .xmm, .xmm_m32, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0a }, 0, .none, .sse4_1 },
978	.{ .roundsd, .rmi, &.{ .xmm, .xmm_m64, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0b }, 0, .none, .sse4_1 },	968	.{ .roundsd, .rmi, &.{ .xmm, .xmm_m64, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x0b }, 0, .none, .sse4_1 },
979		969
980	// AVX	970	// AVX
981	.{ .vmovapd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x28 }, 0, .vex_128, .avx },	971	.{ .vcvtsd2ss, .rvm, &.{ .xmm, .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x5a }, 0, .vex_lig_wig, .avx },
982	.{ .vmovapd, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x66, 0x0f, 0x29 }, 0, .vex_128, .avx },
983	.{ .vmovapd, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x28 }, 0, .vex_256, .avx },
984	.{ .vmovapd, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x66, 0x0f, 0x29 }, 0, .vex_256, .avx },
985
986	.{ .vmovaps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x28 }, 0, .vex_128, .avx },
987	.{ .vmovaps, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x0f, 0x29 }, 0, .vex_128, .avx },
988	.{ .vmovaps, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x0f, 0x28 }, 0, .vex_256, .avx },
989	.{ .vmovaps, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x0f, 0x29 }, 0, .vex_256, .avx },
990
991	.{ .vmovddup, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x12 }, 0, .vex_128, .avx },
992
993	.{ .vmovsd, .rvm, &.{ .xmm, .xmm, .xmm }, &.{ 0xf2, 0x0f, 0x10 }, 0, .vex_128, .avx },
994	.{ .vmovsd, .rm, &.{ .xmm, .m64 }, &.{ 0xf2, 0x0f, 0x10 }, 0, .vex_128, .avx },
995	.{ .vmovsd, .mvr, &.{ .xmm, .xmm, .xmm }, &.{ 0xf2, 0x0f, 0x11 }, 0, .vex_128, .avx },
996	.{ .vmovsd, .mr, &.{ .m64, .xmm }, &.{ 0xf2, 0x0f, 0x11 }, 0, .vex_128, .avx },
997
998	.{ .vmovshdup, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0xf3, 0x0f, 0x16 }, 0, .vex_128, .avx },
999		972
1000	.{ .vmovsldup, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0xf3, 0x0f, 0x12 }, 0, .vex_128, .avx },	973	.{ .vcvtsi2sd, .rvm, &.{ .xmm, .xmm, .rm32 }, &.{ 0xf2, 0x0f, 0x2a }, 0, .vex_lig_w0, .avx },
		974	.{ .vcvtsi2sd, .rvm, &.{ .xmm, .xmm, .rm64 }, &.{ 0xf2, 0x0f, 0x2a }, 0, .vex_lig_w1, .avx },
1001		975
1002	.{ .vmovss, .rvm, &.{ .xmm, .xmm, .xmm }, &.{ 0xf3, 0x0f, 0x10 }, 0, .vex_128, .avx },	976	.{ .vcvtsi2ss, .rvm, &.{ .xmm, .xmm, .rm32 }, &.{ 0xf2, 0x0f, 0x2a }, 0, .vex_lig_w0, .avx },
1003	.{ .vmovss, .rm, &.{ .xmm, .m32 }, &.{ 0xf3, 0x0f, 0x10 }, 0, .vex_128, .avx },	977	.{ .vcvtsi2ss, .rvm, &.{ .xmm, .xmm, .rm64 }, &.{ 0xf2, 0x0f, 0x2a }, 0, .vex_lig_w1, .avx },
1004	.{ .vmovss, .mvr, &.{ .xmm, .xmm, .xmm }, &.{ 0xf3, 0x0f, 0x11 }, 0, .vex_128, .avx },
1005	.{ .vmovss, .mr, &.{ .m32, .xmm }, &.{ 0xf3, 0x0f, 0x11 }, 0, .vex_128, .avx },
1006		978
1007	.{ .vmovupd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x10 }, 0, .vex_128, .avx },	979	.{ .vcvtss2sd, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0xf2, 0x0f, 0x5a }, 0, .vex_lig_wig, .avx },
1008	.{ .vmovupd, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x66, 0x0f, 0x11 }, 0, .vex_128, .avx },
1009	.{ .vmovupd, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x10 }, 0, .vex_256, .avx },
1010	.{ .vmovupd, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x66, 0x0f, 0x11 }, 0, .vex_256, .avx },
1011		980
1012	.{ .vmovups, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x10 }, 0, .vex_128, .avx },	981	.{ .vmovapd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x28 }, 0, .vex_128_wig, .avx },
1013	.{ .vmovups, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x0f, 0x11 }, 0, .vex_128, .avx },	982	.{ .vmovapd, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x66, 0x0f, 0x29 }, 0, .vex_128_wig, .avx },
1014	.{ .vmovups, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x0f, 0x10 }, 0, .vex_256, .avx },	983	.{ .vmovapd, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x28 }, 0, .vex_256_wig, .avx },
1015	.{ .vmovups, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x0f, 0x11 }, 0, .vex_256, .avx },	984	.{ .vmovapd, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x66, 0x0f, 0x29 }, 0, .vex_256_wig, .avx },
1016		985
1017	.{ .vpextrw, .mri, &.{ .r32, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x15 }, 0, .vex_128, .avx },	986	.{ .vmovaps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x28 }, 0, .vex_128_wig, .avx },
1018	.{ .vpextrw, .mri, &.{ .r64, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x15 }, 0, .vex_128_long, .avx },	987	.{ .vmovaps, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x0f, 0x29 }, 0, .vex_128_wig, .avx },
1019	.{ .vpextrw, .mri, &.{ .r32_m16, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x15 }, 0, .vex_128, .avx },	988	.{ .vmovaps, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x0f, 0x28 }, 0, .vex_256_wig, .avx },
1020	.{ .vpextrw, .mri, &.{ .r64_m16, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x15 }, 0, .vex_128_long, .avx },	989	.{ .vmovaps, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x0f, 0x29 }, 0, .vex_256_wig, .avx },
1021		990
1022	.{ .vpinsrw, .rvmi, &.{ .xmm, .xmm, .r32_m16, .imm8 }, &.{ 0x66, 0x0f, 0xc4 }, 0, .vex_128, .avx },	991	.{ .vmovddup, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x12 }, 0, .vex_128_wig, .avx },
		992	.{ .vmovddup, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0xf2, 0x0f, 0x12 }, 0, .vex_256_wig, .avx },
1023		993
1024	.{ .vpsrld, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd2 }, 0, .vex_128, .avx },	994	.{ .vmovsd, .rvm, &.{ .xmm, .xmm, .xmm }, &.{ 0xf2, 0x0f, 0x10 }, 0, .vex_lig_wig, .avx },
1025	.{ .vpsrld, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x72 }, 2, .vex_128, .avx },	995	.{ .vmovsd, .rm, &.{ .xmm, .m64 }, &.{ 0xf2, 0x0f, 0x10 }, 0, .vex_lig_wig, .avx },
		996	.{ .vmovsd, .mvr, &.{ .xmm, .xmm, .xmm }, &.{ 0xf2, 0x0f, 0x11 }, 0, .vex_lig_wig, .avx },
		997	.{ .vmovsd, .mr, &.{ .m64, .xmm }, &.{ 0xf2, 0x0f, 0x11 }, 0, .vex_lig_wig, .avx },
1026		998
1027	.{ .vpsrlq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd3 }, 0, .vex_128, .avx },	999	.{ .vmovshdup, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0xf3, 0x0f, 0x16 }, 0, .vex_128_wig, .avx },
1028	.{ .vpsrlq, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x73 }, 2, .vex_128, .avx },	1000	.{ .vmovshdup, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0xf3, 0x0f, 0x16 }, 0, .vex_256_wig, .avx },
1029		1001
1030	.{ .vpsrlw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd1 }, 0, .vex_128, .avx },	1002	.{ .vmovsldup, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0xf3, 0x0f, 0x12 }, 0, .vex_128_wig, .avx },
1031	.{ .vpsrlw, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 2, .vex_128, .avx },	1003	.{ .vmovsldup, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0xf3, 0x0f, 0x12 }, 0, .vex_256_wig, .avx },
1032		1004
1033	.{ .vpunpckhbw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x68 }, 0, .vex_128, .avx },	1005	.{ .vmovss, .rvm, &.{ .xmm, .xmm, .xmm }, &.{ 0xf3, 0x0f, 0x10 }, 0, .vex_lig_wig, .avx },
		1006	.{ .vmovss, .rm, &.{ .xmm, .m32 }, &.{ 0xf3, 0x0f, 0x10 }, 0, .vex_lig_wig, .avx },
		1007	.{ .vmovss, .mvr, &.{ .xmm, .xmm, .xmm }, &.{ 0xf3, 0x0f, 0x11 }, 0, .vex_lig_wig, .avx },
		1008	.{ .vmovss, .mr, &.{ .m32, .xmm }, &.{ 0xf3, 0x0f, 0x11 }, 0, .vex_lig_wig, .avx },
1034		1009
1035	.{ .vpunpckhdq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6a }, 0, .vex_128, .avx },	1010	.{ .vmovupd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x10 }, 0, .vex_128_wig, .avx },
		1011	.{ .vmovupd, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x66, 0x0f, 0x11 }, 0, .vex_128_wig, .avx },
		1012	.{ .vmovupd, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x10 }, 0, .vex_256_wig, .avx },
		1013	.{ .vmovupd, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x66, 0x0f, 0x11 }, 0, .vex_256_wig, .avx },
1036		1014
1037	.{ .vpunpckhqdq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6d }, 0, .vex_128, .avx },	1015	.{ .vmovups, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x0f, 0x10 }, 0, .vex_128_wig, .avx },
		1016	.{ .vmovups, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x0f, 0x11 }, 0, .vex_128_wig, .avx },
		1017	.{ .vmovups, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x0f, 0x10 }, 0, .vex_256_wig, .avx },
		1018	.{ .vmovups, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x0f, 0x11 }, 0, .vex_256_wig, .avx },
1038		1019
1039	.{ .vpunpckhwd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x69 }, 0, .vex_128, .avx },	1020	.{ .vpextrw, .rmi, &.{ .r32, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x15 }, 0, .vex_128_wig, .avx },
		1021	.{ .vpextrw, .mri, &.{ .r32_m16, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x15 }, 0, .vex_128_wig, .avx },
1040		1022
1041	.{ .vpunpcklbw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x60 }, 0, .vex_128, .avx },	1023	.{ .vpinsrw, .rvmi, &.{ .xmm, .xmm, .r32_m16, .imm8 }, &.{ 0x66, 0x0f, 0xc4 }, 0, .vex_128_wig, .avx },
1042		1024
1043	.{ .vpunpckldq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x62 }, 0, .vex_128, .avx },	1025	.{ .vpsrlw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd1 }, 0, .vex_128_wig, .avx },
		1026	.{ .vpsrlw, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 2, .vex_128_wig, .avx },
		1027	.{ .vpsrld, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd2 }, 0, .vex_128_wig, .avx },
		1028	.{ .vpsrld, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x72 }, 2, .vex_128_wig, .avx },
		1029	.{ .vpsrlq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd3 }, 0, .vex_128_wig, .avx },
		1030	.{ .vpsrlq, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x73 }, 2, .vex_128_wig, .avx },
1044		1031
1045	.{ .vpunpcklqdq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6c }, 0, .vex_128, .avx },	1032	.{ .vpunpckhbw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x68 }, 0, .vex_128_wig, .avx },
		1033	.{ .vpunpckhwd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x69 }, 0, .vex_128_wig, .avx },
		1034	.{ .vpunpckhdq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6a }, 0, .vex_128_wig, .avx },
		1035	.{ .vpunpckhqdq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6d }, 0, .vex_128_wig, .avx },
1046		1036
1047	.{ .vpunpcklwd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x61 }, 0, .vex_128, .avx },	1037	.{ .vpunpcklbw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x60 }, 0, .vex_128_wig, .avx },
		1038	.{ .vpunpcklwd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x61 }, 0, .vex_128_wig, .avx },
		1039	.{ .vpunpckldq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x62 }, 0, .vex_128_wig, .avx },
		1040	.{ .vpunpcklqdq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6c }, 0, .vex_128_wig, .avx },
1048		1041
1049	// F16C	1042	// F16C
1050	.{ .vcvtph2ps, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0x66, 0x0f, 0x38, 0x13 }, 0, .vex_128, .f16c },	1043	.{ .vcvtph2ps, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0x66, 0x0f, 0x38, 0x13 }, 0, .vex_128_w0, .f16c },
		1044	.{ .vcvtph2ps, .rm, &.{ .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x13 }, 0, .vex_256_w0, .f16c },
1051		1045
1052	.{ .vcvtps2ph, .mri, &.{ .xmm_m64, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x1d }, 0, .vex_128, .f16c },	1046	.{ .vcvtps2ph, .mri, &.{ .xmm_m64, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x1d }, 0, .vex_128_w0, .f16c },
		1047	.{ .vcvtps2ph, .mri, &.{ .xmm_m128, .ymm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x1d }, 0, .vex_256_w0, .f16c },
1053		1048
1054	// FMA	1049	// FMA
1055	.{ .vfmadd132pd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x98 }, 0, .vex_128_long, .fma },	1050	.{ .vfmadd132pd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x98 }, 0, .vex_128_w1, .fma },
1056	.{ .vfmadd132pd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0x98 }, 0, .vex_256_long, .fma },	1051	.{ .vfmadd213pd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xa8 }, 0, .vex_128_w1, .fma },
1057	.{ .vfmadd213pd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xa8 }, 0, .vex_128_long, .fma },	1052	.{ .vfmadd231pd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xb8 }, 0, .vex_128_w1, .fma },
1058	.{ .vfmadd213pd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0xa8 }, 0, .vex_256_long, .fma },	1053	.{ .vfmadd132pd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0x98 }, 0, .vex_256_w1, .fma },
1059	.{ .vfmadd231pd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xb8 }, 0, .vex_128_long, .fma },	1054	.{ .vfmadd213pd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0xa8 }, 0, .vex_256_w1, .fma },
1060	.{ .vfmadd231pd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0xb8 }, 0, .vex_256_long, .fma },	1055	.{ .vfmadd231pd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0xb8 }, 0, .vex_256_w1, .fma },
1061		1056
1062	.{ .vfmadd132ps, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x98 }, 0, .vex_128, .fma },	1057	.{ .vfmadd132ps, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x98 }, 0, .vex_128_w0, .fma },
1063	.{ .vfmadd132ps, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0x98 }, 0, .vex_256, .fma },	1058	.{ .vfmadd213ps, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xa8 }, 0, .vex_128_w0, .fma },
1064	.{ .vfmadd213ps, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xa8 }, 0, .vex_128, .fma },	1059	.{ .vfmadd231ps, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xb8 }, 0, .vex_128_w0, .fma },
1065	.{ .vfmadd213ps, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0xa8 }, 0, .vex_256, .fma },	1060	.{ .vfmadd132ps, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0x98 }, 0, .vex_256_w0, .fma },
1066	.{ .vfmadd231ps, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0xb8 }, 0, .vex_128, .fma },	1061	.{ .vfmadd213ps, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0xa8 }, 0, .vex_256_w0, .fma },
1067	.{ .vfmadd231ps, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0xb8 }, 0, .vex_256, .fma },	1062	.{ .vfmadd231ps, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0xb8 }, 0, .vex_256_w0, .fma },
1068		1063
1069	.{ .vfmadd132sd, .rvm, &.{ .xmm, .xmm, .xmm_m64 }, &.{ 0x66, 0x0f, 0x38, 0x99 }, 0, .vex_128_long, .fma },	1064	.{ .vfmadd132sd, .rvm, &.{ .xmm, .xmm, .xmm_m64 }, &.{ 0x66, 0x0f, 0x38, 0x99 }, 0, .vex_lig_w1, .fma },
1070	.{ .vfmadd213sd, .rvm, &.{ .xmm, .xmm, .xmm_m64 }, &.{ 0x66, 0x0f, 0x38, 0xa9 }, 0, .vex_128_long, .fma },	1065	.{ .vfmadd213sd, .rvm, &.{ .xmm, .xmm, .xmm_m64 }, &.{ 0x66, 0x0f, 0x38, 0xa9 }, 0, .vex_lig_w1, .fma },
1071	.{ .vfmadd231sd, .rvm, &.{ .xmm, .xmm, .xmm_m64 }, &.{ 0x66, 0x0f, 0x38, 0xb9 }, 0, .vex_128_long, .fma },	1066	.{ .vfmadd231sd, .rvm, &.{ .xmm, .xmm, .xmm_m64 }, &.{ 0x66, 0x0f, 0x38, 0xb9 }, 0, .vex_lig_w1, .fma },
1072		1067
1073	.{ .vfmadd132ss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0x66, 0x0f, 0x38, 0x99 }, 0, .vex_128, .fma },	1068	.{ .vfmadd132ss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0x66, 0x0f, 0x38, 0x99 }, 0, .vex_lig_w0, .fma },
1074	.{ .vfmadd213ss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0x66, 0x0f, 0x38, 0xa9 }, 0, .vex_128, .fma },	1069	.{ .vfmadd213ss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0x66, 0x0f, 0x38, 0xa9 }, 0, .vex_lig_w0, .fma },
1075	.{ .vfmadd231ss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0x66, 0x0f, 0x38, 0xb9 }, 0, .vex_128, .fma },	1070	.{ .vfmadd231ss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0x66, 0x0f, 0x38, 0xb9 }, 0, .vex_lig_w0, .fma },
		1071
		1072	// AVX2
		1073	.{ .vpsrlw, .rvm, &.{ .ymm, .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd1 }, 0, .vex_256_wig, .avx2 },
		1074	.{ .vpsrlw, .vmi, &.{ .ymm, .ymm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 2, .vex_256_wig, .avx2 },
		1075	.{ .vpsrld, .rvm, &.{ .ymm, .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd2 }, 0, .vex_256_wig, .avx2 },
		1076	.{ .vpsrld, .vmi, &.{ .ymm, .ymm, .imm8 }, &.{ 0x66, 0x0f, 0x72 }, 2, .vex_256_wig, .avx2 },
		1077	.{ .vpsrlq, .rvm, &.{ .ymm, .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd3 }, 0, .vex_256_wig, .avx2 },
		1078	.{ .vpsrlq, .vmi, &.{ .ymm, .ymm, .imm8 }, &.{ 0x66, 0x0f, 0x73 }, 2, .vex_256_wig, .avx2 },
		1079
		1080	.{ .vpunpckhbw, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x68 }, 0, .vex_256_wig, .avx2 },
		1081	.{ .vpunpckhwd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x69 }, 0, .vex_256_wig, .avx2 },
		1082	.{ .vpunpckhdq, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x6a }, 0, .vex_256_wig, .avx2 },
		1083	.{ .vpunpckhqdq, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x6d }, 0, .vex_256_wig, .avx2 },
		1084
		1085	.{ .vpunpcklbw, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x60 }, 0, .vex_256_wig, .avx2 },
		1086	.{ .vpunpcklwd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x61 }, 0, .vex_256_wig, .avx2 },
		1087	.{ .vpunpckldq, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x62 }, 0, .vex_256_wig, .avx2 },
		1088	.{ .vpunpcklqdq, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x6c }, 0, .vex_256_wig, .avx2 },
1076	};	1089	};
1077	// zig fmt: on	1090	// zig fmt: on

test/behavior/floatop.zig+2-1

...	@@ -52,7 +52,8 @@ fn testFloatComparisons() !void {	...	@@ -52,7 +52,8 @@ fn testFloatComparisons() !void {
52	}	52	}
53		53
54	test "different sized float comparisons" {	54	test "different sized float comparisons" {
55	if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO	55	if (builtin.zig_backend == .stage2_x86_64 and
		56	!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .f16c)) return error.SkipZigTest; // TODO
56	if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO	57	if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
57	if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO	58	if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
58	if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO	59	if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO