authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-10-28 10:19:21+01:00
committergravatar for noreply@github.comGitHub <noreply@github.com> 2025-10-28 10:19:21+01:00
log06d9e3bc065be1614ff8e01e394a5160d7283dd7
tree13da053ff6f744a5db769af887cf87c34d7be29e
parent35e1755c996eb1cff77ff262d93302e5d6f16f9a
parent104c272ae5dc0ab2fc6f81da5918f1b8abf7e131
signaturebadge-check Signed by PGP key B5690EEEBB952194

Merge pull request #25691 from GasInfinity-Forks/x86_16-gcc

feat: init x86_16 arch via CBE

16 files changed, 96 insertions(+), 33 deletions(-)

lib/compiler_rt/int_from_float.zig+1-1
...@@ -74,7 +74,7 @@ pub inline fn bigIntFromFloat(comptime signedness: std.builtin.Signedness, resul...@@ -74,7 +74,7 @@ pub inline fn bigIntFromFloat(comptime signedness: std.builtin.Signedness, resul
74 const parts = math.frexp(a);74 const parts = math.frexp(a);
75 const significand_bits_adjusted_to_handle_smin = @as(i32, significand_bits) +75 const significand_bits_adjusted_to_handle_smin = @as(i32, significand_bits) +
76 @intFromBool(signedness == .signed and parts.exponent == 32 * result.len);76 @intFromBool(signedness == .signed and parts.exponent == 32 * result.len);
77 const exponent = @max(parts.exponent - significand_bits_adjusted_to_handle_smin, 0);77 const exponent: usize = @intCast(@max(parts.exponent - significand_bits_adjusted_to_handle_smin, 0));
78 const int: I = @intFromFloat(switch (exponent) {78 const int: I = @intFromFloat(switch (exponent) {
79 0 => a,79 0 => a,
80 else => math.ldexp(parts.significand, significand_bits_adjusted_to_handle_smin),80 else => math.ldexp(parts.significand, significand_bits_adjusted_to_handle_smin),
lib/std/Io/Writer.zig+1-1
...@@ -604,7 +604,7 @@ pub fn print(w: *Writer, comptime fmt: []const u8, args: anytype) Error!void {...@@ -604,7 +604,7 @@ pub fn print(w: *Writer, comptime fmt: []const u8, args: anytype) Error!void {
604 @compileError("32 arguments max are supported per format call");604 @compileError("32 arguments max are supported per format call");
605 }605 }
606606
607 @setEvalBranchQuota(fmt.len * 1000);607 @setEvalBranchQuota(@as(comptime_int, fmt.len) * 1000); // NOTE: We're upcasting as 16-bit usize overflows.
608 comptime var arg_state: std.fmt.ArgState = .{ .args_len = fields_info.len };608 comptime var arg_state: std.fmt.ArgState = .{ .args_len = fields_info.len };
609 comptime var i = 0;609 comptime var i = 0;
610 comptime var literal: []const u8 = "";610 comptime var literal: []const u8 = "";
lib/std/Target.zig+23-7
...@@ -1083,7 +1083,7 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {...@@ -1083,7 +1083,7 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
1083 .sparc => if (target.cpu.has(.sparc, .v9)) .SPARC32PLUS else .SPARC,1083 .sparc => if (target.cpu.has(.sparc, .v9)) .SPARC32PLUS else .SPARC,
1084 .sparc64 => .SPARCV9,1084 .sparc64 => .SPARCV9,
1085 .ve => .VE,1085 .ve => .VE,
1086 .x86 => .@"386",1086 .x86_16, .x86 => .@"386",
1087 .x86_64 => .X86_64,1087 .x86_64 => .X86_64,
1088 .xcore => .XCORE,1088 .xcore => .XCORE,
1089 .xtensa, .xtensaeb => .XTENSA,1089 .xtensa, .xtensaeb => .XTENSA,
...@@ -1154,6 +1154,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {...@@ -1154,6 +1154,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
1154 .ve,1154 .ve,
1155 .wasm32,1155 .wasm32,
1156 .wasm64,1156 .wasm64,
1157 .x86_16,
1157 .xcore,1158 .xcore,
1158 .xtensa,1159 .xtensa,
1159 .xtensaeb,1160 .xtensaeb,
...@@ -1376,6 +1377,7 @@ pub const Cpu = struct {...@@ -1376,6 +1377,7 @@ pub const Cpu = struct {
1376 ve,1377 ve,
1377 wasm32,1378 wasm32,
1378 wasm64,1379 wasm64,
1380 x86_16,
1379 x86,1381 x86,
1380 x86_64,1382 x86_64,
1381 xcore,1383 xcore,
...@@ -1467,7 +1469,7 @@ pub const Cpu = struct {...@@ -1467,7 +1469,7 @@ pub const Cpu = struct {
1467 .spirv32, .spirv64 => .spirv,1469 .spirv32, .spirv64 => .spirv,
1468 .ve => .ve,1470 .ve => .ve,
1469 .wasm32, .wasm64 => .wasm,1471 .wasm32, .wasm64 => .wasm,
1470 .x86, .x86_64 => .x86,1472 .x86_16, .x86, .x86_64 => .x86,
1471 .xcore => .xcore,1473 .xcore => .xcore,
1472 .xtensa, .xtensaeb => .xtensa,1474 .xtensa, .xtensaeb => .xtensa,
1473 };1475 };
...@@ -1475,7 +1477,7 @@ pub const Cpu = struct {...@@ -1475,7 +1477,7 @@ pub const Cpu = struct {
14751477
1476 pub inline fn isX86(arch: Arch) bool {1478 pub inline fn isX86(arch: Arch) bool {
1477 return switch (arch) {1479 return switch (arch) {
1478 .x86, .x86_64 => true,1480 .x86_16, .x86, .x86_64 => true,
1479 else => false,1481 else => false,
1480 };1482 };
1481 }1483 }
...@@ -1669,6 +1671,7 @@ pub const Cpu = struct {...@@ -1669,6 +1671,7 @@ pub const Cpu = struct {
1669 .ve,1671 .ve,
1670 .wasm32,1672 .wasm32,
1671 .wasm64,1673 .wasm64,
1674 .x86_16,
1672 .x86,1675 .x86,
1673 .x86_64,1676 .x86_64,
1674 .xcore,1677 .xcore,
...@@ -1789,6 +1792,12 @@ pub const Cpu = struct {...@@ -1789,6 +1792,12 @@ pub const Cpu = struct {
1789 .x86_interrupt,1792 .x86_interrupt,
1790 => &.{.x86},1793 => &.{.x86},
17911794
1795 .x86_16_cdecl,
1796 .x86_16_stdcall,
1797 .x86_16_regparmcall,
1798 .x86_16_interrupt,
1799 => &.{.x86_16},
1800
1792 .aarch64_aapcs,1801 .aarch64_aapcs,
1793 .aarch64_aapcs_darwin,1802 .aarch64_aapcs_darwin,
1794 .aarch64_aapcs_win,1803 .aarch64_aapcs_win,
...@@ -1971,6 +1980,7 @@ pub const Cpu = struct {...@@ -1971,6 +1980,7 @@ pub const Cpu = struct {
1971 .riscv64, .riscv64be => &riscv.cpu.generic_rv64,1980 .riscv64, .riscv64be => &riscv.cpu.generic_rv64,
1972 .sparc64 => &sparc.cpu.v9, // SPARC can only be 64-bit from v9 and up.1981 .sparc64 => &sparc.cpu.v9, // SPARC can only be 64-bit from v9 and up.
1973 .wasm32, .wasm64 => &wasm.cpu.mvp,1982 .wasm32, .wasm64 => &wasm.cpu.mvp,
1983 .x86_16 => &x86.cpu.i86,
1974 .x86 => &x86.cpu.i386,1984 .x86 => &x86.cpu.i386,
1975 .x86_64 => &x86.cpu.x86_64,1985 .x86_64 => &x86.cpu.x86_64,
1976 inline else => |a| &@field(Target, @tagName(a.family())).cpu.generic,1986 inline else => |a| &@field(Target, @tagName(a.family())).cpu.generic,
...@@ -2237,7 +2247,10 @@ pub fn supportsAddressSpace(...@@ -2237,7 +2247,10 @@ pub fn supportsAddressSpace(
22372247
2238 return switch (address_space) {2248 return switch (address_space) {
2239 .generic => true,2249 .generic => true,
2240 .fs, .gs, .ss => (arch == .x86_64 or arch == .x86) and (context == null or context == .pointer),2250 .fs, .gs, .ss => (arch == .x86_64 or arch == .x86 or arch == .x86_16) and (context == null or context == .pointer),
2251 // Technically x86 can use segmentation...
2252 .far => (arch == .x86_16),
2253
2241 .flash, .flash1, .flash2, .flash3, .flash4, .flash5 => arch == .avr, // TODO this should also check how many flash banks the cpu has2254 .flash, .flash1, .flash2, .flash3, .flash4, .flash5 => arch == .avr, // TODO this should also check how many flash banks the cpu has
2242 .cog, .hub => arch == .propeller,2255 .cog, .hub => arch == .propeller,
2243 .lut => arch == .propeller and std.Target.propeller.featureSetHas(target.cpu.features, .p2),2256 .lut => arch == .propeller and std.Target.propeller.featureSetHas(target.cpu.features, .p2),
...@@ -2800,6 +2813,7 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {...@@ -2800,6 +2813,7 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
2800 return switch (cpu_arch) {2813 return switch (cpu_arch) {
2801 .avr,2814 .avr,
2802 .msp430,2815 .msp430,
2816 .x86_16,
2803 => 16,2817 => 16,
28042818
2805 .arc,2819 .arc,
...@@ -3013,7 +3027,7 @@ pub fn cTypeByteSize(t: *const Target, c_type: CType) u16 {...@@ -3013,7 +3027,7 @@ pub fn cTypeByteSize(t: *const Target, c_type: CType) u16 {
3013pub fn cTypeBitSize(target: *const Target, c_type: CType) u16 {3027pub fn cTypeBitSize(target: *const Target, c_type: CType) u16 {
3014 switch (target.os.tag) {3028 switch (target.os.tag) {
3015 .freestanding, .other => switch (target.cpu.arch) {3029 .freestanding, .other => switch (target.cpu.arch) {
3016 .msp430 => switch (c_type) {3030 .msp430, .x86_16 => switch (c_type) {
3017 .char => return 8,3031 .char => return 8,
3018 .short, .ushort, .int, .uint => return 16,3032 .short, .ushort, .int, .uint => return 16,
3019 .float, .long, .ulong => return 32,3033 .float, .long, .ulong => return 32,
...@@ -3369,6 +3383,7 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {...@@ -3369,6 +3383,7 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
3369 std.math.ceilPowerOfTwoAssert(u16, (cTypeBitSize(target, c_type) + 7) / 8),3383 std.math.ceilPowerOfTwoAssert(u16, (cTypeBitSize(target, c_type) + 7) / 8),
3370 @as(u16, switch (target.cpu.arch) {3384 @as(u16, switch (target.cpu.arch) {
3371 .msp430,3385 .msp430,
3386 .x86_16,
3372 => 2,3387 => 2,
33733388
3374 .arc,3389 .arc,
...@@ -3476,7 +3491,7 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {...@@ -3476,7 +3491,7 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
3476 return @min(3491 return @min(
3477 std.math.ceilPowerOfTwoAssert(u16, (cTypeBitSize(target, c_type) + 7) / 8),3492 std.math.ceilPowerOfTwoAssert(u16, (cTypeBitSize(target, c_type) + 7) / 8),
3478 @as(u16, switch (target.cpu.arch) {3493 @as(u16, switch (target.cpu.arch) {
3479 .msp430 => 2,3494 .x86_16, .msp430 => 2,
34803495
3481 .arc,3496 .arc,
3482 .arceb,3497 .arceb,
...@@ -3548,7 +3563,7 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {...@@ -3548,7 +3563,7 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
3548 return switch (target.cpu.arch) {3563 return switch (target.cpu.arch) {
3549 .avr => 1,3564 .avr => 1,
35503565
3551 .msp430 => 2,3566 .msp430, .x86_16 => 2,
35523567
3553 .arc,3568 .arc,
3554 .arceb,3569 .arceb,
...@@ -3625,6 +3640,7 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention...@@ -3625,6 +3640,7 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
3625 .windows, .uefi => .{ .x86_win = .{} },3640 .windows, .uefi => .{ .x86_win = .{} },
3626 else => .{ .x86_sysv = .{} },3641 else => .{ .x86_sysv = .{} },
3627 },3642 },
3643 .x86_16 => .{ .x86_16_cdecl = .{} },
3628 .aarch64, .aarch64_be => if (target.os.tag.isDarwin())3644 .aarch64, .aarch64_be => if (target.os.tag.isDarwin())
3629 .{ .aarch64_aapcs_darwin = .{} }3645 .{ .aarch64_aapcs_darwin = .{} }
3630 else switch (target.os.tag) {3646 else switch (target.os.tag) {
lib/std/Target/x86.zig+5
...@@ -3081,6 +3081,11 @@ pub const cpu = struct {...@@ -3081,6 +3081,11 @@ pub const cpu = struct {
3081 .xsaveopt,3081 .xsaveopt,
3082 }),3082 }),
3083 };3083 };
3084 pub const @"i86": CpuModel = .{
3085 .name = "i86",
3086 .llvm_name = null,
3087 .features = featureSet(&[_]Feature{}),
3088 };
3084 pub const @"i386": CpuModel = .{3089 pub const @"i386": CpuModel = .{
3085 .name = "i386",3090 .name = "i386",
3086 .llvm_name = "i386",3091 .llvm_name = "i386",
lib/std/builtin.zig+11
...@@ -223,6 +223,13 @@ pub const CallingConvention = union(enum(u8)) {...@@ -223,6 +223,13 @@ pub const CallingConvention = union(enum(u8)) {
223 x86_vectorcall: CommonOptions,223 x86_vectorcall: CommonOptions,
224 x86_interrupt: CommonOptions,224 x86_interrupt: CommonOptions,
225225
226 // Calling conventions for the `x86_16` architecture.
227
228 x86_16_cdecl: CommonOptions,
229 x86_16_stdcall: CommonOptions,
230 x86_16_regparmcall: CommonOptions,
231 x86_16_interrupt: CommonOptions,
232
226 // Calling conventions for the `aarch64` and `aarch64_be` architectures.233 // Calling conventions for the `aarch64` and `aarch64_be` architectures.
227 aarch64_aapcs: CommonOptions,234 aarch64_aapcs: CommonOptions,
228 aarch64_aapcs_darwin: CommonOptions,235 aarch64_aapcs_darwin: CommonOptions,
...@@ -523,6 +530,10 @@ pub const AddressSpace = enum(u5) {...@@ -523,6 +530,10 @@ pub const AddressSpace = enum(u5) {
523 fs,530 fs,
524 ss,531 ss,
525532
533 // x86_16 extra address spaces.
534 /// Allows addressing the entire address space by storing both segment and offset.
535 far,
536
526 // GPU address spaces.537 // GPU address spaces.
527 global,538 global,
528 constant,539 constant,
lib/std/builtin/assembly.zig+1-1
...@@ -1,5 +1,5 @@...@@ -1,5 +1,5 @@
1pub const Clobbers = switch (@import("builtin").cpu.arch) {1pub const Clobbers = switch (@import("builtin").cpu.arch) {
2 .x86, .x86_64 => packed struct {2 .x86_16, .x86, .x86_64 => packed struct {
3 /// Whether the inline assembly code may perform stores to memory3 /// Whether the inline assembly code may perform stores to memory
4 /// addresses other than those derived from input pointer provenance.4 /// addresses other than those derived from input pointer provenance.
5 memory: bool = false,5 memory: bool = false,
lib/std/os/windows.zig+22-19
...@@ -4634,25 +4634,28 @@ pub const TEB = extern struct {...@@ -4634,25 +4634,28 @@ pub const TEB = extern struct {
4634};4634};
46354635
4636comptime {4636comptime {
4637 // Offsets taken from WinDbg info and Geoff Chappell[1] (RIP)4637 // XXX: Without this check we cannot use `std.Io.Writer` on 16-bit platforms. `std.fmt.bufPrint` will hit the unreachable in `PEB.GdiHandleBuffer` without this guard.
4638 // [1]: https://www.geoffchappell.com/studies/windows/km/ntoskrnl/inc/api/pebteb/teb/index.htm4638 if (builtin.os.tag == .windows) {
4639 assert(@offsetOf(TEB, "NtTib") == 0x00);4639 // Offsets taken from WinDbg info and Geoff Chappell[1] (RIP)
4640 if (@sizeOf(usize) == 4) {4640 // [1]: https://www.geoffchappell.com/studies/windows/km/ntoskrnl/inc/api/pebteb/teb/index.htm
4641 assert(@offsetOf(TEB, "EnvironmentPointer") == 0x1C);4641 assert(@offsetOf(TEB, "NtTib") == 0x00);
4642 assert(@offsetOf(TEB, "ClientId") == 0x20);4642 if (@sizeOf(usize) == 4) {
4643 assert(@offsetOf(TEB, "ActiveRpcHandle") == 0x28);4643 assert(@offsetOf(TEB, "EnvironmentPointer") == 0x1C);
4644 assert(@offsetOf(TEB, "ThreadLocalStoragePointer") == 0x2C);4644 assert(@offsetOf(TEB, "ClientId") == 0x20);
4645 assert(@offsetOf(TEB, "ProcessEnvironmentBlock") == 0x30);4645 assert(@offsetOf(TEB, "ActiveRpcHandle") == 0x28);
4646 assert(@offsetOf(TEB, "LastErrorValue") == 0x34);4646 assert(@offsetOf(TEB, "ThreadLocalStoragePointer") == 0x2C);
4647 assert(@offsetOf(TEB, "TlsSlots") == 0xe10);4647 assert(@offsetOf(TEB, "ProcessEnvironmentBlock") == 0x30);
4648 } else if (@sizeOf(usize) == 8) {4648 assert(@offsetOf(TEB, "LastErrorValue") == 0x34);
4649 assert(@offsetOf(TEB, "EnvironmentPointer") == 0x38);4649 assert(@offsetOf(TEB, "TlsSlots") == 0xe10);
4650 assert(@offsetOf(TEB, "ClientId") == 0x40);4650 } else if (@sizeOf(usize) == 8) {
4651 assert(@offsetOf(TEB, "ActiveRpcHandle") == 0x50);4651 assert(@offsetOf(TEB, "EnvironmentPointer") == 0x38);
4652 assert(@offsetOf(TEB, "ThreadLocalStoragePointer") == 0x58);4652 assert(@offsetOf(TEB, "ClientId") == 0x40);
4653 assert(@offsetOf(TEB, "ProcessEnvironmentBlock") == 0x60);4653 assert(@offsetOf(TEB, "ActiveRpcHandle") == 0x50);
4654 assert(@offsetOf(TEB, "LastErrorValue") == 0x68);4654 assert(@offsetOf(TEB, "ThreadLocalStoragePointer") == 0x58);
4655 assert(@offsetOf(TEB, "TlsSlots") == 0x1480);4655 assert(@offsetOf(TEB, "ProcessEnvironmentBlock") == 0x60);
4656 assert(@offsetOf(TEB, "LastErrorValue") == 0x68);
4657 assert(@offsetOf(TEB, "TlsSlots") == 0x1480);
4658 }
4656 }4659 }
4657}4660}
46584661
lib/std/zig/system.zig+5
...@@ -374,6 +374,11 @@ pub fn resolveTargetQuery(query: Target.Query) DetectError!Target {...@@ -374,6 +374,11 @@ pub fn resolveTargetQuery(query: Target.Query) DetectError!Target {
374 // However, the "mode" flags can be used as overrides, so if the user explicitly374 // However, the "mode" flags can be used as overrides, so if the user explicitly
375 // sets one of them, that takes precedence.375 // sets one of them, that takes precedence.
376 switch (query_cpu_arch) {376 switch (query_cpu_arch) {
377 .x86_16 => {
378 cpu.features.addFeature(
379 @intFromEnum(Target.x86.Feature.@"16bit_mode"),
380 );
381 },
377 .x86 => {382 .x86 => {
378 if (!Target.x86.featureSetHasAny(query.cpu_features_add, .{383 if (!Target.x86.featureSetHasAny(query.cpu_features_add, .{
379 .@"16bit_mode", .@"32bit_mode",384 .@"16bit_mode", .@"32bit_mode",
lib/std/zig/target.zig+3-2
...@@ -472,8 +472,9 @@ fn eqlIgnoreCase(ignore_case: bool, a: []const u8, b: []const u8) bool {...@@ -472,8 +472,9 @@ fn eqlIgnoreCase(ignore_case: bool, a: []const u8, b: []const u8) bool {
472 }472 }
473}473}
474474
475pub fn intByteSize(target: *const std.Target, bits: u16) u19 {475pub fn intByteSize(target: *const std.Target, bits: u16) u16 {
476 return std.mem.alignForward(u19, @intCast((@as(u17, bits) + 7) / 8), intAlignment(target, bits));476 const previous_aligned = std.mem.alignBackward(u16, bits, 8);
477 return std.mem.alignForward(u16, @divExact(previous_aligned, 8) + @intFromBool(previous_aligned != bits), intAlignment(target, bits));
477}478}
478479
479pub fn intAlignment(target: *const std.Target, bits: u16) u16 {480pub fn intAlignment(target: *const std.Target, bits: u16) u16 {
lib/zig.h+6-1
...@@ -74,6 +74,9 @@...@@ -74,6 +74,9 @@
74#elif defined (__x86_64__) || (defined(zig_msvc) && defined(_M_X64))74#elif defined (__x86_64__) || (defined(zig_msvc) && defined(_M_X64))
75#define zig_x86_6475#define zig_x86_64
76#define zig_x8676#define zig_x86
77#elif defined(__I86__)
78#define zig_x86_16
79#define zig_x86
77#endif80#endif
7881
79#if defined(zig_msvc) || __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__82#if defined(zig_msvc) || __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
...@@ -400,6 +403,8 @@...@@ -400,6 +403,8 @@
400#define zig_trap() __asm__ volatile("j 0x2")403#define zig_trap() __asm__ volatile("j 0x2")
401#elif defined(zig_sparc)404#elif defined(zig_sparc)
402#define zig_trap() __asm__ volatile("illtrap")405#define zig_trap() __asm__ volatile("illtrap")
406#elif defined(zig_x86_16)
407#define zig_trap() __asm__ volatile("int $0x3")
403#elif defined(zig_x86)408#elif defined(zig_x86)
404#define zig_trap() __asm__ volatile("ud2")409#define zig_trap() __asm__ volatile("ud2")
405#else410#else
...@@ -4219,7 +4224,7 @@ static inline void zig_loongarch_cpucfg(uint32_t word, uint32_t* result) {...@@ -4219,7 +4224,7 @@ static inline void zig_loongarch_cpucfg(uint32_t word, uint32_t* result) {
4219#endif4224#endif
4220}4225}
42214226
4222#elif defined(zig_x86)4227#elif defined(zig_x86) && !defined(zig_x86_16)
42234228
4224static inline void zig_x86_cpuid(uint32_t leaf_id, uint32_t subid, uint32_t* eax, uint32_t* ebx, uint32_t* ecx, uint32_t* edx) {4229static inline void zig_x86_cpuid(uint32_t leaf_id, uint32_t subid, uint32_t* eax, uint32_t* ebx, uint32_t* ecx, uint32_t* edx) {
4225#if defined(zig_msvc)4230#if defined(zig_msvc)
src/Sema.zig+1
...@@ -9034,6 +9034,7 @@ pub fn handleExternLibName(...@@ -9034,6 +9034,7 @@ pub fn handleExternLibName(
9034/// Any calling conventions not included here are either not yet verified to work with variadic9034/// Any calling conventions not included here are either not yet verified to work with variadic
9035/// functions or there are no more other calling conventions that support variadic functions.9035/// functions or there are no more other calling conventions that support variadic functions.
9036const calling_conventions_supporting_var_args = [_]std.builtin.CallingConvention.Tag{9036const calling_conventions_supporting_var_args = [_]std.builtin.CallingConvention.Tag{
9037 .x86_16_cdecl,
9037 .x86_64_sysv,9038 .x86_64_sysv,
9038 .x86_64_x32,9039 .x86_64_x32,
9039 .x86_64_win,9040 .x86_64_win,
src/Zcu.zig+4
...@@ -4406,6 +4406,10 @@ pub fn callconvSupported(zcu: *Zcu, cc: std.builtin.CallingConvention) union(enu...@@ -4406,6 +4406,10 @@ pub fn callconvSupported(zcu: *Zcu, cc: std.builtin.CallingConvention) union(enu
4406 }4406 }
4407 }4407 }
4408 break :ok switch (cc) {4408 break :ok switch (cc) {
4409 .x86_16_cdecl,
4410 .x86_16_stdcall,
4411 .x86_16_regparmcall,
4412 .x86_16_interrupt,
4409 .x86_64_sysv,4413 .x86_64_sysv,
4410 .x86_64_win,4414 .x86_64_win,
4411 .x86_64_vectorcall,4415 .x86_64_vectorcall,
src/codegen/c.zig+4-1
...@@ -8055,9 +8055,11 @@ fn toCallingConvention(cc: std.builtin.CallingConvention, zcu: *Zcu) ?[]const u8...@@ -8055,9 +8055,11 @@ fn toCallingConvention(cc: std.builtin.CallingConvention, zcu: *Zcu) ?[]const u8
8055 return switch (cc) {8055 return switch (cc) {
8056 .auto, .naked => null,8056 .auto, .naked => null,
80578057
8058 .x86_16_cdecl => "cdecl",
8059 .x86_16_regparmcall => "regparmcall",
8058 .x86_64_sysv, .x86_sysv => "sysv_abi",8060 .x86_64_sysv, .x86_sysv => "sysv_abi",
8059 .x86_64_win, .x86_win => "ms_abi",8061 .x86_64_win, .x86_win => "ms_abi",
8060 .x86_stdcall => "stdcall",8062 .x86_16_stdcall, .x86_stdcall => "stdcall",
8061 .x86_fastcall => "fastcall",8063 .x86_fastcall => "fastcall",
8062 .x86_thiscall => "thiscall",8064 .x86_thiscall => "thiscall",
80638065
...@@ -8127,6 +8129,7 @@ fn toCallingConvention(cc: std.builtin.CallingConvention, zcu: *Zcu) ?[]const u8...@@ -8127,6 +8129,7 @@ fn toCallingConvention(cc: std.builtin.CallingConvention, zcu: *Zcu) ?[]const u8
8127 .csky_interrupt,8129 .csky_interrupt,
8128 .m68k_interrupt,8130 .m68k_interrupt,
8129 .msp430_interrupt,8131 .msp430_interrupt,
8132 .x86_16_interrupt,
8130 .x86_interrupt,8133 .x86_interrupt,
8131 .x86_64_interrupt,8134 .x86_64_interrupt,
8132 => "interrupt",8135 => "interrupt",
src/codegen/llvm.zig+7
...@@ -117,6 +117,7 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8...@@ -117,6 +117,7 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8
117 .propeller,117 .propeller,
118 .sh,118 .sh,
119 .sheb,119 .sheb,
120 .x86_16,
120 .xtensaeb,121 .xtensaeb,
121 => unreachable, // Gated by hasLlvmSupport().122 => unreachable, // Gated by hasLlvmSupport().
122 };123 };
...@@ -493,6 +494,7 @@ pub fn dataLayout(target: *const std.Target) []const u8 {...@@ -493,6 +494,7 @@ pub fn dataLayout(target: *const std.Target) []const u8 {
493 .propeller,494 .propeller,
494 .sh,495 .sh,
495 .sheb,496 .sheb,
497 .x86_16,
496 .xtensaeb,498 .xtensaeb,
497 => unreachable, // Gated by hasLlvmSupport().499 => unreachable, // Gated by hasLlvmSupport().
498 };500 };
...@@ -11902,6 +11904,10 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: *const s...@@ -11902,6 +11904,10 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: *const s
1190211904
11903 // All the calling conventions which LLVM does not have a general representation for.11905 // All the calling conventions which LLVM does not have a general representation for.
11904 // Note that these are often still supported through the `cCallingConvention` path above via `ccc`.11906 // Note that these are often still supported through the `cCallingConvention` path above via `ccc`.
11907 .x86_16_cdecl,
11908 .x86_16_stdcall,
11909 .x86_16_regparmcall,
11910 .x86_16_interrupt,
11905 .x86_sysv,11911 .x86_sysv,
11906 .x86_win,11912 .x86_win,
11907 .x86_thiscall_mingw,11913 .x86_thiscall_mingw,
...@@ -13131,6 +13137,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {...@@ -13131,6 +13137,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
13131 .propeller,13137 .propeller,
13132 .sh,13138 .sh,
13133 .sheb,13139 .sheb,
13140 .x86_16,
13134 .xtensaeb,13141 .xtensaeb,
13135 => unreachable,13142 => unreachable,
13136 }13143 }
src/codegen/spirv/Module.zig+1
...@@ -927,6 +927,7 @@ pub fn storageClass(module: *Module, as: std.builtin.AddressSpace) spec.StorageC...@@ -927,6 +927,7 @@ pub fn storageClass(module: *Module, as: std.builtin.AddressSpace) spec.StorageC
927 .gs,927 .gs,
928 .fs,928 .fs,
929 .ss,929 .ss,
930 .far,
930 .param,931 .param,
931 .flash,932 .flash,
932 .flash1,933 .flash1,
src/target.zig+1
...@@ -227,6 +227,7 @@ pub fn hasLlvmSupport(target: *const std.Target, ofmt: std.Target.ObjectFormat)...@@ -227,6 +227,7 @@ pub fn hasLlvmSupport(target: *const std.Target, ofmt: std.Target.ObjectFormat)
227 .propeller,227 .propeller,
228 .sh,228 .sh,
229 .sheb,229 .sheb,
230 .x86_16,
230 .xtensaeb,231 .xtensaeb,
231 => false,232 => false,
232 };233 };