authorgravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2025-01-03 05:44:03-05:00
committergravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2025-01-16 20:47:30-05:00
log094ac8c3dc7945c8452931aed28d6e0b3e26769b
tree6453fe249bc6044f949f3fd0b07648ae9edded09
parentb7acd977896a13d37d3f592627e55d372aeedc6a

x86_64: fix f16 miscomp exposed by new calling convention

1 files changed, 16 insertions(+), 16 deletions(-)

src/arch/x86_64/CodeGen.zig+16-16
......@@ -17443,21 +17443,22 @@ fn genBinOp(
1744317443 .float => switch (lhs_ty.floatBits(self.target.*)) {
1744417444 16 => {
1744517445 assert(self.hasFeature(.f16c));
17446 const tmp_reg =
17447 (try self.register_manager.allocReg(null, abi.RegisterClass.sse)).to128();
17446 const lhs_reg = if (copied_to_dst) dst_reg else registerAlias(lhs_mcv.getReg().?, abi_size);
17447
17448 const tmp_reg = (try self.register_manager.allocReg(null, abi.RegisterClass.sse)).to128();
1744817449 const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
1744917450 defer self.register_manager.unlockReg(tmp_lock);
1745017451
1745117452 if (src_mcv.isBase()) try self.asmRegisterRegisterMemoryImmediate(
1745217453 .{ .vp_w, .insr },
1745317454 dst_reg,
17454 dst_reg,
17455 lhs_reg,
1745517456 try src_mcv.mem(self, .{ .size = .word }),
1745617457 .u(1),
1745717458 ) else try self.asmRegisterRegisterRegister(
1745817459 .{ .vp_, .unpcklwd },
1745917460 dst_reg,
17460 dst_reg,
17461 lhs_reg,
1746117462 (if (src_mcv.isRegister())
1746217463 src_mcv.getReg().?
1746317464 else
......@@ -17885,25 +17886,24 @@ fn genBinOp(
1788517886 .float => switch (lhs_ty.childType(zcu).floatBits(self.target.*)) {
1788617887 16 => tag: {
1788717888 assert(self.hasFeature(.f16c));
17889 const lhs_reg = if (copied_to_dst) dst_reg else registerAlias(lhs_mcv.getReg().?, abi_size);
1788817890 switch (lhs_ty.vectorLen(zcu)) {
1788917891 1 => {
17890 const tmp_reg = (try self.register_manager.allocReg(
17891 null,
17892 abi.RegisterClass.sse,
17893 )).to128();
17892 const tmp_reg =
17893 (try self.register_manager.allocReg(null, abi.RegisterClass.sse)).to128();
1789417894 const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
1789517895 defer self.register_manager.unlockReg(tmp_lock);
1789617896
1789717897 if (src_mcv.isBase()) try self.asmRegisterRegisterMemoryImmediate(
1789817898 .{ .vp_w, .insr },
1789917899 dst_reg,
17900 dst_reg,
17900 lhs_reg,
1790117901 try src_mcv.mem(self, .{ .size = .word }),
1790217902 .u(1),
1790317903 ) else try self.asmRegisterRegisterRegister(
1790417904 .{ .vp_, .unpcklwd },
1790517905 dst_reg,
17906 dst_reg,
17906 lhs_reg,
1790717907 (if (src_mcv.isRegister())
1790817908 src_mcv.getReg().?
1790917909 else
......@@ -17941,15 +17941,16 @@ fn genBinOp(
1794117941 const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
1794217942 defer self.register_manager.unlockReg(tmp_lock);
1794317943
17944 if (src_mcv.isBase()) try self.asmRegisterMemoryImmediate(
17944 if (src_mcv.isBase()) try self.asmRegisterRegisterMemoryImmediate(
1794517945 .{ .vp_d, .insr },
1794617946 dst_reg,
17947 lhs_reg,
1794717948 try src_mcv.mem(self, .{ .size = .dword }),
1794817949 .u(1),
1794917950 ) else try self.asmRegisterRegisterRegister(
1795017951 .{ .v_ps, .unpckl },
1795117952 dst_reg,
17952 dst_reg,
17953 lhs_reg,
1795317954 (if (src_mcv.isRegister())
1795417955 src_mcv.getReg().?
1795517956 else
......@@ -17992,7 +17993,7 @@ fn genBinOp(
1799217993 const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
1799317994 defer self.register_manager.unlockReg(tmp_lock);
1799417995
17995 try self.asmRegisterRegister(.{ .v_ps, .cvtph2 }, dst_reg, dst_reg);
17996 try self.asmRegisterRegister(.{ .v_ps, .cvtph2 }, dst_reg, lhs_reg);
1799617997 if (src_mcv.isBase()) try self.asmRegisterMemory(
1799717998 .{ .v_ps, .cvtph2 },
1799817999 tmp_reg,
......@@ -18035,7 +18036,7 @@ fn genBinOp(
1803518036 const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
1803618037 defer self.register_manager.unlockReg(tmp_lock);
1803718038
18038 try self.asmRegisterRegister(.{ .v_ps, .cvtph2 }, dst_reg.to256(), dst_reg);
18039 try self.asmRegisterRegister(.{ .v_ps, .cvtph2 }, dst_reg.to256(), lhs_reg);
1803918040 if (src_mcv.isBase()) try self.asmRegisterMemory(
1804018041 .{ .v_ps, .cvtph2 },
1804118042 tmp_reg,
......@@ -18196,8 +18197,7 @@ fn genBinOp(
1819618197
1819718198 switch (mir_tag[1]) {
1819818199 else => if (self.hasFeature(.avx)) {
18199 const lhs_reg =
18200 if (copied_to_dst) dst_reg else registerAlias(lhs_mcv.getReg().?, abi_size);
18200 const lhs_reg = if (copied_to_dst) dst_reg else registerAlias(lhs_mcv.getReg().?, abi_size);
1820118201 if (src_mcv.isBase()) try self.asmRegisterRegisterMemory(
1820218202 mir_tag,
1820318203 dst_reg,