| ... | ... | @@ -431,6 +431,17 @@ fn asmJmpReloc(self: *Self, target: Mir.Inst.Index) !Mir.Inst.Index { |
| 431 | 431 | }); |
| 432 | 432 | } |
| 433 | 433 | |
| 434 | fn asmJccReloc(self: *Self, target: Mir.Inst.Index, cc: bits.Condition) !Mir.Inst.Index { |
| 435 | return self.addInst(.{ |
| 436 | .tag = .jcc, |
| 437 | .ops = .inst_cc, |
| 438 | .data = .{ .inst_cc = .{ |
| 439 | .inst = target, |
| 440 | .cc = cc, |
| 441 | } }, |
| 442 | }); |
| 443 | } |
| 444 | |
| 434 | 445 | fn asmNone(self: *Self, tag: Mir.Inst.Tag) !void { |
| 435 | 446 | _ = try self.addInst(.{ |
| 436 | 447 | .tag = tag, |
| ... | ... | @@ -4360,29 +4371,13 @@ fn genCondBrMir(self: *Self, ty: Type, mcv: MCValue) !u32 { |
| 4360 | 4371 | const abi_size = ty.abiSize(self.target.*); |
| 4361 | 4372 | switch (mcv) { |
| 4362 | 4373 | .eflags => |cc| { |
| 4363 | | return self.addInst(.{ |
| 4364 | | .tag = .jcc, |
| 4365 | | .ops = .inst_cc, |
| 4366 | | .data = .{ |
| 4367 | | .inst_cc = .{ |
| 4368 | | .inst = undefined, |
| 4369 | | // Here we map the opposites since the jump is to the false branch. |
| 4370 | | .cc = cc.negate(), |
| 4371 | | }, |
| 4372 | | }, |
| 4373 | | }); |
| 4374 | // Here we map the opposites since the jump is to the false branch. |
| 4375 | return self.asmJccReloc(undefined, cc.negate()); |
| 4374 | 4376 | }, |
| 4375 | 4377 | .register => |reg| { |
| 4376 | 4378 | try self.spillEflagsIfOccupied(); |
| 4377 | 4379 | try self.asmRegisterImmediate(.@"test", reg, Immediate.u(1)); |
| 4378 | | return self.addInst(.{ |
| 4379 | | .tag = .jcc, |
| 4380 | | .ops = .inst_cc, |
| 4381 | | .data = .{ .inst_cc = .{ |
| 4382 | | .inst = undefined, |
| 4383 | | .cc = .e, |
| 4384 | | } }, |
| 4385 | | }); |
| 4380 | return self.asmJccReloc(undefined, .e); |
| 4386 | 4381 | }, |
| 4387 | 4382 | .immediate, |
| 4388 | 4383 | .stack_offset, |
| ... | ... | @@ -4792,15 +4787,7 @@ fn genCondSwitchMir(self: *Self, ty: Type, condition: MCValue, case: MCValue) !u |
| 4792 | 4787 | |
| 4793 | 4788 | const aliased_reg = registerAlias(cond_reg, abi_size); |
| 4794 | 4789 | try self.asmRegisterRegister(.@"test", aliased_reg, aliased_reg); |
| 4795 | | |
| 4796 | | return self.addInst(.{ |
| 4797 | | .tag = .jcc, |
| 4798 | | .ops = .inst_cc, |
| 4799 | | .data = .{ .inst_cc = .{ |
| 4800 | | .inst = undefined, |
| 4801 | | .cc = .ne, |
| 4802 | | } }, |
| 4803 | | }); |
| 4790 | return self.asmJccReloc(undefined, .ne); |
| 4804 | 4791 | }, |
| 4805 | 4792 | .stack_offset => { |
| 4806 | 4793 | try self.spillEflagsIfOccupied(); |
| ... | ... | @@ -5612,7 +5599,6 @@ fn genInlineMemcpy( |
| 5612 | 5599 | |
| 5613 | 5600 | try self.genSetReg(Type.usize, count_reg, len); |
| 5614 | 5601 | try self.asmRegisterImmediate(.mov, index_reg, Immediate.u(0)); |
| 5615 | | |
| 5616 | 5602 | const loop_start = try self.addInst(.{ |
| 5617 | 5603 | .tag = .cmp, |
| 5618 | 5604 | .ops = .ri_u, |
| ... | ... | @@ -5621,15 +5607,7 @@ fn genInlineMemcpy( |
| 5621 | 5607 | .imm = 0, |
| 5622 | 5608 | } }, |
| 5623 | 5609 | }); |
| 5624 | | const loop_reloc = try self.addInst(.{ |
| 5625 | | .tag = .jcc, |
| 5626 | | .ops = .inst_cc, |
| 5627 | | .data = .{ .inst_cc = .{ |
| 5628 | | .inst = undefined, |
| 5629 | | .cc = .e, |
| 5630 | | } }, |
| 5631 | | }); |
| 5632 | | |
| 5610 | const loop_reloc = try self.asmJccReloc(undefined, .e); |
| 5633 | 5611 | try self.asmRegisterMemory(.mov, tmp_reg.to8(), Memory.sib(.byte, .{ |
| 5634 | 5612 | .base = src_addr_reg, |
| 5635 | 5613 | .scale_index = .{ |
| ... | ... | @@ -5708,15 +5686,7 @@ fn genInlineMemset( |
| 5708 | 5686 | .imm = -1, |
| 5709 | 5687 | } }, |
| 5710 | 5688 | }); |
| 5711 | | |
| 5712 | | const loop_reloc = try self.addInst(.{ |
| 5713 | | .tag = .jcc, |
| 5714 | | .ops = .inst_cc, |
| 5715 | | .data = .{ .inst_cc = .{ |
| 5716 | | .inst = undefined, |
| 5717 | | .cc = .e, |
| 5718 | | } }, |
| 5719 | | }); |
| 5689 | const loop_reloc = try self.asmJccReloc(undefined, .e); |
| 5720 | 5690 | |
| 5721 | 5691 | switch (value) { |
| 5722 | 5692 | .immediate => |x| { |
Jakub Konka <kubkon@jakubkonka.com> 2023-03-11 09:37:54+01:00
src