authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-10-16 12:27:40+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-10-18 00:36:52+02:00
log0b55393a2f7d6c3ea233eee53067c535f857a62f
treee1262c057ba3c3e6051ea875fea3e742eeb664a5
parent2eca0e42e59fafae839b507148e8a3679d172079
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.debug: add CPU context and DWARF mappings for ve

2 files changed, 98 insertions(+), 0 deletions(-)

lib/std/debug/Dwarf.zig+3
...@@ -1438,6 +1438,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {...@@ -1438,6 +1438,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
1438 .riscv32, .riscv32be, .riscv64, .riscv64be => 65,1438 .riscv32, .riscv32be, .riscv64, .riscv64be => 65,
1439 .s390x => 65,1439 .s390x => 65,
1440 .sparc, .sparc64 => 32,1440 .sparc, .sparc64 => 32,
1441 .ve => 144,
1441 .x86 => 8,1442 .x86 => 8,
1442 .x86_64 => 16,1443 .x86_64 => 16,
1443 else => null,1444 else => null,
...@@ -1455,6 +1456,7 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {...@@ -1455,6 +1456,7 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
1455 .riscv32, .riscv32be, .riscv64, .riscv64be => 8,1456 .riscv32, .riscv32be, .riscv64, .riscv64be => 8,
1456 .s390x => 11,1457 .s390x => 11,
1457 .sparc, .sparc64 => 30,1458 .sparc, .sparc64 => 30,
1459 .ve => 9,
1458 .x86 => 5,1460 .x86 => 5,
1459 .x86_64 => 6,1461 .x86_64 => 6,
1460 else => unreachable,1462 else => unreachable,
...@@ -1472,6 +1474,7 @@ pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 {...@@ -1472,6 +1474,7 @@ pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 {
1472 .riscv32, .riscv32be, .riscv64, .riscv64be => 2,1474 .riscv32, .riscv32be, .riscv64, .riscv64be => 2,
1473 .s390x => 15,1475 .s390x => 15,
1474 .sparc, .sparc64 => 14,1476 .sparc, .sparc64 => 14,
1477 .ve => 11,
1475 .x86 => 4,1478 .x86 => 4,
1476 .x86_64 => 7,1479 .x86_64 => 7,
1477 else => unreachable,1480 else => unreachable,
lib/std/debug/cpu_context.zig+95
...@@ -12,6 +12,7 @@ else switch (native_arch) {...@@ -12,6 +12,7 @@ else switch (native_arch) {
12 .powerpc, .powerpcle, .powerpc64, .powerpc64le => Powerpc,12 .powerpc, .powerpcle, .powerpc64, .powerpc64le => Powerpc,
13 .sparc, .sparc64 => Sparc,13 .sparc, .sparc64 => Sparc,
14 .riscv32, .riscv32be, .riscv64, .riscv64be => Riscv,14 .riscv32, .riscv32be, .riscv64, .riscv64be => Riscv,
15 .ve => Ve,
15 .s390x => S390x,16 .s390x => S390x,
16 .x86 => X86,17 .x86 => X86,
17 .x86_64 => X86_64,18 .x86_64 => X86_64,
...@@ -1126,6 +1127,100 @@ const S390x = extern struct {...@@ -1126,6 +1127,100 @@ const S390x = extern struct {
1126 }1127 }
1127};1128};
11281129
1130/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
1131const Ve = extern struct {
1132 s: [64]u64,
1133 ic: u64,
1134
1135 pub inline fn current() Ve {
1136 var ctx: Ve = undefined;
1137 asm volatile (
1138 \\ st %%s0, 0(, %%s8)
1139 \\ st %%s1, 8(, %%s8)
1140 \\ st %%s2, 16(, %%s8)
1141 \\ st %%s3, 24(, %%s8)
1142 \\ st %%s4, 32(, %%s8)
1143 \\ st %%s5, 40(, %%s8)
1144 \\ st %%s6, 48(, %%s8)
1145 \\ st %%s7, 56(, %%s8)
1146 \\ st %%s8, 64(, %%s8)
1147 \\ st %%s9, 72(, %%s8)
1148 \\ st %%s10, 80(, %%s8)
1149 \\ st %%s11, 88(, %%s8)
1150 \\ st %%s12, 96(, %%s8)
1151 \\ st %%s13, 104(, %%s8)
1152 \\ st %%s14, 112(, %%s8)
1153 \\ st %%s15, 120(, %%s8)
1154 \\ st %%s16, 128(, %%s8)
1155 \\ st %%s17, 136(, %%s8)
1156 \\ st %%s18, 144(, %%s8)
1157 \\ st %%s19, 152(, %%s8)
1158 \\ st %%s20, 160(, %%s8)
1159 \\ st %%s21, 168(, %%s8)
1160 \\ st %%s22, 176(, %%s8)
1161 \\ st %%s23, 184(, %%s8)
1162 \\ st %%s24, 192(, %%s8)
1163 \\ st %%s25, 200(, %%s8)
1164 \\ st %%s26, 208(, %%s8)
1165 \\ st %%s27, 216(, %%s8)
1166 \\ st %%s28, 224(, %%s8)
1167 \\ st %%s29, 232(, %%s8)
1168 \\ st %%s30, 240(, %%s8)
1169 \\ st %%s31, 248(, %%s8)
1170 \\ st %%s32, 256(, %%s8)
1171 \\ st %%s33, 264(, %%s8)
1172 \\ st %%s34, 272(, %%s8)
1173 \\ st %%s35, 280(, %%s8)
1174 \\ st %%s36, 288(, %%s8)
1175 \\ st %%s37, 296(, %%s8)
1176 \\ st %%s38, 304(, %%s8)
1177 \\ st %%s39, 312(, %%s8)
1178 \\ st %%s40, 320(, %%s8)
1179 \\ st %%s41, 328(, %%s8)
1180 \\ st %%s42, 336(, %%s8)
1181 \\ st %%s43, 344(, %%s8)
1182 \\ st %%s44, 352(, %%s8)
1183 \\ st %%s45, 360(, %%s8)
1184 \\ st %%s46, 368(, %%s8)
1185 \\ st %%s47, 376(, %%s8)
1186 \\ st %%s48, 384(, %%s8)
1187 \\ st %%s49, 392(, %%s8)
1188 \\ st %%s50, 400(, %%s8)
1189 \\ st %%s51, 408(, %%s8)
1190 \\ st %%s52, 416(, %%s8)
1191 \\ st %%s53, 424(, %%s8)
1192 \\ st %%s54, 432(, %%s8)
1193 \\ st %%s55, 440(, %%s8)
1194 \\ st %%s56, 448(, %%s8)
1195 \\ st %%s57, 456(, %%s8)
1196 \\ st %%s58, 464(, %%s8)
1197 \\ st %%s59, 472(, %%s8)
1198 \\ st %%s60, 480(, %%s8)
1199 \\ st %%s61, 488(, %%s8)
1200 \\ st %%s62, 496(, %%s8)
1201 \\ st %%s63, 504(, %%s8)
1202 \\ br.l 1f
1203 \\1:
1204 \\ st %%lr, 512(, %%s8)
1205 :
1206 : [ctx] "{s8}" (&ctx),
1207 : .{ .s10 = true, .memory = true });
1208 return ctx;
1209 }
1210
1211 pub fn dwarfRegisterBytes(ctx: *Ve, register_num: u16) DwarfRegisterError![]u8 {
1212 switch (register_num) {
1213 0...63 => return @ptrCast(&ctx.s[register_num]),
1214 144 => return @ptrCast(&ctx.ic),
1215
1216 64...127 => return error.UnsupportedRegister, // v0 - v63
1217 128...143 => return error.UnsupportedRegister, // vm0 - vm15
1218
1219 else => return error.InvalidRegister,
1220 }
1221 }
1222};
1223
1129/// The native operating system's `ucontext_t` as seen in the third argument to signal handlers.1224/// The native operating system's `ucontext_t` as seen in the third argument to signal handlers.
1130///1225///
1131/// These are dramatically simplified since we only need general-purpose registers and don't care1226/// These are dramatically simplified since we only need general-purpose registers and don't care