Commit 0c1b9992fd1d3c20595304c9e9b87c6053c24f45 | zig

author	Andrew Kelley <andrew@ziglang.org> 2024-02-12 12:18:03-08:00
committer	GitHub <noreply@github.com> 2024-02-12 12:18:03-08:00
log	0c1b9992fd1d3c20595304c9e9b87c6053c24f45
tree	82f7aef2294f86d981488d564b2ccd626d4e829a
parent	f995c1b08ab72897cadbb6a365fb04afb8ea9ca1
parent	e27db373ec276f7839fac0a024b92a0945b5f905
signature	Signed by PGP key B5690EEEBB952194

Merge pull request #18821 from jacobly0/x86_64-tests

x86_64: pass more tests

23 files changed, 10368 insertions(+), 550 deletions(-)

lib
- compiler_rt
  - udivmodei4.zig
- std
  - Random
    Xoshiro256.zig
  - crypto
    aes_ocb.zig
    ecdsa.zig
    ff.zig
    pcurves
    p384.zig
    secp256k1.zig
  - fmt.zig
  - math
    big
    int_test.zig
    log10.zig
    nextafter.zig
src
- arch
  - x86_64
    CodeGen.zig
    Encoding.zig
    Mir.zig
    abi.zig
    encodings.zig
- codegen
  - llvm.zig
test
- behavior
- c_abi
  - cfuncs.c
  - main.zig

lib/compiler_rt/udivmodei4.zig+6-7

 @@ -114,23 +114,22 @@ fn divmod(q: ?[]u32, r: ?[]u32, u: []const u32, v: []const u32) !void {
 pub fn __udivei4(r_q: [*]u32, u_p: [*]const u32, v_p: [*]const u32, bits: usize) callconv(.C) void {
     @setRuntimeSafety(builtin.is_test);
-    const u = u_p[0 .. bits / 32];
+    const u = u_p[0 .. std.math.divCeil(usize, bits, 32) catch unreachable];
-    const v = v_p[0 .. bits / 32];
+    const v = v_p[0 .. std.math.divCeil(usize, bits, 32) catch unreachable];
-    const q = r_q[0 .. bits / 32];
+    const q = r_q[0 .. std.math.divCeil(usize, bits, 32) catch unreachable];
     @call(.always_inline, divmod, .{ q, null, u, v }) catch unreachable;
 }
 pub fn __umodei4(r_p: [*]u32, u_p: [*]const u32, v_p: [*]const u32, bits: usize) callconv(.C) void {
     @setRuntimeSafety(builtin.is_test);
-    const u = u_p[0 .. bits / 32];
+    const u = u_p[0 .. std.math.divCeil(usize, bits, 32) catch unreachable];
-    const v = v_p[0 .. bits / 32];
+    const v = v_p[0 .. std.math.divCeil(usize, bits, 32) catch unreachable];
-    const r = r_p[0 .. bits / 32];
+    const r = r_p[0 .. std.math.divCeil(usize, bits, 32) catch unreachable];
     @call(.always_inline, divmod, .{ null, r, u, v }) catch unreachable;
 }
 test "__udivei4/__umodei4" {
     if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
-    if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
     const RndGen = std.Random.DefaultPrng;
     var rnd = RndGen.init(42);

lib/std/Random/Xoshiro256.zig-1

...	@@ -90,7 +90,6 @@ pub fn fill(self: *Xoshiro256, buf: []u8) void {	...	@@ -90,7 +90,6 @@ pub fn fill(self: *Xoshiro256, buf: []u8) void {
90		90
91	test "xoroshiro sequence" {	91	test "xoroshiro sequence" {
92	if (@import("builtin").zig_backend == .stage2_c) return error.SkipZigTest;	92	if (@import("builtin").zig_backend == .stage2_c) return error.SkipZigTest;
93	if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
94		93
95	var r = Xoshiro256.init(0);	94	var r = Xoshiro256.init(0);
96		95

lib/std/crypto/aes_ocb.zig-4

lib/std/crypto/ecdsa.zig-1

...	@@ -389,7 +389,6 @@ test "ECDSA - Basic operations over EcdsaP384Sha384" {	...	@@ -389,7 +389,6 @@ test "ECDSA - Basic operations over EcdsaP384Sha384" {
389		389
390	test "ECDSA - Basic operations over Secp256k1" {	390	test "ECDSA - Basic operations over Secp256k1" {
391	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;	391	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
392	if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
393		392
394	const Scheme = EcdsaSecp256k1Sha256oSha256;	393	const Scheme = EcdsaSecp256k1Sha256oSha256;
395	const kp = try Scheme.KeyPair.create(null);	394	const kp = try Scheme.KeyPair.create(null);

lib/std/crypto/ff.zig+1-2

 @@ -907,9 +907,8 @@ const ct_unprotected = struct {
     }
 };
-test {
+test "finite field arithmetic" {
     if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
-    if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
     const M = Modulus(256);
     const m = try M.fromPrimitive(u256, 3429938563481314093726330772853735541133072814650493833233);

lib/std/crypto/pcurves/p384.zig-1

...	@@ -479,7 +479,6 @@ pub const AffineCoordinates = struct {	...	@@ -479,7 +479,6 @@ pub const AffineCoordinates = struct {
479		479
480	test {	480	test {
481	if (@import("builtin").zig_backend == .stage2_c) return error.SkipZigTest;	481	if (@import("builtin").zig_backend == .stage2_c) return error.SkipZigTest;
482	if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
483		482
484	_ = @import("tests/p384.zig");	483	_ = @import("tests/p384.zig");
485	}	484	}

lib/std/crypto/pcurves/secp256k1.zig-1

...	@@ -557,7 +557,6 @@ pub const AffineCoordinates = struct {	...	@@ -557,7 +557,6 @@ pub const AffineCoordinates = struct {
557		557
558	test {	558	test {
559	if (@import("builtin").zig_backend == .stage2_c) return error.SkipZigTest;	559	if (@import("builtin").zig_backend == .stage2_c) return error.SkipZigTest;
560	if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
561		560
562	_ = @import("tests/secp256k1.zig");	561	_ = @import("tests/secp256k1.zig");
563	}	562	}

lib/std/fmt.zig-2

...	@@ -2790,8 +2790,6 @@ test "positional/alignment/width/precision" {	...	@@ -2790,8 +2790,6 @@ test "positional/alignment/width/precision" {
2790	}	2790	}
2791		2791
2792	test "vector" {	2792	test "vector" {
2793	if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
2794
2795	if (builtin.target.cpu.arch == .riscv64) {	2793	if (builtin.target.cpu.arch == .riscv64) {
2796	// https://github.com/ziglang/zig/issues/4486	2794	// https://github.com/ziglang/zig/issues/4486
2797	return error.SkipZigTest;	2795	return error.SkipZigTest;

lib/std/math/big/int_test.zig-5

lib/std/math/log10.zig+19-65

...	@@ -1,10 +1,6 @@	...	@@ -1,10 +1,6 @@
1	const std = @import("../std.zig");	1	const std = @import("../std.zig");
2	const builtin = @import("builtin");	2	const builtin = @import("builtin");
3	const math = std.math;
4	const testing = std.testing;	3	const testing = std.testing;
5	const maxInt = std.math.maxInt;
6	const assert = std.debug.assert;
7	const Log2Int = std.math.Log2Int;
8		4
9	/// Returns the base-10 logarithm of x.	5	/// Returns the base-10 logarithm of x.
10	///	6	///
...	@@ -38,13 +34,13 @@ pub fn log10(x: anytype) @TypeOf(x) {	...	@@ -38,13 +34,13 @@ pub fn log10(x: anytype) @TypeOf(x) {
38		34
39	/// Return the log base 10 of integer value x, rounding down to the	35	/// Return the log base 10 of integer value x, rounding down to the
40	/// nearest integer.	36	/// nearest integer.
41	pub fn log10_int(x: anytype) Log2Int(@TypeOf(x)) {	37	pub fn log10_int(x: anytype) std.math.Log2Int(@TypeOf(x)) {
42	const T = @TypeOf(x);	38	const T = @TypeOf(x);
43	const OutT = Log2Int(T);	39	const OutT = std.math.Log2Int(T);
44	if (@typeInfo(T) != .Int or @typeInfo(T).Int.signedness != .unsigned)	40	if (@typeInfo(T) != .Int or @typeInfo(T).Int.signedness != .unsigned)
45	@compileError("log10_int requires an unsigned integer, found " ++ @typeName(T));	41	@compileError("log10_int requires an unsigned integer, found " ++ @typeName(T));
46		42
47	assert(x != 0);	43	std.debug.assert(x != 0);
48		44
49	const bit_size = @typeInfo(T).Int.bits;	45	const bit_size = @typeInfo(T).Int.bits;
50		46
...	@@ -133,18 +129,7 @@ inline fn less_than_5(x: u32) u32 {	...	@@ -133,18 +129,7 @@ inline fn less_than_5(x: u32) u32 {
133	return (((x + C1) & (x + C2)) ^ ((x + C3) & (x + C4))) >> 17;	129	return (((x + C1) & (x + C2)) ^ ((x + C3) & (x + C4))) >> 17;
134	}	130	}
135		131
136	fn oldlog10(x: anytype) u8 {	132	test log10_int {
137	return @as(u8, @intFromFloat(@log10(@as(f64, @floatFromInt(x)))));
138	}
139
140	test "oldlog10 doesn't work" {
141	try testing.expect(14 != oldlog10(pow10(15) - 1));
142
143	// log10(10**15 -1) should indeed be 14
144	try testing.expect(14 == log10_int(@as(u64, pow10(15) - 1)));
145	}
146
147	test "log10_int vs old implementation" {
148	if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO	133	if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
149	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO	134	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
150	if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO	135	if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
...	@@ -152,53 +137,22 @@ test "log10_int vs old implementation" {	...	@@ -152,53 +137,22 @@ test "log10_int vs old implementation" {
152	if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO	137	if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
153	if (builtin.zig_backend == .stage2_llvm and comptime builtin.target.isWasm()) return error.SkipZigTest; // TODO	138	if (builtin.zig_backend == .stage2_llvm and comptime builtin.target.isWasm()) return error.SkipZigTest; // TODO
154		139
155	const int_types = .{ u8, u16, u32, u64, u128 };	140	inline for (
156		141	.{ u8, u16, u32, u64, u128, u256, u512 },
157	inline for (int_types) \|T\| {	142	.{ 2, 4, 9, 19, 38, 77, 154 },
158	const last = @min(maxInt(T), 100_000);	143	) \|T, max_exponent\| {
159	for (1..last) \|i\| {	144	for (0..max_exponent + 1) \|exponent_usize\| {
160	const x = @as(T, @intCast(i));	145	const exponent: std.math.Log2Int(T) = @intCast(exponent_usize);
161	try testing.expectEqual(oldlog10(x), log10_int(x));	146	const power_of_ten = try std.math.powi(T, 10, exponent);
162	}	147
163		148	if (exponent > 0) {
164	const max_int: T = maxInt(T);	149	try testing.expectEqual(exponent - 1, log10_int(power_of_ten - 9));
165	try testing.expectEqual(oldlog10(max_int), log10_int(max_int));	150	try testing.expectEqual(exponent - 1, log10_int(power_of_ten - 1));
166	}
167	}
168
169	test "log10_int close to powers of 10" {
170	if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
171	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
172	if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
173	if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
174	if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
175	if (builtin.zig_backend == .stage2_llvm and comptime builtin.target.isWasm()) return error.SkipZigTest; // TODO
176	if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
177
178	const int_types = .{ u8, u16, u32, u64, u128, u256, u512 };
179	const max_log_values: [7]usize = .{ 2, 4, 9, 19, 38, 77, 154 };
180
181	inline for (int_types, max_log_values) \|T, expected_max_ilog\| {
182	const max_val: T = maxInt(T);
183
184	try testing.expectEqual(expected_max_ilog, log10_int(max_val));
185
186	for (0..(expected_max_ilog + 1)) \|idx\| {
187	const i = @as(T, @intCast(idx));
188	const p: T = try math.powi(T, 10, i);
189
190	const b = @as(Log2Int(T), @intCast(i));
191
192	if (p >= 10) {
193	try testing.expectEqual(b - 1, log10_int(p - 9));
194	try testing.expectEqual(b - 1, log10_int(p - 1));
195	}
196
197	try testing.expectEqual(b, log10_int(p));
198	try testing.expectEqual(b, log10_int(p + 1));
199	if (p >= 10) {
200	try testing.expectEqual(b, log10_int(p + 9));
201	}	151	}
		152	try testing.expectEqual(exponent, log10_int(power_of_ten));
		153	try testing.expectEqual(exponent, log10_int(power_of_ten + 1));
		154	try testing.expectEqual(exponent, log10_int(power_of_ten + 8));
202	}	155	}
		156	try testing.expectEqual(max_exponent, log10_int(@as(T, std.math.maxInt(T))));
203	}	157	}
204	}	158	}

lib/std/math/nextafter.zig-2

...	@@ -102,8 +102,6 @@ fn nextAfterFloat(comptime T: type, x: T, y: T) T {	...	@@ -102,8 +102,6 @@ fn nextAfterFloat(comptime T: type, x: T, y: T) T {
102	}	102	}
103		103
104	test "math.nextAfter.int" {	104	test "math.nextAfter.int" {
105	if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
106
107	try expect(nextAfter(i0, 0, 0) == 0);	105	try expect(nextAfter(i0, 0, 0) == 0);
108	try expect(nextAfter(u0, 0, 0) == 0);	106	try expect(nextAfter(u0, 0, 0) == 0);
109	try expect(nextAfter(i1, 0, 0) == 0);	107	try expect(nextAfter(i1, 0, 0) == 0);

src/arch/x86_64/CodeGen.zig+1749-450

...	@@ -221,6 +221,8 @@ pub const MCValue = union(enum) {	...	@@ -221,6 +221,8 @@ pub const MCValue = union(enum) {
221	/// The address of an offset from a frame index	221	/// The address of an offset from a frame index
222	/// Payload is a frame address.	222	/// Payload is a frame address.
223	lea_frame: FrameAddr,	223	lea_frame: FrameAddr,
		224	/// Supports integer_per_element abi
		225	elementwise_regs_then_frame: packed struct { regs: u3 = 0, frame_off: i29 = 0, frame_index: FrameIndex },
224	/// This indicates that we have already allocated a frame index for this instruction,	226	/// This indicates that we have already allocated a frame index for this instruction,
225	/// but it has not been spilled there yet in the current control flow.	227	/// but it has not been spilled there yet in the current control flow.
226	/// Payload is a frame index.	228	/// Payload is a frame index.
...	@@ -300,6 +302,7 @@ pub const MCValue = union(enum) {	...	@@ -300,6 +302,7 @@ pub const MCValue = union(enum) {
300	.lea_got,	302	.lea_got,
301	.lea_tlv,	303	.lea_tlv,
302	.lea_frame,	304	.lea_frame,
		305	.elementwise_regs_then_frame,
303	.reserved_frame,	306	.reserved_frame,
304	.air_ref,	307	.air_ref,
305	=> unreachable, // not in memory	308	=> unreachable, // not in memory
...	@@ -332,6 +335,7 @@ pub const MCValue = union(enum) {	...	@@ -332,6 +335,7 @@ pub const MCValue = union(enum) {
332	.load_tlv,	335	.load_tlv,
333	.load_frame,	336	.load_frame,
334	.load_symbol,	337	.load_symbol,
		338	.elementwise_regs_then_frame,
335	.reserved_frame,	339	.reserved_frame,
336	.air_ref,	340	.air_ref,
337	=> unreachable, // not dereferenceable	341	=> unreachable, // not dereferenceable
...	@@ -352,6 +356,7 @@ pub const MCValue = union(enum) {	...	@@ -352,6 +356,7 @@ pub const MCValue = union(enum) {
352	.unreach,	356	.unreach,
353	.dead,	357	.dead,
354	.undef,	358	.undef,
		359	.elementwise_regs_then_frame,
355	.reserved_frame,	360	.reserved_frame,
356	.air_ref,	361	.air_ref,
357	=> unreachable, // not valid	362	=> unreachable, // not valid
...	@@ -403,8 +408,8 @@ pub const MCValue = union(enum) {	...	@@ -403,8 +408,8 @@ pub const MCValue = union(enum) {
403	.load_tlv,	408	.load_tlv,
404	.lea_tlv,	409	.lea_tlv,
405	.lea_frame,	410	.lea_frame,
		411	.elementwise_regs_then_frame,
406	.reserved_frame,	412	.reserved_frame,
407	.air_ref,
408	.lea_symbol,	413	.lea_symbol,
409	=> unreachable,	414	=> unreachable,
410	.memory => \|addr\| if (math.cast(i32, @as(i64, @bitCast(addr)))) \|small_addr\| .{	415	.memory => \|addr\| if (math.cast(i32, @as(i64, @bitCast(addr)))) \|small_addr\| .{
...	@@ -441,6 +446,7 @@ pub const MCValue = union(enum) {	...	@@ -441,6 +446,7 @@ pub const MCValue = union(enum) {
441	} },	446	} },
442	};	447	};
443	},	448	},
		449	.air_ref => \|ref\| (try function.resolveInst(ref)).mem(function, size),
444	};	450	};
445	}	451	}
446		452
...	@@ -470,6 +476,7 @@ pub const MCValue = union(enum) {	...	@@ -470,6 +476,7 @@ pub const MCValue = union(enum) {
470	.load_tlv => \|pl\| try writer.print("[tlv:{d}]", .{pl}),	476	.load_tlv => \|pl\| try writer.print("[tlv:{d}]", .{pl}),
471	.lea_tlv => \|pl\| try writer.print("tlv:{d}", .{pl}),	477	.lea_tlv => \|pl\| try writer.print("tlv:{d}", .{pl}),
472	.load_frame => \|pl\| try writer.print("[{} + 0x{x}]", .{ pl.index, pl.off }),	478	.load_frame => \|pl\| try writer.print("[{} + 0x{x}]", .{ pl.index, pl.off }),
		479	.elementwise_regs_then_frame => \|pl\| try writer.print("elementwise:{d}:[{} + 0x{x}]", .{ pl.regs, pl.frame_index, pl.frame_off }),
473	.lea_frame => \|pl\| try writer.print("{} + 0x{x}", .{ pl.index, pl.off }),	480	.lea_frame => \|pl\| try writer.print("{} + 0x{x}", .{ pl.index, pl.off }),
474	.reserved_frame => \|pl\| try writer.print("(dead:{})", .{pl}),	481	.reserved_frame => \|pl\| try writer.print("(dead:{})", .{pl}),
475	.air_ref => \|pl\| try writer.print("(air:0x{x})", .{@intFromEnum(pl)}),	482	.air_ref => \|pl\| try writer.print("(air:0x{x})", .{@intFromEnum(pl)}),
...	@@ -502,6 +509,7 @@ const InstTracking = struct {	...	@@ -502,6 +509,7 @@ const InstTracking = struct {
502	.lea_symbol,	509	.lea_symbol,
503	=> result,	510	=> result,
504	.dead,	511	.dead,
		512	.elementwise_regs_then_frame,
505	.reserved_frame,	513	.reserved_frame,
506	.air_ref,	514	.air_ref,
507	=> unreachable,	515	=> unreachable,
...	@@ -537,7 +545,7 @@ const InstTracking = struct {	...	@@ -537,7 +545,7 @@ const InstTracking = struct {
537	else => unreachable,	545	else => unreachable,
538	}	546	}
539	tracking_log.debug("spill %{d} from {} to {}", .{ inst, self.short, self.long });	547	tracking_log.debug("spill %{d} from {} to {}", .{ inst, self.short, self.long });
540	try function.genCopy(function.typeOfIndex(inst), self.long, self.short);	548	try function.genCopy(function.typeOfIndex(inst), self.long, self.short, .{});
541	}	549	}
542		550
543	fn reuseFrame(self: *InstTracking) void {	551	fn reuseFrame(self: *InstTracking) void {
...	@@ -569,6 +577,7 @@ const InstTracking = struct {	...	@@ -569,6 +577,7 @@ const InstTracking = struct {
569	.register_offset,	577	.register_offset,
570	.register_overflow,	578	.register_overflow,
571	.indirect,	579	.indirect,
		580	.elementwise_regs_then_frame,
572	.reserved_frame,	581	.reserved_frame,
573	.air_ref,	582	.air_ref,
574	=> unreachable,	583	=> unreachable,
...	@@ -614,6 +623,7 @@ const InstTracking = struct {	...	@@ -614,6 +623,7 @@ const InstTracking = struct {
614	.register_offset,	623	.register_offset,
615	.register_overflow,	624	.register_overflow,
616	.indirect,	625	.indirect,
		626	.elementwise_regs_then_frame,
617	.air_ref,	627	.air_ref,
618	=> unreachable,	628	=> unreachable,
619	}	629	}
...	@@ -637,8 +647,8 @@ const InstTracking = struct {	...	@@ -637,8 +647,8 @@ const InstTracking = struct {
637	) !void {	647	) !void {
638	const ty = function.typeOfIndex(inst);	648	const ty = function.typeOfIndex(inst);
639	if ((self.long == .none or self.long == .reserved_frame) and target.long == .load_frame)	649	if ((self.long == .none or self.long == .reserved_frame) and target.long == .load_frame)
640	try function.genCopy(ty, target.long, self.short);	650	try function.genCopy(ty, target.long, self.short, .{});
641	try function.genCopy(ty, target.short, self.short);	651	try function.genCopy(ty, target.short, self.short, .{});
642	}	652	}
643		653
644	fn trackMaterialize(self: *InstTracking, inst: Air.Inst.Index, target: InstTracking) void {	654	fn trackMaterialize(self: *InstTracking, inst: Air.Inst.Index, target: InstTracking) void {
...	@@ -1717,6 +1727,7 @@ fn gen(self: *Self) InnerError!void {	...	@@ -1717,6 +1727,7 @@ fn gen(self: *Self) InnerError!void {
1717	0,	1727	0,
1718	Type.usize,	1728	Type.usize,
1719	self.ret_mcv.long.address().offset(-self.ret_mcv.short.indirect.off),	1729	self.ret_mcv.long.address().offset(-self.ret_mcv.short.indirect.off),
		1730	.{},
1720	);	1731	);
1721	self.ret_mcv.long = .{ .load_frame = .{ .index = frame_index } };	1732	self.ret_mcv.long = .{ .load_frame = .{ .index = frame_index } };
1722	tracking_log.debug("spill {} to {}", .{ self.ret_mcv.long, frame_index });	1733	tracking_log.debug("spill {} to {}", .{ self.ret_mcv.long, frame_index });
...	@@ -1740,6 +1751,7 @@ fn gen(self: *Self) InnerError!void {	...	@@ -1740,6 +1751,7 @@ fn gen(self: *Self) InnerError!void {
1740	@intCast(reg_i * 8),	1751	@intCast(reg_i * 8),
1741	Type.usize,	1752	Type.usize,
1742	.{ .register = reg },	1753	.{ .register = reg },
		1754	.{},
1743	);	1755	);
1744		1756
1745	try self.asmRegisterImmediate(.{ ._, .cmp }, .al, Immediate.u(info.fp_count));	1757	try self.asmRegisterImmediate(.{ ._, .cmp }, .al, Immediate.u(info.fp_count));
...	@@ -1752,9 +1764,10 @@ fn gen(self: *Self) InnerError!void {	...	@@ -1752,9 +1764,10 @@ fn gen(self: *Self) InnerError!void {
1752	@intCast(abi.SysV.c_abi_int_param_regs.len * 8 + reg_i * 16),	1764	@intCast(abi.SysV.c_abi_int_param_regs.len * 8 + reg_i * 16),
1753	vec_2_f64,	1765	vec_2_f64,
1754	.{ .register = reg },	1766	.{ .register = reg },
		1767	.{},
1755	);	1768	);
1756		1769
1757	try self.performReloc(skip_sse_reloc);	1770	self.performReloc(skip_sse_reloc);
1758	},	1771	},
1759	.Win64 => return self.fail("TODO implement gen var arg function for Win64", .{}),	1772	.Win64 => return self.fail("TODO implement gen var arg function for Win64", .{}),
1760	else => unreachable,	1773	else => unreachable,
...	@@ -2006,8 +2019,8 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {	...	@@ -2006,8 +2019,8 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
2006	.load => try self.airLoad(inst),	2019	.load => try self.airLoad(inst),
2007	.loop => try self.airLoop(inst),	2020	.loop => try self.airLoop(inst),
2008	.int_from_ptr => try self.airIntFromPtr(inst),	2021	.int_from_ptr => try self.airIntFromPtr(inst),
2009	.ret => try self.airRet(inst),	2022	.ret => try self.airRet(inst, false),
2010	.ret_safe => try self.airRet(inst), // TODO	2023	.ret_safe => try self.airRet(inst, true),
2011	.ret_load => try self.airRetLoad(inst),	2024	.ret_load => try self.airRetLoad(inst),
2012	.store => try self.airStore(inst, false),	2025	.store => try self.airStore(inst, false),
2013	.store_safe => try self.airStore(inst, true),	2026	.store_safe => try self.airStore(inst, true),
...	@@ -2209,18 +2222,25 @@ fn genLazy(self: *Self, lazy_sym: link.File.LazySymbol) InnerError!void {	...	@@ -2209,18 +2222,25 @@ fn genLazy(self: *Self, lazy_sym: link.File.LazySymbol) InnerError!void {
2209	0,	2222	0,
2210	Type.usize,	2223	Type.usize,
2211	.{ .register_offset = .{ .reg = data_reg, .off = data_off } },	2224	.{ .register_offset = .{ .reg = data_reg, .off = data_off } },
		2225	.{},
		2226	);
		2227	try self.genSetMem(
		2228	.{ .reg = ret_reg },
		2229	8,
		2230	Type.usize,
		2231	.{ .immediate = tag_name.len },
		2232	.{},
2212	);	2233	);
2213	try self.genSetMem(.{ .reg = ret_reg }, 8, Type.usize, .{ .immediate = tag_name.len });
2214		2234
2215	exitlude_jump_reloc.* = try self.asmJmpReloc(undefined);	2235	exitlude_jump_reloc.* = try self.asmJmpReloc(undefined);
2216	try self.performReloc(skip_reloc);	2236	self.performReloc(skip_reloc);
2217		2237
2218	data_off += @intCast(tag_name.len + 1);	2238	data_off += @intCast(tag_name.len + 1);
2219	}	2239	}
2220		2240
2221	try self.airTrap();	2241	try self.airTrap();
2222		2242
2223	for (exitlude_jump_relocs) \|reloc\| try self.performReloc(reloc);	2243	for (exitlude_jump_relocs) \|reloc\| self.performReloc(reloc);
2224	try self.asmOpOnly(.{ ._, .ret });	2244	try self.asmOpOnly(.{ ._, .ret });
2225	},	2245	},
2226	else => return self.fail(	2246	else => return self.fail(
...	@@ -2651,7 +2671,7 @@ pub fn spillRegisters(self: *Self, comptime registers: []const Register) !void {	...	@@ -2651,7 +2671,7 @@ pub fn spillRegisters(self: *Self, comptime registers: []const Register) !void {
2651	/// This can have a side effect of spilling instructions to the stack to free up a register.	2671	/// This can have a side effect of spilling instructions to the stack to free up a register.
2652	fn copyToTmpRegister(self: *Self, ty: Type, mcv: MCValue) !Register {	2672	fn copyToTmpRegister(self: *Self, ty: Type, mcv: MCValue) !Register {
2653	const reg = try self.register_manager.allocReg(null, self.regClassForType(ty));	2673	const reg = try self.register_manager.allocReg(null, self.regClassForType(ty));
2654	try self.genSetReg(reg, ty, mcv);	2674	try self.genSetReg(reg, ty, mcv, .{});
2655	return reg;	2675	return reg;
2656	}	2676	}
2657		2677
...	@@ -2666,7 +2686,7 @@ fn copyToRegisterWithInstTracking(	...	@@ -2666,7 +2686,7 @@ fn copyToRegisterWithInstTracking(
2666	mcv: MCValue,	2686	mcv: MCValue,
2667	) !MCValue {	2687	) !MCValue {
2668	const reg: Register = try self.register_manager.allocReg(reg_owner, self.regClassForType(ty));	2688	const reg: Register = try self.register_manager.allocReg(reg_owner, self.regClassForType(ty));
2669	try self.genSetReg(reg, ty, mcv);	2689	try self.genSetReg(reg, ty, mcv, .{});
2670	return MCValue{ .register = reg };	2690	return MCValue{ .register = reg };
2671	}	2691	}
2672		2692
...	@@ -2919,7 +2939,7 @@ fn airIntCast(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -2919,7 +2939,7 @@ fn airIntCast(self: *Self, inst: Air.Inst.Index) !void {
2919	math.divCeil(u32, src_storage_bits, 64) catch unreachable and	2939	math.divCeil(u32, src_storage_bits, 64) catch unreachable and
2920	self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) src_mcv else dst: {	2940	self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) src_mcv else dst: {
2921	const dst_mcv = try self.allocRegOrMem(inst, true);	2941	const dst_mcv = try self.allocRegOrMem(inst, true);
2922	try self.genCopy(min_ty, dst_mcv, src_mcv);	2942	try self.genCopy(min_ty, dst_mcv, src_mcv, .{});
2923	break :dst dst_mcv;	2943	break :dst dst_mcv;
2924	};	2944	};
2925		2945
...	@@ -2954,7 +2974,7 @@ fn airIntCast(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -2954,7 +2974,7 @@ fn airIntCast(self: *Self, inst: Air.Inst.Index) !void {
2954	if (high_bits > 0) {	2974	if (high_bits > 0) {
2955	try self.truncateRegister(src_ty, high_reg);	2975	try self.truncateRegister(src_ty, high_reg);
2956	const high_ty = if (dst_int_info.bits >= 64) Type.usize else dst_ty;	2976	const high_ty = if (dst_int_info.bits >= 64) Type.usize else dst_ty;
2957	try self.genCopy(high_ty, high_mcv, .{ .register = high_reg });	2977	try self.genCopy(high_ty, high_mcv, .{ .register = high_reg }, .{});
2958	}	2978	}
2959		2979
2960	if (dst_limbs_len > src_limbs_len) try self.genInlineMemset(	2980	if (dst_limbs_len > src_limbs_len) try self.genInlineMemset(
...	@@ -2966,6 +2986,7 @@ fn airIntCast(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -2966,6 +2986,7 @@ fn airIntCast(self: *Self, inst: Air.Inst.Index) !void {
2966	.{ ._r, .sa },	2986	.{ ._r, .sa },
2967	Type.isize,	2987	Type.isize,
2968	extend_mcv,	2988	extend_mcv,
		2989	Type.u8,
2969	.{ .immediate = 63 },	2990	.{ .immediate = 63 },
2970	);	2991	);
2971	break :extend extend_mcv;	2992	break :extend extend_mcv;
...	@@ -2973,6 +2994,7 @@ fn airIntCast(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -2973,6 +2994,7 @@ fn airIntCast(self: *Self, inst: Air.Inst.Index) !void {
2973	.unsigned => .{ .immediate = 0 },	2994	.unsigned => .{ .immediate = 0 },
2974	},	2995	},
2975	.{ .immediate = (dst_limbs_len - src_limbs_len) * 8 },	2996	.{ .immediate = (dst_limbs_len - src_limbs_len) * 8 },
		2997	.{},
2976	);	2998	);
2977		2999
2978	break :result dst_mcv;	3000	break :result dst_mcv;
...	@@ -3006,9 +3028,13 @@ fn airTrunc(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -3006,9 +3028,13 @@ fn airTrunc(self: *Self, inst: Air.Inst.Index) !void {
3006	const dst_locks = self.register_manager.lockRegsAssumeUnused(2, dst_regs);	3028	const dst_locks = self.register_manager.lockRegsAssumeUnused(2, dst_regs);
3007	defer for (dst_locks) \|lock\| self.register_manager.unlockReg(lock);	3029	defer for (dst_locks) \|lock\| self.register_manager.unlockReg(lock);
3008		3030
3009	try self.genCopy(dst_ty, dst_mcv, src_mcv);	3031	try self.genCopy(dst_ty, dst_mcv, src_mcv, .{});
		3032	break :dst dst_mcv;
		3033	} else dst: {
		3034	const dst_mcv = try self.allocRegOrMem(inst, true);
		3035	try self.genCopy(dst_ty, dst_mcv, src_mcv, .{});
3010	break :dst dst_mcv;	3036	break :dst dst_mcv;
3011	} else return self.fail("TODO implement trunc from {} to {}", .{ src_ty.fmt(mod), dst_ty.fmt(mod) });	3037	};
3012		3038
3013	if (dst_ty.zigTypeTag(mod) == .Vector) {	3039	if (dst_ty.zigTypeTag(mod) == .Vector) {
3014	assert(src_ty.zigTypeTag(mod) == .Vector and dst_ty.vectorLen(mod) == src_ty.vectorLen(mod));	3040	assert(src_ty.zigTypeTag(mod) == .Vector and dst_ty.vectorLen(mod) == src_ty.vectorLen(mod));
...	@@ -3082,11 +3108,15 @@ fn airTrunc(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -3082,11 +3108,15 @@ fn airTrunc(self: *Self, inst: Air.Inst.Index) !void {
3082	// when truncating a `u16` to `u5`, for example, those top 3 bits in the result	3108	// when truncating a `u16` to `u5`, for example, those top 3 bits in the result
3083	// have to be removed. this only happens if the dst if not a power-of-two size.	3109	// have to be removed. this only happens if the dst if not a power-of-two size.
3084	if (dst_abi_size <= 8) {	3110	if (dst_abi_size <= 8) {
3085	if (self.regExtraBits(dst_ty) > 0) try self.truncateRegister(dst_ty, dst_mcv.register.to64());	3111	if (self.regExtraBits(dst_ty) > 0) {
		3112	try self.truncateRegister(dst_ty, dst_mcv.register.to64());
		3113	}
3086	} else if (dst_abi_size <= 16) {	3114	} else if (dst_abi_size <= 16) {
3087	const dst_info = dst_ty.intInfo(mod);	3115	const dst_info = dst_ty.intInfo(mod);
3088	const high_ty = try mod.intType(dst_info.signedness, dst_info.bits - 64);	3116	const high_ty = try mod.intType(dst_info.signedness, dst_info.bits - 64);
3089	if (self.regExtraBits(high_ty) > 0) try self.truncateRegister(high_ty, dst_mcv.register_pair[1].to64());	3117	if (self.regExtraBits(high_ty) > 0) {
		3118	try self.truncateRegister(high_ty, dst_mcv.register_pair[1].to64());
		3119	}
3090	}	3120	}
3091		3121
3092	break :result dst_mcv;	3122	break :result dst_mcv;
...	@@ -3116,7 +3146,7 @@ fn airSlice(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -3116,7 +3146,7 @@ fn airSlice(self: *Self, inst: Air.Inst.Index) !void {
3116	const frame_index = try self.allocFrameIndex(FrameAlloc.initSpill(slice_ty, mod));	3146	const frame_index = try self.allocFrameIndex(FrameAlloc.initSpill(slice_ty, mod));
3117		3147
3118	const ptr_ty = self.typeOf(bin_op.lhs);	3148	const ptr_ty = self.typeOf(bin_op.lhs);
3119	try self.genSetMem(.{ .frame = frame_index }, 0, ptr_ty, .{ .air_ref = bin_op.lhs });	3149	try self.genSetMem(.{ .frame = frame_index }, 0, ptr_ty, .{ .air_ref = bin_op.lhs }, .{});
3120		3150
3121	const len_ty = self.typeOf(bin_op.rhs);	3151	const len_ty = self.typeOf(bin_op.rhs);
3122	try self.genSetMem(	3152	try self.genSetMem(
...	@@ -3124,6 +3154,7 @@ fn airSlice(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -3124,6 +3154,7 @@ fn airSlice(self: *Self, inst: Air.Inst.Index) !void {
3124	@intCast(ptr_ty.abiSize(mod)),	3154	@intCast(ptr_ty.abiSize(mod)),
3125	len_ty,	3155	len_ty,
3126	.{ .air_ref = bin_op.rhs },	3156	.{ .air_ref = bin_op.rhs },
		3157	.{},
3127	);	3158	);
3128		3159
3129	const result = MCValue{ .load_frame = .{ .index = frame_index } };	3160	const result = MCValue{ .load_frame = .{ .index = frame_index } };
...	@@ -3161,9 +3192,9 @@ fn airBinOp(self: *Self, inst: Air.Inst.Index, tag: Air.Inst.Tag) !void {	...	@@ -3161,9 +3192,9 @@ fn airBinOp(self: *Self, inst: Air.Inst.Index, tag: Air.Inst.Tag) !void {
3161		3192
3162	const hi_ty = try mod.intType(.unsigned, @intCast((dst_ty.bitSize(mod) - 1) % 64 + 1));	3193	const hi_ty = try mod.intType(.unsigned, @intCast((dst_ty.bitSize(mod) - 1) % 64 + 1));
3163	const hi_mcv = dst_mcv.address().offset(@intCast(bit_size / 64 * 8)).deref();	3194	const hi_mcv = dst_mcv.address().offset(@intCast(bit_size / 64 * 8)).deref();
3164	try self.genSetReg(tmp_reg, hi_ty, hi_mcv);	3195	try self.genSetReg(tmp_reg, hi_ty, hi_mcv, .{});
3165	try self.truncateRegister(dst_ty, tmp_reg);	3196	try self.truncateRegister(dst_ty, tmp_reg);
3166	try self.genCopy(hi_ty, hi_mcv, .{ .register = tmp_reg });	3197	try self.genCopy(hi_ty, hi_mcv, .{ .register = tmp_reg }, .{});
3167	}	3198	}
3168	}	3199	}
3169	}	3200	}
...	@@ -3344,7 +3375,7 @@ fn airMulDivBinOp(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -3344,7 +3375,7 @@ fn airMulDivBinOp(self: *Self, inst: Air.Inst.Index) !void {
3344	.resurrect = true,	3375	.resurrect = true,
3345	.close_scope = true,	3376	.close_scope = true,
3346	});	3377	});
3347	try self.performReloc(signed_div_floor_state.reloc);	3378	self.performReloc(signed_div_floor_state.reloc);
3348	const dst_mcv = try self.genCall(	3379	const dst_mcv = try self.genCall(
3349	.{ .lib = .{	3380	.{ .lib = .{
3350	.return_type = dst_ty.toIntern(),	3381	.return_type = dst_ty.toIntern(),
...	@@ -3429,7 +3460,10 @@ fn airMulDivBinOp(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -3429,7 +3460,10 @@ fn airMulDivBinOp(self: *Self, inst: Air.Inst.Index) !void {
3429	};	3460	};
3430		3461
3431	try self.spillEflagsIfOccupied();	3462	try self.spillEflagsIfOccupied();
3432	try self.spillRegisters(&.{ .rax, .rdx });	3463	try self.spillRegisters(&.{ .rax, .rcx, .rdx });
		3464	const reg_locks = self.register_manager.lockRegsAssumeUnused(3, .{ .rax, .rcx, .rdx });
		3465	defer for (reg_locks) \|lock\| self.register_manager.unlockReg(lock);
		3466
3433	const lhs_mcv = try self.resolveInst(bin_op.lhs);	3467	const lhs_mcv = try self.resolveInst(bin_op.lhs);
3434	const rhs_mcv = try self.resolveInst(bin_op.rhs);	3468	const rhs_mcv = try self.resolveInst(bin_op.rhs);
3435	break :result try self.genMulDivBinOp(tag, inst, dst_ty, src_ty, lhs_mcv, rhs_mcv);	3469	break :result try self.genMulDivBinOp(tag, inst, dst_ty, src_ty, lhs_mcv, rhs_mcv);
...	@@ -3471,10 +3505,22 @@ fn airAddSat(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -3471,10 +3505,22 @@ fn airAddSat(self: *Self, inst: Air.Inst.Index) !void {
3471	const reg_extra_bits = self.regExtraBits(ty);	3505	const reg_extra_bits = self.regExtraBits(ty);
3472	const cc: Condition = if (ty.isSignedInt(mod)) cc: {	3506	const cc: Condition = if (ty.isSignedInt(mod)) cc: {
3473	if (reg_extra_bits > 0) {	3507	if (reg_extra_bits > 0) {
3474	try self.genShiftBinOpMir(.{ ._l, .sa }, ty, dst_mcv, .{ .immediate = reg_extra_bits });	3508	try self.genShiftBinOpMir(
		3509	.{ ._l, .sa },
		3510	ty,
		3511	dst_mcv,
		3512	Type.u8,
		3513	.{ .immediate = reg_extra_bits },
		3514	);
3475	}	3515	}
3476	try self.genSetReg(limit_reg, ty, dst_mcv);	3516	try self.genSetReg(limit_reg, ty, dst_mcv, .{});
3477	try self.genShiftBinOpMir(.{ ._r, .sa }, ty, limit_mcv, .{ .immediate = reg_bits - 1 });	3517	try self.genShiftBinOpMir(
		3518	.{ ._r, .sa },
		3519	ty,
		3520	limit_mcv,
		3521	Type.u8,
		3522	.{ .immediate = reg_bits - 1 },
		3523	);
3478	try self.genBinOpMir(.{ ._, .xor }, ty, limit_mcv, .{	3524	try self.genBinOpMir(.{ ._, .xor }, ty, limit_mcv, .{
3479	.immediate = (@as(u64, 1) << @intCast(reg_bits - 1)) - 1,	3525	.immediate = (@as(u64, 1) << @intCast(reg_bits - 1)) - 1,
3480	});	3526	});
...	@@ -3488,6 +3534,7 @@ fn airAddSat(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -3488,6 +3534,7 @@ fn airAddSat(self: *Self, inst: Air.Inst.Index) !void {
3488	.{ ._l, .sa },	3534	.{ ._l, .sa },
3489	ty,	3535	ty,
3490	shifted_rhs_mcv,	3536	shifted_rhs_mcv,
		3537	Type.u8,
3491	.{ .immediate = reg_extra_bits },	3538	.{ .immediate = reg_extra_bits },
3492	);	3539	);
3493	try self.genBinOpMir(.{ ._, .add }, ty, dst_mcv, shifted_rhs_mcv);	3540	try self.genBinOpMir(.{ ._, .add }, ty, dst_mcv, shifted_rhs_mcv);
...	@@ -3496,7 +3543,7 @@ fn airAddSat(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -3496,7 +3543,7 @@ fn airAddSat(self: *Self, inst: Air.Inst.Index) !void {
3496	} else cc: {	3543	} else cc: {
3497	try self.genSetReg(limit_reg, ty, .{	3544	try self.genSetReg(limit_reg, ty, .{
3498	.immediate = @as(u64, math.maxInt(u64)) >> @intCast(64 - ty.bitSize(mod)),	3545	.immediate = @as(u64, math.maxInt(u64)) >> @intCast(64 - ty.bitSize(mod)),
3499	});	3546	}, .{});
3500		3547
3501	try self.genBinOpMir(.{ ._, .add }, ty, dst_mcv, rhs_mcv);	3548	try self.genBinOpMir(.{ ._, .add }, ty, dst_mcv, rhs_mcv);
3502	if (reg_extra_bits > 0) {	3549	if (reg_extra_bits > 0) {
...	@@ -3513,9 +3560,13 @@ fn airAddSat(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -3513,9 +3560,13 @@ fn airAddSat(self: *Self, inst: Air.Inst.Index) !void {
3513	registerAlias(limit_reg, cmov_abi_size),	3560	registerAlias(limit_reg, cmov_abi_size),
3514	);	3561	);
3515		3562
3516	if (reg_extra_bits > 0 and ty.isSignedInt(mod)) {	3563	if (reg_extra_bits > 0 and ty.isSignedInt(mod)) try self.genShiftBinOpMir(
3517	try self.genShiftBinOpMir(.{ ._r, .sa }, ty, dst_mcv, .{ .immediate = reg_extra_bits });	3564	.{ ._r, .sa },
3518	}	3565	ty,
		3566	dst_mcv,
		3567	Type.u8,
		3568	.{ .immediate = reg_extra_bits },
		3569	);
3519		3570
3520	return self.finishAir(inst, dst_mcv, .{ bin_op.lhs, bin_op.rhs, .none });	3571	return self.finishAir(inst, dst_mcv, .{ bin_op.lhs, bin_op.rhs, .none });
3521	}	3572	}
...	@@ -3554,10 +3605,22 @@ fn airSubSat(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -3554,10 +3605,22 @@ fn airSubSat(self: *Self, inst: Air.Inst.Index) !void {
3554	const reg_extra_bits = self.regExtraBits(ty);	3605	const reg_extra_bits = self.regExtraBits(ty);
3555	const cc: Condition = if (ty.isSignedInt(mod)) cc: {	3606	const cc: Condition = if (ty.isSignedInt(mod)) cc: {
3556	if (reg_extra_bits > 0) {	3607	if (reg_extra_bits > 0) {
3557	try self.genShiftBinOpMir(.{ ._l, .sa }, ty, dst_mcv, .{ .immediate = reg_extra_bits });	3608	try self.genShiftBinOpMir(
		3609	.{ ._l, .sa },
		3610	ty,
		3611	dst_mcv,
		3612	Type.u8,
		3613	.{ .immediate = reg_extra_bits },
		3614	);
3558	}	3615	}
3559	try self.genSetReg(limit_reg, ty, dst_mcv);	3616	try self.genSetReg(limit_reg, ty, dst_mcv, .{});
3560	try self.genShiftBinOpMir(.{ ._r, .sa }, ty, limit_mcv, .{ .immediate = reg_bits - 1 });	3617	try self.genShiftBinOpMir(
		3618	.{ ._r, .sa },
		3619	ty,
		3620	limit_mcv,
		3621	Type.u8,
		3622	.{ .immediate = reg_bits - 1 },
		3623	);
3561	try self.genBinOpMir(.{ ._, .xor }, ty, limit_mcv, .{	3624	try self.genBinOpMir(.{ ._, .xor }, ty, limit_mcv, .{
3562	.immediate = (@as(u64, 1) << @intCast(reg_bits - 1)) - 1,	3625	.immediate = (@as(u64, 1) << @intCast(reg_bits - 1)) - 1,
3563	});	3626	});
...	@@ -3571,13 +3634,14 @@ fn airSubSat(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -3571,13 +3634,14 @@ fn airSubSat(self: *Self, inst: Air.Inst.Index) !void {
3571	.{ ._l, .sa },	3634	.{ ._l, .sa },
3572	ty,	3635	ty,
3573	shifted_rhs_mcv,	3636	shifted_rhs_mcv,
		3637	Type.u8,
3574	.{ .immediate = reg_extra_bits },	3638	.{ .immediate = reg_extra_bits },
3575	);	3639	);
3576	try self.genBinOpMir(.{ ._, .sub }, ty, dst_mcv, shifted_rhs_mcv);	3640	try self.genBinOpMir(.{ ._, .sub }, ty, dst_mcv, shifted_rhs_mcv);
3577	} else try self.genBinOpMir(.{ ._, .sub }, ty, dst_mcv, rhs_mcv);	3641	} else try self.genBinOpMir(.{ ._, .sub }, ty, dst_mcv, rhs_mcv);
3578	break :cc .o;	3642	break :cc .o;
3579	} else cc: {	3643	} else cc: {
3580	try self.genSetReg(limit_reg, ty, .{ .immediate = 0 });	3644	try self.genSetReg(limit_reg, ty, .{ .immediate = 0 }, .{});
3581	try self.genBinOpMir(.{ ._, .sub }, ty, dst_mcv, rhs_mcv);	3645	try self.genBinOpMir(.{ ._, .sub }, ty, dst_mcv, rhs_mcv);
3582	break :cc .c;	3646	break :cc .c;
3583	};	3647	};
...	@@ -3589,9 +3653,13 @@ fn airSubSat(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -3589,9 +3653,13 @@ fn airSubSat(self: *Self, inst: Air.Inst.Index) !void {
3589	registerAlias(limit_reg, cmov_abi_size),	3653	registerAlias(limit_reg, cmov_abi_size),
3590	);	3654	);
3591		3655
3592	if (reg_extra_bits > 0 and ty.isSignedInt(mod)) {	3656	if (reg_extra_bits > 0 and ty.isSignedInt(mod)) try self.genShiftBinOpMir(
3593	try self.genShiftBinOpMir(.{ ._r, .sa }, ty, dst_mcv, .{ .immediate = reg_extra_bits });	3657	.{ ._r, .sa },
3594	}	3658	ty,
		3659	dst_mcv,
		3660	Type.u8,
		3661	.{ .immediate = reg_extra_bits },
		3662	);
3595		3663
3596	return self.finishAir(inst, dst_mcv, .{ bin_op.lhs, bin_op.rhs, .none });	3664	return self.finishAir(inst, dst_mcv, .{ bin_op.lhs, bin_op.rhs, .none });
3597	}	3665	}
...	@@ -3685,9 +3753,9 @@ fn airMulSat(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -3685,9 +3753,9 @@ fn airMulSat(self: *Self, inst: Air.Inst.Index) !void {
3685	.{ty.fmt(mod)},	3753	.{ty.fmt(mod)},
3686	);	3754	);
3687		3755
3688	try self.spillRegisters(&.{ .rax, .rdx });	3756	try self.spillRegisters(&.{ .rax, .rcx, .rdx });
3689	const reg_locks = self.register_manager.lockRegs(2, .{ .rax, .rdx });	3757	const reg_locks = self.register_manager.lockRegsAssumeUnused(3, .{ .rax, .rcx, .rdx });
3690	defer for (reg_locks) \|reg_lock\| if (reg_lock) \|lock\| self.register_manager.unlockReg(lock);	3758	defer for (reg_locks) \|lock\| self.register_manager.unlockReg(lock);
3691		3759
3692	const lhs_mcv = try self.resolveInst(bin_op.lhs);	3760	const lhs_mcv = try self.resolveInst(bin_op.lhs);
3693	const lhs_lock = switch (lhs_mcv) {	3761	const lhs_lock = switch (lhs_mcv) {
...	@@ -3710,9 +3778,15 @@ fn airMulSat(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -3710,9 +3778,15 @@ fn airMulSat(self: *Self, inst: Air.Inst.Index) !void {
3710		3778
3711	const reg_bits = self.regBitSize(ty);	3779	const reg_bits = self.regBitSize(ty);
3712	const cc: Condition = if (ty.isSignedInt(mod)) cc: {	3780	const cc: Condition = if (ty.isSignedInt(mod)) cc: {
3713	try self.genSetReg(limit_reg, ty, lhs_mcv);	3781	try self.genSetReg(limit_reg, ty, lhs_mcv, .{});
3714	try self.genBinOpMir(.{ ._, .xor }, ty, limit_mcv, rhs_mcv);	3782	try self.genBinOpMir(.{ ._, .xor }, ty, limit_mcv, rhs_mcv);
3715	try self.genShiftBinOpMir(.{ ._r, .sa }, ty, limit_mcv, .{ .immediate = reg_bits - 1 });	3783	try self.genShiftBinOpMir(
		3784	.{ ._r, .sa },
		3785	ty,
		3786	limit_mcv,
		3787	Type.u8,
		3788	.{ .immediate = reg_bits - 1 },
		3789	);
3716	try self.genBinOpMir(.{ ._, .xor }, ty, limit_mcv, .{	3790	try self.genBinOpMir(.{ ._, .xor }, ty, limit_mcv, .{
3717	.immediate = (@as(u64, 1) << @intCast(reg_bits - 1)) - 1,	3791	.immediate = (@as(u64, 1) << @intCast(reg_bits - 1)) - 1,
3718	});	3792	});
...	@@ -3720,7 +3794,7 @@ fn airMulSat(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -3720,7 +3794,7 @@ fn airMulSat(self: *Self, inst: Air.Inst.Index) !void {
3720	} else cc: {	3794	} else cc: {
3721	try self.genSetReg(limit_reg, ty, .{	3795	try self.genSetReg(limit_reg, ty, .{
3722	.immediate = @as(u64, math.maxInt(u64)) >> @intCast(64 - reg_bits),	3796	.immediate = @as(u64, math.maxInt(u64)) >> @intCast(64 - reg_bits),
3723	});	3797	}, .{});
3724	break :cc .c;	3798	break :cc .c;
3725	};	3799	};
3726		3800
...	@@ -3747,6 +3821,9 @@ fn airAddSubWithOverflow(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -3747,6 +3821,9 @@ fn airAddSubWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
3747	.Vector => return self.fail("TODO implement add/sub with overflow for Vector type", .{}),	3821	.Vector => return self.fail("TODO implement add/sub with overflow for Vector type", .{}),
3748	.Int => {	3822	.Int => {
3749	try self.spillEflagsIfOccupied();	3823	try self.spillEflagsIfOccupied();
		3824	try self.spillRegisters(&.{ .rcx, .rdi, .rsi });
		3825	const reg_locks = self.register_manager.lockRegsAssumeUnused(3, .{ .rcx, .rdi, .rsi });
		3826	defer for (reg_locks) \|lock\| self.register_manager.unlockReg(lock);
3750		3827
3751	const partial_mcv = try self.genBinOp(null, switch (tag) {	3828	const partial_mcv = try self.genBinOp(null, switch (tag) {
3752	.add_with_overflow => .add,	3829	.add_with_overflow => .add,
...	@@ -3776,12 +3853,14 @@ fn airAddSubWithOverflow(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -3776,12 +3853,14 @@ fn airAddSubWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
3776	@intCast(tuple_ty.structFieldOffset(1, mod)),	3853	@intCast(tuple_ty.structFieldOffset(1, mod)),
3777	Type.u1,	3854	Type.u1,
3778	.{ .eflags = cc },	3855	.{ .eflags = cc },
		3856	.{},
3779	);	3857	);
3780	try self.genSetMem(	3858	try self.genSetMem(
3781	.{ .frame = frame_index },	3859	.{ .frame = frame_index },
3782	@intCast(tuple_ty.structFieldOffset(0, mod)),	3860	@intCast(tuple_ty.structFieldOffset(0, mod)),
3783	ty,	3861	ty,
3784	partial_mcv,	3862	partial_mcv,
		3863	.{},
3785	);	3864	);
3786	break :result .{ .load_frame = .{ .index = frame_index } };	3865	break :result .{ .load_frame = .{ .index = frame_index } };
3787	}	3866	}
...	@@ -3808,8 +3887,10 @@ fn airShlWithOverflow(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -3808,8 +3887,10 @@ fn airShlWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
3808	.Vector => return self.fail("TODO implement shl with overflow for Vector type", .{}),	3887	.Vector => return self.fail("TODO implement shl with overflow for Vector type", .{}),
3809	.Int => {	3888	.Int => {
3810	try self.spillEflagsIfOccupied();	3889	try self.spillEflagsIfOccupied();
		3890	try self.spillRegisters(&.{ .rcx, .rdi, .rsi });
		3891	const reg_locks = self.register_manager.lockRegsAssumeUnused(3, .{ .rcx, .rdi, .rsi });
		3892	defer for (reg_locks) \|lock\| self.register_manager.unlockReg(lock);
3811		3893
3812	try self.register_manager.getReg(.rcx, null);
3813	const lhs = try self.resolveInst(bin_op.lhs);	3894	const lhs = try self.resolveInst(bin_op.lhs);
3814	const rhs = try self.resolveInst(bin_op.rhs);	3895	const rhs = try self.resolveInst(bin_op.rhs);
3815		3896
...	@@ -3849,12 +3930,14 @@ fn airShlWithOverflow(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -3849,12 +3930,14 @@ fn airShlWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
3849	@intCast(tuple_ty.structFieldOffset(1, mod)),	3930	@intCast(tuple_ty.structFieldOffset(1, mod)),
3850	tuple_ty.structFieldType(1, mod),	3931	tuple_ty.structFieldType(1, mod),
3851	.{ .eflags = cc },	3932	.{ .eflags = cc },
		3933	.{},
3852	);	3934	);
3853	try self.genSetMem(	3935	try self.genSetMem(
3854	.{ .frame = frame_index },	3936	.{ .frame = frame_index },
3855	@intCast(tuple_ty.structFieldOffset(0, mod)),	3937	@intCast(tuple_ty.structFieldOffset(0, mod)),
3856	tuple_ty.structFieldType(0, mod),	3938	tuple_ty.structFieldType(0, mod),
3857	partial_mcv,	3939	partial_mcv,
		3940	.{},
3858	);	3941	);
3859	break :result .{ .load_frame = .{ .index = frame_index } };	3942	break :result .{ .load_frame = .{ .index = frame_index } };
3860	}	3943	}
...	@@ -3896,7 +3979,7 @@ fn genSetFrameTruncatedOverflowCompare(	...	@@ -3896,7 +3979,7 @@ fn genSetFrameTruncatedOverflowCompare(
3896	const rest_ty = try mod.intType(.unsigned, int_info.bits - hi_bits);	3979	const rest_ty = try mod.intType(.unsigned, int_info.bits - hi_bits);
3897		3980
3898	const temp_regs =	3981	const temp_regs =
3899	try self.register_manager.allocRegs(3, .{ null, null, null }, abi.RegisterClass.gp);	3982	try self.register_manager.allocRegs(3, .{null} ** 3, abi.RegisterClass.gp);
3900	const temp_locks = self.register_manager.lockRegsAssumeUnused(3, temp_regs);	3983	const temp_locks = self.register_manager.lockRegsAssumeUnused(3, temp_regs);
3901	defer for (temp_locks) \|lock\| self.register_manager.unlockReg(lock);	3984	defer for (temp_locks) \|lock\| self.register_manager.unlockReg(lock);
3902		3985
...	@@ -3909,7 +3992,7 @@ fn genSetFrameTruncatedOverflowCompare(	...	@@ -3909,7 +3992,7 @@ fn genSetFrameTruncatedOverflowCompare(
3909	src_mcv.address().offset(int_info.bits / 64 * 8).deref()	3992	src_mcv.address().offset(int_info.bits / 64 * 8).deref()
3910	else	3993	else
3911	src_mcv;	3994	src_mcv;
3912	try self.genSetReg(scratch_reg, limb_ty, hi_limb_mcv);	3995	try self.genSetReg(scratch_reg, limb_ty, hi_limb_mcv, .{});
3913	try self.truncateRegister(hi_ty, scratch_reg);	3996	try self.truncateRegister(hi_ty, scratch_reg);
3914	try self.genBinOpMir(.{ ._, .cmp }, limb_ty, .{ .register = scratch_reg }, hi_limb_mcv);	3997	try self.genBinOpMir(.{ ._, .cmp }, limb_ty, .{ .register = scratch_reg }, hi_limb_mcv);
3915		3998
...	@@ -3925,18 +4008,26 @@ fn genSetFrameTruncatedOverflowCompare(	...	@@ -3925,18 +4008,26 @@ fn genSetFrameTruncatedOverflowCompare(
3925	}	4008	}
3926		4009
3927	const payload_off: i32 = @intCast(tuple_ty.structFieldOffset(0, mod));	4010	const payload_off: i32 = @intCast(tuple_ty.structFieldOffset(0, mod));
3928	if (hi_limb_off > 0) try self.genSetMem(.{ .frame = frame_index }, payload_off, rest_ty, src_mcv);	4011	if (hi_limb_off > 0) try self.genSetMem(
		4012	.{ .frame = frame_index },
		4013	payload_off,
		4014	rest_ty,
		4015	src_mcv,
		4016	.{},
		4017	);
3929	try self.genSetMem(	4018	try self.genSetMem(
3930	.{ .frame = frame_index },	4019	.{ .frame = frame_index },
3931	payload_off + hi_limb_off,	4020	payload_off + hi_limb_off,
3932	limb_ty,	4021	limb_ty,
3933	.{ .register = scratch_reg },	4022	.{ .register = scratch_reg },
		4023	.{},
3934	);	4024	);
3935	try self.genSetMem(	4025	try self.genSetMem(
3936	.{ .frame = frame_index },	4026	.{ .frame = frame_index },
3937	@intCast(tuple_ty.structFieldOffset(1, mod)),	4027	@intCast(tuple_ty.structFieldOffset(1, mod)),
3938	tuple_ty.structFieldType(1, mod),	4028	tuple_ty.structFieldType(1, mod),
3939	if (overflow_cc) \|_\| .{ .register = overflow_reg.to8() } else .{ .eflags = .ne },	4029	if (overflow_cc) \|_\| .{ .register = overflow_reg.to8() } else .{ .eflags = .ne },
		4030	.{},
3940	);	4031	);
3941	}	4032	}
3942		4033
...	@@ -3950,11 +4041,157 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -3950,11 +4041,157 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
3950	.Vector => return self.fail("TODO implement airMulWithOverflow for {}", .{dst_ty.fmt(mod)}),	4041	.Vector => return self.fail("TODO implement airMulWithOverflow for {}", .{dst_ty.fmt(mod)}),
3951	.Int => result: {	4042	.Int => result: {
3952	const dst_info = dst_ty.intInfo(mod);	4043	const dst_info = dst_ty.intInfo(mod);
		4044	if (dst_info.bits > 128 and dst_info.signedness == .unsigned) {
		4045	const slow_inc = self.hasFeature(.slow_incdec);
		4046	const abi_size: u32 = @intCast(dst_ty.abiSize(mod));
		4047	const limb_len = std.math.divCeil(u32, abi_size, 8) catch unreachable;
		4048
		4049	try self.spillRegisters(&.{ .rax, .rcx, .rdx });
		4050	const reg_locks = self.register_manager.lockRegsAssumeUnused(3, .{ .rax, .rcx, .rdx });
		4051	defer for (reg_locks) \|lock\| self.register_manager.unlockReg(lock);
		4052
		4053	const dst_mcv = try self.allocRegOrMem(inst, false);
		4054	try self.genInlineMemset(
		4055	dst_mcv.address(),
		4056	.{ .immediate = 0 },
		4057	.{ .immediate = tuple_ty.abiSize(mod) },
		4058	.{},
		4059	);
		4060	const lhs_mcv = try self.resolveInst(bin_op.lhs);
		4061	const rhs_mcv = try self.resolveInst(bin_op.rhs);
		4062
		4063	const temp_regs =
		4064	try self.register_manager.allocRegs(4, .{null} ** 4, abi.RegisterClass.gp);
		4065	const temp_locks = self.register_manager.lockRegsAssumeUnused(4, temp_regs);
		4066	defer for (temp_locks) \|lock\| self.register_manager.unlockReg(lock);
		4067
		4068	try self.asmRegisterRegister(.{ ._, .xor }, temp_regs[0].to32(), temp_regs[0].to32());
		4069
		4070	const outer_loop: Mir.Inst.Index = @intCast(self.mir_instructions.len);
		4071	try self.asmRegisterMemory(.{ ._, .mov }, temp_regs[1].to64(), .{
		4072	.base = .{ .frame = rhs_mcv.load_frame.index },
		4073	.mod = .{ .rm = .{
		4074	.size = .qword,
		4075	.index = temp_regs[0].to64(),
		4076	.scale = .@"8",
		4077	.disp = rhs_mcv.load_frame.off,
		4078	} },
		4079	});
		4080	try self.asmRegisterRegister(.{ ._, .@"test" }, temp_regs[1].to64(), temp_regs[1].to64());
		4081	const skip_inner = try self.asmJccReloc(.z, undefined);
		4082
		4083	try self.asmRegisterRegister(.{ ._, .xor }, temp_regs[2].to32(), temp_regs[2].to32());
		4084	try self.asmRegisterRegister(.{ ._, .mov }, temp_regs[3].to32(), temp_regs[0].to32());
		4085	try self.asmRegisterRegister(.{ ._, .xor }, .ecx, .ecx);
		4086	try self.asmRegisterRegister(.{ ._, .xor }, .edx, .edx);
		4087
		4088	const inner_loop: Mir.Inst.Index = @intCast(self.mir_instructions.len);
		4089	try self.asmRegisterImmediate(.{ ._r, .sh }, .cl, Immediate.u(1));
		4090	try self.asmMemoryRegister(.{ ._, .adc }, .{
		4091	.base = .{ .frame = dst_mcv.load_frame.index },
		4092	.mod = .{ .rm = .{
		4093	.size = .qword,
		4094	.index = temp_regs[3].to64(),
		4095	.scale = .@"8",
		4096	.disp = dst_mcv.load_frame.off +
		4097	@as(i32, @intCast(tuple_ty.structFieldOffset(0, mod))),
		4098	} },
		4099	}, .rdx);
		4100	try self.asmSetccRegister(.c, .cl);
		4101
		4102	try self.asmRegisterMemory(.{ ._, .mov }, .rax, .{
		4103	.base = .{ .frame = lhs_mcv.load_frame.index },
		4104	.mod = .{ .rm = .{
		4105	.size = .qword,
		4106	.index = temp_regs[2].to64(),
		4107	.scale = .@"8",
		4108	.disp = lhs_mcv.load_frame.off,
		4109	} },
		4110	});
		4111	try self.asmRegister(.{ ._, .mul }, temp_regs[1].to64());
		4112
		4113	try self.asmRegisterImmediate(.{ ._r, .sh }, .ch, Immediate.u(1));
		4114	try self.asmMemoryRegister(.{ ._, .adc }, .{
		4115	.base = .{ .frame = dst_mcv.load_frame.index },
		4116	.mod = .{ .rm = .{
		4117	.size = .qword,
		4118	.index = temp_regs[3].to64(),
		4119	.scale = .@"8",
		4120	.disp = dst_mcv.load_frame.off +
		4121	@as(i32, @intCast(tuple_ty.structFieldOffset(0, mod))),
		4122	} },
		4123	}, .rax);
		4124	try self.asmSetccRegister(.c, .ch);
		4125
		4126	if (slow_inc) {
		4127	try self.asmRegisterImmediate(.{ ._, .add }, temp_regs[2].to32(), Immediate.u(1));
		4128	try self.asmRegisterImmediate(.{ ._, .add }, temp_regs[3].to32(), Immediate.u(1));
		4129	} else {
		4130	try self.asmRegister(.{ ._, .inc }, temp_regs[2].to32());
		4131	try self.asmRegister(.{ ._, .inc }, temp_regs[3].to32());
		4132	}
		4133	try self.asmRegisterImmediate(
		4134	.{ ._, .cmp },
		4135	temp_regs[3].to32(),
		4136	Immediate.u(limb_len),
		4137	);
		4138	_ = try self.asmJccReloc(.b, inner_loop);
		4139
		4140	try self.asmRegisterRegister(.{ ._, .@"or" }, .rdx, .rcx);
		4141	const overflow = try self.asmJccReloc(.nz, undefined);
		4142	const overflow_loop: Mir.Inst.Index = @intCast(self.mir_instructions.len);
		4143	try self.asmRegisterImmediate(
		4144	.{ ._, .cmp },
		4145	temp_regs[2].to32(),
		4146	Immediate.u(limb_len),
		4147	);
		4148	const no_overflow = try self.asmJccReloc(.nb, undefined);
		4149	if (slow_inc) {
		4150	try self.asmRegisterImmediate(.{ ._, .add }, temp_regs[2].to32(), Immediate.u(1));
		4151	} else {
		4152	try self.asmRegister(.{ ._, .inc }, temp_regs[2].to32());
		4153	}
		4154	try self.asmMemoryImmediate(.{ ._, .cmp }, .{
		4155	.base = .{ .frame = lhs_mcv.load_frame.index },
		4156	.mod = .{ .rm = .{
		4157	.size = .qword,
		4158	.index = temp_regs[2].to64(),
		4159	.scale = .@"8",
		4160	.disp = lhs_mcv.load_frame.off - 8,
		4161	} },
		4162	}, Immediate.u(0));
		4163	_ = try self.asmJccReloc(.z, overflow_loop);
		4164	self.performReloc(overflow);
		4165	try self.asmMemoryImmediate(.{ ._, .mov }, .{
		4166	.base = .{ .frame = dst_mcv.load_frame.index },
		4167	.mod = .{ .rm = .{
		4168	.size = .byte,
		4169	.disp = dst_mcv.load_frame.off +
		4170	@as(i32, @intCast(tuple_ty.structFieldOffset(1, mod))),
		4171	} },
		4172	}, Immediate.u(1));
		4173	self.performReloc(no_overflow);
		4174
		4175	self.performReloc(skip_inner);
		4176	if (slow_inc) {
		4177	try self.asmRegisterImmediate(.{ ._, .add }, temp_regs[0].to32(), Immediate.u(1));
		4178	} else {
		4179	try self.asmRegister(.{ ._, .inc }, temp_regs[0].to32());
		4180	}
		4181	try self.asmRegisterImmediate(
		4182	.{ ._, .cmp },
		4183	temp_regs[0].to32(),
		4184	Immediate.u(limb_len),
		4185	);
		4186	_ = try self.asmJccReloc(.b, outer_loop);
		4187
		4188	break :result dst_mcv;
		4189	}
		4190
3953	const lhs_active_bits = self.activeIntBits(bin_op.lhs);	4191	const lhs_active_bits = self.activeIntBits(bin_op.lhs);
3954	const rhs_active_bits = self.activeIntBits(bin_op.rhs);	4192	const rhs_active_bits = self.activeIntBits(bin_op.rhs);
3955	const src_bits = @max(lhs_active_bits, rhs_active_bits, dst_info.bits / 2);	4193	const src_bits = @max(lhs_active_bits, rhs_active_bits, dst_info.bits / 2);
3956	const src_ty = try mod.intType(dst_info.signedness, src_bits);	4194	const src_ty = try mod.intType(dst_info.signedness, src_bits);
3957
3958	if (src_bits > 64 and src_bits <= 128 and	4195	if (src_bits > 64 and src_bits <= 128 and
3959	dst_info.bits > 64 and dst_info.bits <= 128) switch (dst_info.signedness) {	4196	dst_info.bits > 64 and dst_info.bits <= 128) switch (dst_info.signedness) {
3960	.signed => {	4197	.signed => {
...	@@ -3976,6 +4213,7 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -3976,6 +4213,7 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
3976	@intCast(tuple_ty.structFieldOffset(0, mod)),	4213	@intCast(tuple_ty.structFieldOffset(0, mod)),
3977	tuple_ty.structFieldType(0, mod),	4214	tuple_ty.structFieldType(0, mod),
3978	result,	4215	result,
		4216	.{},
3979	);	4217	);
3980	try self.asmMemoryImmediate(	4218	try self.asmMemoryImmediate(
3981	.{ ._, .cmp },	4219	.{ ._, .cmp },
...	@@ -3987,6 +4225,7 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -3987,6 +4225,7 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
3987	@intCast(tuple_ty.structFieldOffset(1, mod)),	4225	@intCast(tuple_ty.structFieldOffset(1, mod)),
3988	tuple_ty.structFieldType(1, mod),	4226	tuple_ty.structFieldType(1, mod),
3989	.{ .eflags = .ne },	4227	.{ .eflags = .ne },
		4228	.{},
3990	);	4229	);
3991	try self.freeValue(overflow);	4230	try self.freeValue(overflow);
3992	break :result dst_mcv;	4231	break :result dst_mcv;
...	@@ -4098,19 +4337,23 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -4098,19 +4337,23 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
4098	@intCast(tuple_ty.structFieldOffset(0, mod)),	4337	@intCast(tuple_ty.structFieldOffset(0, mod)),
4099	tuple_ty.structFieldType(0, mod),	4338	tuple_ty.structFieldType(0, mod),
4100	.{ .register_pair = .{ .rax, .rdx } },	4339	.{ .register_pair = .{ .rax, .rdx } },
		4340	.{},
4101	);	4341	);
4102	try self.genSetMem(	4342	try self.genSetMem(
4103	.{ .frame = dst_mcv.load_frame.index },	4343	.{ .frame = dst_mcv.load_frame.index },
4104	@intCast(tuple_ty.structFieldOffset(1, mod)),	4344	@intCast(tuple_ty.structFieldOffset(1, mod)),
4105	tuple_ty.structFieldType(1, mod),	4345	tuple_ty.structFieldType(1, mod),
4106	.{ .register = tmp_regs[1] },	4346	.{ .register = tmp_regs[1] },
		4347	.{},
4107	);	4348	);
4108	break :result dst_mcv;	4349	break :result dst_mcv;
4109	},	4350	},
4110	};	4351	};
4111		4352
4112	try self.spillEflagsIfOccupied();	4353	try self.spillEflagsIfOccupied();
4113	try self.spillRegisters(&.{ .rax, .rdx });	4354	try self.spillRegisters(&.{ .rax, .rcx, .rdx, .rdi, .rsi });
		4355	const reg_locks = self.register_manager.lockRegsAssumeUnused(5, .{ .rax, .rcx, .rdx, .rdi, .rsi });
		4356	defer for (reg_locks) \|lock\| self.register_manager.unlockReg(lock);
4114		4357
4115	const cc: Condition = switch (dst_info.signedness) {	4358	const cc: Condition = switch (dst_info.signedness) {
4116	.unsigned => .c,	4359	.unsigned => .c,
...	@@ -4149,12 +4392,14 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -4149,12 +4392,14 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
4149	@intCast(tuple_ty.structFieldOffset(0, mod)),	4392	@intCast(tuple_ty.structFieldOffset(0, mod)),
4150	tuple_ty.structFieldType(0, mod),	4393	tuple_ty.structFieldType(0, mod),
4151	partial_mcv,	4394	partial_mcv,
		4395	.{},
4152	);	4396	);
4153	try self.genSetMem(	4397	try self.genSetMem(
4154	.{ .frame = frame_index },	4398	.{ .frame = frame_index },
4155	@intCast(tuple_ty.structFieldOffset(1, mod)),	4399	@intCast(tuple_ty.structFieldOffset(1, mod)),
4156	tuple_ty.structFieldType(1, mod),	4400	tuple_ty.structFieldType(1, mod),
4157	.{ .immediate = 0 }, // cc being set is impossible	4401	.{ .immediate = 0 }, // cc being set is impossible
		4402	.{},
4158	);	4403	);
4159	} else try self.genSetFrameTruncatedOverflowCompare(	4404	} else try self.genSetFrameTruncatedOverflowCompare(
4160	tuple_ty,	4405	tuple_ty,
...	@@ -4182,7 +4427,7 @@ fn genIntMulDivOpMir(self: *Self, tag: Mir.Inst.FixedTag, ty: Type, lhs: MCValue	...	@@ -4182,7 +4427,7 @@ fn genIntMulDivOpMir(self: *Self, tag: Mir.Inst.FixedTag, ty: Type, lhs: MCValue
4182	return self.fail("TODO implement genIntMulDivOpMir for ABI size larger than 8", .{});	4427	return self.fail("TODO implement genIntMulDivOpMir for ABI size larger than 8", .{});
4183	}	4428	}
4184		4429
4185	try self.genSetReg(.rax, ty, lhs);	4430	try self.genSetReg(.rax, ty, lhs, .{});
4186	switch (tag[1]) {	4431	switch (tag[1]) {
4187	else => unreachable,	4432	else => unreachable,
4188	.mul => {},	4433	.mul => {},
...	@@ -4311,6 +4556,7 @@ fn airShlShrBinOp(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -4311,6 +4556,7 @@ fn airShlShrBinOp(self: *Self, inst: Air.Inst.Index) !void {
4311	tmp_reg,	4556	tmp_reg,
4312	tmp_ty,	4557	tmp_ty,
4313	.{ .load_frame = .{ .index = frame_addr.index, .off = off } },	4558	.{ .load_frame = .{ .index = frame_addr.index, .off = off } },
		4559	.{},
4314	);	4560	);
4315	try self.truncateRegister(lhs_ty, tmp_reg);	4561	try self.truncateRegister(lhs_ty, tmp_reg);
4316	try self.genSetMem(	4562	try self.genSetMem(
...	@@ -4318,6 +4564,7 @@ fn airShlShrBinOp(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -4318,6 +4564,7 @@ fn airShlShrBinOp(self: *Self, inst: Air.Inst.Index) !void {
4318	off,	4564	off,
4319	tmp_ty,	4565	tmp_ty,
4320	.{ .register = tmp_reg },	4566	.{ .register = tmp_reg },
		4567	.{},
4321	);	4568	);
4322	},	4569	},
4323	else => {},	4570	else => {},
...	@@ -4578,7 +4825,7 @@ fn airOptionalPayload(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -4578,7 +4825,7 @@ fn airOptionalPayload(self: *Self, inst: Air.Inst.Index) !void {
4578	try self.genCopy(pl_ty, pl_mcv, switch (opt_mcv) {	4825	try self.genCopy(pl_ty, pl_mcv, switch (opt_mcv) {
4579	else => opt_mcv,	4826	else => opt_mcv,
4580	.register_overflow => \|ro\| .{ .register = ro.reg },	4827	.register_overflow => \|ro\| .{ .register = ro.reg },
4581	});	4828	}, .{});
4582	break :result pl_mcv;	4829	break :result pl_mcv;
4583	};	4830	};
4584	return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });	4831	return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
...	@@ -4625,7 +4872,13 @@ fn airOptionalPayloadPtrSet(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -4625,7 +4872,13 @@ fn airOptionalPayloadPtrSet(self: *Self, inst: Air.Inst.Index) !void {
4625		4872
4626	const pl_ty = dst_ty.childType(mod);	4873	const pl_ty = dst_ty.childType(mod);
4627	const pl_abi_size: i32 = @intCast(pl_ty.abiSize(mod));	4874	const pl_abi_size: i32 = @intCast(pl_ty.abiSize(mod));
4628	try self.genSetMem(.{ .reg = dst_mcv.getReg().? }, pl_abi_size, Type.bool, .{ .immediate = 1 });	4875	try self.genSetMem(
		4876	.{ .reg = dst_mcv.getReg().? },
		4877	pl_abi_size,
		4878	Type.bool,
		4879	.{ .immediate = 1 },
		4880	.{},
		4881	);
4629	break :result if (self.liveness.isUnused(inst)) .unreach else dst_mcv;	4882	break :result if (self.liveness.isUnused(inst)) .unreach else dst_mcv;
4630	};	4883	};
4631	return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });	4884	return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
...	@@ -4660,6 +4913,7 @@ fn airUnwrapErrUnionErr(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -4660,6 +4913,7 @@ fn airUnwrapErrUnionErr(self: *Self, inst: Air.Inst.Index) !void {
4660	.{ ._r, .sh },	4913	.{ ._r, .sh },
4661	err_union_ty,	4914	err_union_ty,
4662	result,	4915	result,
		4916	Type.u8,
4663	.{ .immediate = @as(u6, @intCast(err_off * 8)) },	4917	.{ .immediate = @as(u6, @intCast(err_off * 8)) },
4664	) else try self.truncateRegister(Type.anyerror, result.register);	4918	) else try self.truncateRegister(Type.anyerror, result.register);
4665	break :result result;	4919	break :result result;
...	@@ -4817,6 +5071,7 @@ fn genUnwrapErrUnionPayloadMir(	...	@@ -4817,6 +5071,7 @@ fn genUnwrapErrUnionPayloadMir(
4817	.{ ._r, .sh },	5071	.{ ._r, .sh },
4818	err_union_ty,	5072	err_union_ty,
4819	result_mcv,	5073	result_mcv,
		5074	Type.u8,
4820	.{ .immediate = @as(u6, @intCast(payload_off * 8)) },	5075	.{ .immediate = @as(u6, @intCast(payload_off * 8)) },
4821	) else try self.truncateRegister(payload_ty, result_mcv.register);	5076	) else try self.truncateRegister(payload_ty, result_mcv.register);
4822	break :result if (payload_in_gp)	5077	break :result if (payload_in_gp)
...	@@ -4891,7 +5146,7 @@ fn airWrapOptional(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -4891,7 +5146,7 @@ fn airWrapOptional(self: *Self, inst: Air.Inst.Index) !void {
4891	defer if (pl_lock) \|lock\| self.register_manager.unlockReg(lock);	5146	defer if (pl_lock) \|lock\| self.register_manager.unlockReg(lock);
4892		5147
4893	const opt_mcv = try self.allocRegOrMem(inst, true);	5148	const opt_mcv = try self.allocRegOrMem(inst, true);
4894	try self.genCopy(pl_ty, opt_mcv, pl_mcv);	5149	try self.genCopy(pl_ty, opt_mcv, pl_mcv, .{});
4895		5150
4896	if (!same_repr) {	5151	if (!same_repr) {
4897	const pl_abi_size: i32 = @intCast(pl_ty.abiSize(mod));	5152	const pl_abi_size: i32 = @intCast(pl_ty.abiSize(mod));
...	@@ -4941,8 +5196,8 @@ fn airWrapErrUnionPayload(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -4941,8 +5196,8 @@ fn airWrapErrUnionPayload(self: *Self, inst: Air.Inst.Index) !void {
4941	const frame_index = try self.allocFrameIndex(FrameAlloc.initSpill(eu_ty, mod));	5196	const frame_index = try self.allocFrameIndex(FrameAlloc.initSpill(eu_ty, mod));
4942	const pl_off: i32 = @intCast(errUnionPayloadOffset(pl_ty, mod));	5197	const pl_off: i32 = @intCast(errUnionPayloadOffset(pl_ty, mod));
4943	const err_off: i32 = @intCast(errUnionErrorOffset(pl_ty, mod));	5198	const err_off: i32 = @intCast(errUnionErrorOffset(pl_ty, mod));
4944	try self.genSetMem(.{ .frame = frame_index }, pl_off, pl_ty, operand);	5199	try self.genSetMem(.{ .frame = frame_index }, pl_off, pl_ty, operand, .{});
4945	try self.genSetMem(.{ .frame = frame_index }, err_off, err_ty, .{ .immediate = 0 });	5200	try self.genSetMem(.{ .frame = frame_index }, err_off, err_ty, .{ .immediate = 0 }, .{});
4946	break :result .{ .load_frame = .{ .index = frame_index } };	5201	break :result .{ .load_frame = .{ .index = frame_index } };
4947	};	5202	};
4948	return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });	5203	return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
...	@@ -4963,9 +5218,9 @@ fn airWrapErrUnionErr(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -4963,9 +5218,9 @@ fn airWrapErrUnionErr(self: *Self, inst: Air.Inst.Index) !void {
4963	const frame_index = try self.allocFrameIndex(FrameAlloc.initSpill(eu_ty, mod));	5218	const frame_index = try self.allocFrameIndex(FrameAlloc.initSpill(eu_ty, mod));
4964	const pl_off: i32 = @intCast(errUnionPayloadOffset(pl_ty, mod));	5219	const pl_off: i32 = @intCast(errUnionPayloadOffset(pl_ty, mod));
4965	const err_off: i32 = @intCast(errUnionErrorOffset(pl_ty, mod));	5220	const err_off: i32 = @intCast(errUnionErrorOffset(pl_ty, mod));
4966	try self.genSetMem(.{ .frame = frame_index }, pl_off, pl_ty, .undef);	5221	try self.genSetMem(.{ .frame = frame_index }, pl_off, pl_ty, .undef, .{});
4967	const operand = try self.resolveInst(ty_op.operand);	5222	const operand = try self.resolveInst(ty_op.operand);
4968	try self.genSetMem(.{ .frame = frame_index }, err_off, err_ty, operand);	5223	try self.genSetMem(.{ .frame = frame_index }, err_off, err_ty, operand, .{});
4969	break :result .{ .load_frame = .{ .index = frame_index } };	5224	break :result .{ .load_frame = .{ .index = frame_index } };
4970	};	5225	};
4971	return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });	5226	return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
...	@@ -4979,7 +5234,7 @@ fn airSlicePtr(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -4979,7 +5234,7 @@ fn airSlicePtr(self: *Self, inst: Air.Inst.Index) !void {
4979		5234
4980	const dst_mcv = try self.allocRegOrMem(inst, true);	5235	const dst_mcv = try self.allocRegOrMem(inst, true);
4981	const dst_ty = self.typeOfIndex(inst);	5236	const dst_ty = self.typeOfIndex(inst);
4982	try self.genCopy(dst_ty, dst_mcv, src_mcv);	5237	try self.genCopy(dst_ty, dst_mcv, src_mcv, .{});
4983	break :result dst_mcv;	5238	break :result dst_mcv;
4984	};	5239	};
4985	return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });	5240	return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
...	@@ -4999,7 +5254,7 @@ fn airSliceLen(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -4999,7 +5254,7 @@ fn airSliceLen(self: *Self, inst: Air.Inst.Index) !void {
4999	if (self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) break :result len_mcv;	5254	if (self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) break :result len_mcv;
5000		5255
5001	const dst_mcv = try self.allocRegOrMem(inst, true);	5256	const dst_mcv = try self.allocRegOrMem(inst, true);
5002	try self.genCopy(Type.usize, dst_mcv, len_mcv);	5257	try self.genCopy(Type.usize, dst_mcv, len_mcv, .{});
5003	break :result dst_mcv;	5258	break :result dst_mcv;
5004	},	5259	},
5005	else => return self.fail("TODO implement slice_len for {}", .{src_mcv}),	5260	else => return self.fail("TODO implement slice_len for {}", .{src_mcv}),
...	@@ -5063,7 +5318,7 @@ fn elemOffset(self: *Self, index_ty: Type, index: MCValue, elem_size: u64) !Regi	...	@@ -5063,7 +5318,7 @@ fn elemOffset(self: *Self, index_ty: Type, index: MCValue, elem_size: u64) !Regi
5063	// Optimisation: if index MCValue is an immediate, we can multiply in `comptime`	5318	// Optimisation: if index MCValue is an immediate, we can multiply in `comptime`
5064	// and set the register directly to the scaled offset as an immediate.	5319	// and set the register directly to the scaled offset as an immediate.
5065	const reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);	5320	const reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
5066	try self.genSetReg(reg, index_ty, .{ .immediate = imm * elem_size });	5321	try self.genSetReg(reg, index_ty, .{ .immediate = imm * elem_size }, .{});
5067	break :blk reg;	5322	break :blk reg;
5068	},	5323	},
5069	else => {	5324	else => {
...	@@ -5103,7 +5358,7 @@ fn genSliceElemPtr(self: *Self, lhs: Air.Inst.Ref, rhs: Air.Inst.Ref) !MCValue {	...	@@ -5103,7 +5358,7 @@ fn genSliceElemPtr(self: *Self, lhs: Air.Inst.Ref, rhs: Air.Inst.Ref) !MCValue {
5103	defer self.register_manager.unlockReg(offset_reg_lock);	5358	defer self.register_manager.unlockReg(offset_reg_lock);
5104		5359
5105	const addr_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);	5360	const addr_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
5106	try self.genSetReg(addr_reg, Type.usize, slice_mcv);	5361	try self.genSetReg(addr_reg, Type.usize, slice_mcv, .{});
5107	// TODO we could allocate register here, but need to expect addr register and potentially	5362	// TODO we could allocate register here, but need to expect addr register and potentially
5108	// offset register.	5363	// offset register.
5109	try self.genBinOpMir(.{ ._, .add }, slice_ptr_field_type, .{ .register = addr_reg }, .{	5364	try self.genBinOpMir(.{ ._, .add }, slice_ptr_field_type, .{ .register = addr_reg }, .{
...	@@ -5167,11 +5422,26 @@ fn airArrayElemVal(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -5167,11 +5422,26 @@ fn airArrayElemVal(self: *Self, inst: Air.Inst.Index) !void {
5167	else => try self.copyToTmpRegister(index_ty, index_mcv),	5422	else => try self.copyToTmpRegister(index_ty, index_mcv),
5168	};	5423	};
5169	switch (array_mcv) {	5424	switch (array_mcv) {
5170	.register => \|array_reg\| try self.asmRegisterRegister(	5425	.register => \|array_reg\| switch (array_reg.class()) {
5171	.{ ._, .bt },	5426	.general_purpose => try self.asmRegisterRegister(
5172	array_reg.to64(),	5427	.{ ._, .bt },
5173	index_reg.to64(),	5428	array_reg.to64(),
5174	),	5429	index_reg.to64(),
		5430	),
		5431	.sse => {
		5432	const frame_index = try self.allocFrameIndex(FrameAlloc.initType(array_ty, mod));
		5433	try self.genSetMem(.{ .frame = frame_index }, 0, array_ty, array_mcv, .{});
		5434	try self.asmMemoryRegister(
		5435	.{ ._, .bt },
		5436	.{
		5437	.base = .{ .frame = frame_index },
		5438	.mod = .{ .rm = .{ .size = .qword } },
		5439	},
		5440	index_reg.to64(),
		5441	);
		5442	},
		5443	else => unreachable,
		5444	},
5175	.load_frame => try self.asmMemoryRegister(	5445	.load_frame => try self.asmMemoryRegister(
5176	.{ ._, .bt },	5446	.{ ._, .bt },
5177	try array_mcv.mem(self, .qword),	5447	try array_mcv.mem(self, .qword),
...	@@ -5205,7 +5475,7 @@ fn airArrayElemVal(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -5205,7 +5475,7 @@ fn airArrayElemVal(self: *Self, inst: Air.Inst.Index) !void {
5205	switch (array_mcv) {	5475	switch (array_mcv) {
5206	.register => {	5476	.register => {
5207	const frame_index = try self.allocFrameIndex(FrameAlloc.initType(array_ty, mod));	5477	const frame_index = try self.allocFrameIndex(FrameAlloc.initType(array_ty, mod));
5208	try self.genSetMem(.{ .frame = frame_index }, 0, array_ty, array_mcv);	5478	try self.genSetMem(.{ .frame = frame_index }, 0, array_ty, array_mcv, .{});
5209	try self.asmRegisterMemory(	5479	try self.asmRegisterMemory(
5210	.{ ._, .lea },	5480	.{ ._, .lea },
5211	addr_reg,	5481	addr_reg,
...	@@ -5225,7 +5495,7 @@ fn airArrayElemVal(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -5225,7 +5495,7 @@ fn airArrayElemVal(self: *Self, inst: Air.Inst.Index) !void {
5225	.load_direct,	5495	.load_direct,
5226	.load_got,	5496	.load_got,
5227	.load_tlv,	5497	.load_tlv,
5228	=> try self.genSetReg(addr_reg, Type.usize, array_mcv.address()),	5498	=> try self.genSetReg(addr_reg, Type.usize, array_mcv.address(), .{}),
5229	.lea_symbol, .lea_direct, .lea_tlv => unreachable,	5499	.lea_symbol, .lea_direct, .lea_tlv => unreachable,
5230	else => return self.fail("TODO airArrayElemVal_val for {s} of {}", .{	5500	else => return self.fail("TODO airArrayElemVal_val for {s} of {}", .{
5231	@tagName(array_mcv), array_ty.fmt(mod),	5501	@tagName(array_mcv), array_ty.fmt(mod),
...	@@ -5245,7 +5515,7 @@ fn airArrayElemVal(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -5245,7 +5515,7 @@ fn airArrayElemVal(self: *Self, inst: Air.Inst.Index) !void {
5245	.{ .register = addr_reg },	5515	.{ .register = addr_reg },
5246	.{ .register = offset_reg },	5516	.{ .register = offset_reg },
5247	);	5517	);
5248	try self.genCopy(elem_ty, dst_mcv, .{ .indirect = .{ .reg = addr_reg } });	5518	try self.genCopy(elem_ty, dst_mcv, .{ .indirect = .{ .reg = addr_reg } }, .{});
5249	break :result dst_mcv;	5519	break :result dst_mcv;
5250	};	5520	};
5251	return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });	5521	return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
...	@@ -5385,7 +5655,7 @@ fn airSetUnionTag(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -5385,7 +5655,7 @@ fn airSetUnionTag(self: *Self, inst: Air.Inst.Index) !void {
5385	} else ptr;	5655	} else ptr;
5386		5656
5387	const ptr_tag_ty = try mod.adjustPtrTypeChild(ptr_union_ty, tag_ty);	5657	const ptr_tag_ty = try mod.adjustPtrTypeChild(ptr_union_ty, tag_ty);
5388	try self.store(ptr_tag_ty, adjusted_ptr, tag);	5658	try self.store(ptr_tag_ty, adjusted_ptr, tag, .{});
5389		5659
5390	return self.finishAir(inst, .none, .{ bin_op.lhs, bin_op.rhs, .none });	5660	return self.finishAir(inst, .none, .{ bin_op.lhs, bin_op.rhs, .none });
5391	}	5661	}
...	@@ -5424,7 +5694,10 @@ fn airGetUnionTag(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -5424,7 +5694,10 @@ fn airGetUnionTag(self: *Self, inst: Air.Inst.Index) !void {
5424	});	5694	});
5425	}	5695	}
5426		5696
5427	return self.fail("TODO implement get_union_tag for ABI larger than 8 bytes and operand {}", .{operand});	5697	return self.fail(
		5698	"TODO implement get_union_tag for ABI larger than 8 bytes and operand {}",
		5699	.{operand},
		5700	);
5428	},	5701	},
5429	.register => {	5702	.register => {
5430	const shift: u6 = if (layout.tag_align.compare(.lt, layout.payload_align))	5703	const shift: u6 = if (layout.tag_align.compare(.lt, layout.payload_align))
...	@@ -5432,7 +5705,13 @@ fn airGetUnionTag(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -5432,7 +5705,13 @@ fn airGetUnionTag(self: *Self, inst: Air.Inst.Index) !void {
5432	else	5705	else
5433	0;	5706	0;
5434	const result = try self.copyToRegisterWithInstTracking(inst, union_ty, operand);	5707	const result = try self.copyToRegisterWithInstTracking(inst, union_ty, operand);
5435	try self.genShiftBinOpMir(.{ ._r, .sh }, Type.usize, result, .{ .immediate = shift });	5708	try self.genShiftBinOpMir(
		5709	.{ ._r, .sh },
		5710	Type.usize,
		5711	result,
		5712	Type.u8,
		5713	.{ .immediate = shift },
		5714	);
5436	break :blk MCValue{	5715	break :blk MCValue{
5437	.register = registerAlias(result.register, @intCast(layout.tag_size)),	5716	.register = registerAlias(result.register, @intCast(layout.tag_size)),
5438	};	5717	};
...	@@ -5448,30 +5727,13 @@ fn airClz(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -5448,30 +5727,13 @@ fn airClz(self: *Self, inst: Air.Inst.Index) !void {
5448	const mod = self.bin_file.comp.module.?;	5727	const mod = self.bin_file.comp.module.?;
5449	const ty_op = self.air.instructions.items(.data)[@intFromEnum(inst)].ty_op;	5728	const ty_op = self.air.instructions.items(.data)[@intFromEnum(inst)].ty_op;
5450	const result = result: {	5729	const result = result: {
		5730	try self.spillEflagsIfOccupied();
		5731
5451	const dst_ty = self.typeOfIndex(inst);	5732	const dst_ty = self.typeOfIndex(inst);
5452	const src_ty = self.typeOf(ty_op.operand);	5733	const src_ty = self.typeOf(ty_op.operand);
5453	if (src_ty.zigTypeTag(mod) == .Vector) return self.fail("TODO implement airClz for {}", .{	5734	if (src_ty.zigTypeTag(mod) == .Vector) return self.fail("TODO implement airClz for {}", .{
5454	src_ty.fmt(mod),	5735	src_ty.fmt(mod),
5455	});	5736	});
5456	const src_bits: u32 = @intCast(src_ty.bitSize(mod));
5457
5458	const has_lzcnt = self.hasFeature(.lzcnt);
5459	if (src_bits > 64 and !has_lzcnt) {
5460	var callee_buf: ["__clz?i2".len]u8 = undefined;
5461	const result = try self.genCall(.{ .lib = .{
5462	.return_type = .i32_type,
5463	.param_types = &.{src_ty.toIntern()},
5464	.callee = std.fmt.bufPrint(&callee_buf, "__clz{c}i2", .{
5465	intCompilerRtAbiName(src_bits),
5466	}) catch unreachable,
5467	} }, &.{src_ty}, &.{.{ .air_ref = ty_op.operand }});
5468	if (src_bits < 128) try self.asmRegisterImmediate(
5469	.{ ._, .sub },
5470	result.register,
5471	Immediate.u(128 - src_bits),
5472	);
5473	break :result result;
5474	}
5475		5737
5476	const src_mcv = try self.resolveInst(ty_op.operand);	5738	const src_mcv = try self.resolveInst(ty_op.operand);
5477	const mat_src_mcv = switch (src_mcv) {	5739	const mat_src_mcv = switch (src_mcv) {
...	@@ -5489,6 +5751,61 @@ fn airClz(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -5489,6 +5751,61 @@ fn airClz(self: *Self, inst: Air.Inst.Index) !void {
5489	const dst_lock = self.register_manager.lockRegAssumeUnused(dst_reg);	5751	const dst_lock = self.register_manager.lockRegAssumeUnused(dst_reg);
5490	defer self.register_manager.unlockReg(dst_lock);	5752	defer self.register_manager.unlockReg(dst_lock);
5491		5753
		5754	const abi_size: u31 = @intCast(src_ty.abiSize(mod));
		5755	const src_bits: u31 = @intCast(src_ty.bitSize(mod));
		5756	const has_lzcnt = self.hasFeature(.lzcnt);
		5757	if (src_bits > @as(u32, if (has_lzcnt) 128 else 64)) {
		5758	const limbs_len = math.divCeil(u32, abi_size, 8) catch unreachable;
		5759	const extra_bits = abi_size * 8 - src_bits;
		5760
		5761	const index_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
		5762	const index_lock = self.register_manager.lockRegAssumeUnused(index_reg);
		5763	defer self.register_manager.unlockReg(index_lock);
		5764
		5765	try self.asmRegisterImmediate(.{ ._, .mov }, index_reg.to32(), Immediate.u(limbs_len));
		5766	switch (extra_bits) {
		5767	1 => try self.asmRegisterRegister(.{ ._, .xor }, dst_reg.to32(), dst_reg.to32()),
		5768	else => try self.asmRegisterImmediate(
		5769	.{ ._, .mov },
		5770	dst_reg.to32(),
		5771	Immediate.s(@as(i32, extra_bits) - 1),
		5772	),
		5773	}
		5774	const loop: Mir.Inst.Index = @intCast(self.mir_instructions.len);
		5775	try self.asmRegisterRegister(.{ ._, .@"test" }, index_reg.to32(), index_reg.to32());
		5776	const zero = try self.asmJccReloc(.z, undefined);
		5777	if (self.hasFeature(.slow_incdec)) {
		5778	try self.asmRegisterImmediate(.{ ._, .sub }, index_reg.to32(), Immediate.u(1));
		5779	} else {
		5780	try self.asmRegister(.{ ._, .dec }, index_reg.to32());
		5781	}
		5782	try self.asmMemoryImmediate(.{ ._, .cmp }, .{
		5783	.base = .{ .frame = src_mcv.load_frame.index },
		5784	.mod = .{ .rm = .{
		5785	.size = .qword,
		5786	.index = index_reg.to64(),
		5787	.scale = .@"8",
		5788	.disp = src_mcv.load_frame.off,
		5789	} },
		5790	}, Immediate.u(0));
		5791	_ = try self.asmJccReloc(.e, loop);
		5792	try self.asmRegisterMemory(.{ ._, .bsr }, dst_reg.to64(), .{
		5793	.base = .{ .frame = src_mcv.load_frame.index },
		5794	.mod = .{ .rm = .{
		5795	.size = .qword,
		5796	.index = index_reg.to64(),
		5797	.scale = .@"8",
		5798	.disp = src_mcv.load_frame.off,
		5799	} },
		5800	});
		5801	self.performReloc(zero);
		5802	try self.asmRegisterImmediate(.{ ._l, .sh }, index_reg.to32(), Immediate.u(6));
		5803	try self.asmRegisterRegister(.{ ._, .add }, index_reg.to32(), dst_reg.to32());
		5804	try self.asmRegisterImmediate(.{ ._, .mov }, dst_reg.to32(), Immediate.u(src_bits - 1));
		5805	try self.asmRegisterRegister(.{ ._, .sub }, dst_reg.to32(), index_reg.to32());
		5806	break :result dst_mcv;
		5807	}
		5808
5492	if (has_lzcnt) {	5809	if (has_lzcnt) {
5493	if (src_bits <= 8) {	5810	if (src_bits <= 8) {
5494	const wide_reg = try self.copyToTmpRegister(src_ty, mat_src_mcv);	5811	const wide_reg = try self.copyToTmpRegister(src_ty, mat_src_mcv);
...	@@ -5506,7 +5823,8 @@ fn airClz(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -5506,7 +5823,8 @@ fn airClz(self: *Self, inst: Air.Inst.Index) !void {
5506	if (extra_bits > 0) {	5823	if (extra_bits > 0) {
5507	try self.genBinOpMir(.{ ._, .sub }, dst_ty, dst_mcv, .{ .immediate = extra_bits });	5824	try self.genBinOpMir(.{ ._, .sub }, dst_ty, dst_mcv, .{ .immediate = extra_bits });
5508	}	5825	}
5509	} else if (src_bits <= 128) {	5826	} else {
		5827	assert(src_bits <= 128);
5510	const tmp_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);	5828	const tmp_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
5511	const tmp_mcv = MCValue{ .register = tmp_reg };	5829	const tmp_mcv = MCValue{ .register = tmp_reg };
5512	const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);	5830	const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
...	@@ -5539,12 +5857,12 @@ fn airClz(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -5539,12 +5857,12 @@ fn airClz(self: *Self, inst: Air.Inst.Index) !void {
5539	dst_mcv,	5857	dst_mcv,
5540	.{ .immediate = 128 - src_bits },	5858	.{ .immediate = 128 - src_bits },
5541	);	5859	);
5542	} else return self.fail("TODO airClz of {}", .{src_ty.fmt(mod)});	5860	}
5543	break :result dst_mcv;	5861	break :result dst_mcv;
5544	}	5862	}
5545		5863
5546	if (src_bits > 64)	5864	assert(src_bits <= 64);
5547	return self.fail("TODO airClz of {}", .{src_ty.fmt(mod)});	5865	const cmov_abi_size = @max(@as(u32, @intCast(dst_ty.abiSize(mod))), 2);
5548	if (math.isPowerOfTwo(src_bits)) {	5866	if (math.isPowerOfTwo(src_bits)) {
5549	const imm_reg = try self.copyToTmpRegister(dst_ty, .{	5867	const imm_reg = try self.copyToTmpRegister(dst_ty, .{
5550	.immediate = src_bits ^ (src_bits - 1),	5868	.immediate = src_bits ^ (src_bits - 1),
...	@@ -5561,7 +5879,6 @@ fn airClz(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -5561,7 +5879,6 @@ fn airClz(self: *Self, inst: Air.Inst.Index) !void {
5561	try self.genBinOpMir(.{ ._, .bsr }, Type.u16, dst_mcv, .{ .register = wide_reg });	5879	try self.genBinOpMir(.{ ._, .bsr }, Type.u16, dst_mcv, .{ .register = wide_reg });
5562	} else try self.genBinOpMir(.{ ._, .bsr }, src_ty, dst_mcv, mat_src_mcv);	5880	} else try self.genBinOpMir(.{ ._, .bsr }, src_ty, dst_mcv, mat_src_mcv);
5563		5881
5564	const cmov_abi_size = @max(@as(u32, @intCast(dst_ty.abiSize(mod))), 2);
5565	try self.asmCmovccRegisterRegister(	5882	try self.asmCmovccRegisterRegister(
5566	.z,	5883	.z,
5567	registerAlias(dst_reg, cmov_abi_size),	5884	registerAlias(dst_reg, cmov_abi_size),
...	@@ -5588,14 +5905,13 @@ fn airClz(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -5588,14 +5905,13 @@ fn airClz(self: *Self, inst: Air.Inst.Index) !void {
5588	.{ .register = wide_reg },	5905	.{ .register = wide_reg },
5589	);	5906	);
5590		5907
5591	const cmov_abi_size = @max(@as(u32, @intCast(dst_ty.abiSize(mod))), 2);
5592	try self.asmCmovccRegisterRegister(	5908	try self.asmCmovccRegisterRegister(
5593	.nz,	5909	.nz,
5594	registerAlias(imm_reg, cmov_abi_size),	5910	registerAlias(imm_reg, cmov_abi_size),
5595	registerAlias(dst_reg, cmov_abi_size),	5911	registerAlias(dst_reg, cmov_abi_size),
5596	);	5912	);
5597		5913
5598	try self.genSetReg(dst_reg, dst_ty, .{ .immediate = src_bits - 1 });	5914	try self.genSetReg(dst_reg, dst_ty, .{ .immediate = src_bits - 1 }, .{});
5599	try self.genBinOpMir(.{ ._, .sub }, dst_ty, dst_mcv, .{ .register = imm_reg });	5915	try self.genBinOpMir(.{ ._, .sub }, dst_ty, dst_mcv, .{ .register = imm_reg });
5600	}	5916	}
5601	break :result dst_mcv;	5917	break :result dst_mcv;
...	@@ -5607,24 +5923,13 @@ fn airCtz(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -5607,24 +5923,13 @@ fn airCtz(self: *Self, inst: Air.Inst.Index) !void {
5607	const mod = self.bin_file.comp.module.?;	5923	const mod = self.bin_file.comp.module.?;
5608	const ty_op = self.air.instructions.items(.data)[@intFromEnum(inst)].ty_op;	5924	const ty_op = self.air.instructions.items(.data)[@intFromEnum(inst)].ty_op;
5609	const result = result: {	5925	const result = result: {
		5926	try self.spillEflagsIfOccupied();
		5927
5610	const dst_ty = self.typeOfIndex(inst);	5928	const dst_ty = self.typeOfIndex(inst);
5611	const src_ty = self.typeOf(ty_op.operand);	5929	const src_ty = self.typeOf(ty_op.operand);
5612	if (src_ty.zigTypeTag(mod) == .Vector) return self.fail("TODO implement airClz for {}", .{	5930	if (src_ty.zigTypeTag(mod) == .Vector) return self.fail("TODO implement airCtz for {}", .{
5613	src_ty.fmt(mod),	5931	src_ty.fmt(mod),
5614	});	5932	});
5615	const src_bits: u32 = @intCast(src_ty.bitSize(mod));
5616
5617	const has_bmi = self.hasFeature(.bmi);
5618	if (src_bits > 64 and !has_bmi) {
5619	var callee_buf: ["__ctz?i2".len]u8 = undefined;
5620	break :result try self.genCall(.{ .lib = .{
5621	.return_type = .i32_type,
5622	.param_types = &.{src_ty.toIntern()},
5623	.callee = std.fmt.bufPrint(&callee_buf, "__ctz{c}i2", .{
5624	intCompilerRtAbiName(src_bits),
5625	}) catch unreachable,
5626	} }, &.{src_ty}, &.{.{ .air_ref = ty_op.operand }});
5627	}
5628		5933
5629	const src_mcv = try self.resolveInst(ty_op.operand);	5934	const src_mcv = try self.resolveInst(ty_op.operand);
5630	const mat_src_mcv = switch (src_mcv) {	5935	const mat_src_mcv = switch (src_mcv) {
...	@@ -5642,15 +5947,69 @@ fn airCtz(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -5642,15 +5947,69 @@ fn airCtz(self: *Self, inst: Air.Inst.Index) !void {
5642	const dst_lock = self.register_manager.lockReg(dst_reg);	5947	const dst_lock = self.register_manager.lockReg(dst_reg);
5643	defer if (dst_lock) \|lock\| self.register_manager.unlockReg(lock);	5948	defer if (dst_lock) \|lock\| self.register_manager.unlockReg(lock);
5644		5949
		5950	const abi_size: u31 = @intCast(src_ty.abiSize(mod));
		5951	const src_bits: u31 = @intCast(src_ty.bitSize(mod));
		5952	const has_bmi = self.hasFeature(.bmi);
		5953	if (src_bits > @as(u32, if (has_bmi) 128 else 64)) {
		5954	const limbs_len = math.divCeil(u32, abi_size, 8) catch unreachable;
		5955	const extra_bits = abi_size * 8 - src_bits;
		5956
		5957	const index_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
		5958	const index_lock = self.register_manager.lockRegAssumeUnused(index_reg);
		5959	defer self.register_manager.unlockReg(index_lock);
		5960
		5961	try self.asmRegisterImmediate(.{ ._, .mov }, index_reg.to32(), Immediate.s(-1));
		5962	switch (extra_bits) {
		5963	0 => try self.asmRegisterRegister(.{ ._, .xor }, dst_reg.to32(), dst_reg.to32()),
		5964	1 => try self.asmRegisterRegister(.{ ._, .mov }, dst_reg.to32(), dst_reg.to32()),
		5965	else => try self.asmRegisterImmediate(
		5966	.{ ._, .mov },
		5967	dst_reg.to32(),
		5968	Immediate.s(-@as(i32, extra_bits)),
		5969	),
		5970	}
		5971	const loop: Mir.Inst.Index = @intCast(self.mir_instructions.len);
		5972	if (self.hasFeature(.slow_incdec)) {
		5973	try self.asmRegisterImmediate(.{ ._, .add }, index_reg.to32(), Immediate.u(1));
		5974	} else {
		5975	try self.asmRegister(.{ ._, .inc }, index_reg.to32());
		5976	}
		5977	try self.asmRegisterImmediate(.{ ._, .cmp }, index_reg.to32(), Immediate.u(limbs_len));
		5978	const zero = try self.asmJccReloc(.nb, undefined);
		5979	try self.asmMemoryImmediate(.{ ._, .cmp }, .{
		5980	.base = .{ .frame = src_mcv.load_frame.index },
		5981	.mod = .{ .rm = .{
		5982	.size = .qword,
		5983	.index = index_reg.to64(),
		5984	.scale = .@"8",
		5985	.disp = src_mcv.load_frame.off,
		5986	} },
		5987	}, Immediate.u(0));
		5988	_ = try self.asmJccReloc(.e, loop);
		5989	try self.asmRegisterMemory(.{ ._, .bsf }, dst_reg.to64(), .{
		5990	.base = .{ .frame = src_mcv.load_frame.index },
		5991	.mod = .{ .rm = .{
		5992	.size = .qword,
		5993	.index = index_reg.to64(),
		5994	.scale = .@"8",
		5995	.disp = src_mcv.load_frame.off,
		5996	} },
		5997	});
		5998	self.performReloc(zero);
		5999	try self.asmRegisterImmediate(.{ ._l, .sh }, index_reg.to32(), Immediate.u(6));
		6000	try self.asmRegisterRegister(.{ ._, .add }, dst_reg.to32(), index_reg.to32());
		6001	break :result dst_mcv;
		6002	}
		6003
5645	const wide_ty = if (src_bits <= 8) Type.u16 else src_ty;	6004	const wide_ty = if (src_bits <= 8) Type.u16 else src_ty;
5646	if (self.hasFeature(.bmi)) {	6005	if (has_bmi) {
5647	if (src_bits <= 64) {	6006	if (src_bits <= 64) {
5648	const extra_bits = self.regExtraBits(src_ty) + @as(u64, if (src_bits <= 8) 8 else 0);	6007	const extra_bits = self.regExtraBits(src_ty) + @as(u64, if (src_bits <= 8) 8 else 0);
5649	const masked_mcv = if (extra_bits > 0) masked: {	6008	const masked_mcv = if (extra_bits > 0) masked: {
5650	const tmp_mcv = tmp: {	6009	const tmp_mcv = tmp: {
5651	if (src_mcv.isImmediate() or self.liveness.operandDies(inst, 0))	6010	if (src_mcv.isImmediate() or self.liveness.operandDies(inst, 0))
5652	break :tmp src_mcv;	6011	break :tmp src_mcv;
5653	try self.genSetReg(dst_reg, wide_ty, src_mcv);	6012	try self.genSetReg(dst_reg, wide_ty, src_mcv, .{});
5654	break :tmp dst_mcv;	6013	break :tmp dst_mcv;
5655	};	6014	};
5656	try self.genBinOpMir(	6015	try self.genBinOpMir(
...	@@ -5663,7 +6022,8 @@ fn airCtz(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -5663,7 +6022,8 @@ fn airCtz(self: *Self, inst: Air.Inst.Index) !void {
5663	break :masked tmp_mcv;	6022	break :masked tmp_mcv;
5664	} else mat_src_mcv;	6023	} else mat_src_mcv;
5665	try self.genBinOpMir(.{ ._, .tzcnt }, wide_ty, dst_mcv, masked_mcv);	6024	try self.genBinOpMir(.{ ._, .tzcnt }, wide_ty, dst_mcv, masked_mcv);
5666	} else if (src_bits <= 128) {	6025	} else {
		6026	assert(src_bits <= 128);
5667	const tmp_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);	6027	const tmp_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
5668	const tmp_mcv = MCValue{ .register = tmp_reg };	6028	const tmp_mcv = MCValue{ .register = tmp_reg };
5669	const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);	6029	const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
...	@@ -5678,7 +6038,7 @@ fn airCtz(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -5678,7 +6038,7 @@ fn airCtz(self: *Self, inst: Air.Inst.Index) !void {
5678	else	6038	else
5679	.{ .register = mat_src_mcv.register_pair[1] };	6039	.{ .register = mat_src_mcv.register_pair[1] };
5680	const masked_mcv = if (src_bits < 128) masked: {	6040	const masked_mcv = if (src_bits < 128) masked: {
5681	try self.genCopy(Type.u64, dst_mcv, hi_mat_src_mcv);	6041	try self.genCopy(Type.u64, dst_mcv, hi_mat_src_mcv, .{});
5682	try self.genBinOpMir(	6042	try self.genBinOpMir(
5683	.{ ._, .@"or" },	6043	.{ ._, .@"or" },
5684	Type.u64,	6044	Type.u64,
...	@@ -5691,12 +6051,11 @@ fn airCtz(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -5691,12 +6051,11 @@ fn airCtz(self: *Self, inst: Air.Inst.Index) !void {
5691	try self.genBinOpMir(.{ ._, .add }, dst_ty, dst_mcv, .{ .immediate = 64 });	6051	try self.genBinOpMir(.{ ._, .add }, dst_ty, dst_mcv, .{ .immediate = 64 });
5692	try self.genBinOpMir(.{ ._, .tzcnt }, Type.u64, tmp_mcv, lo_mat_src_mcv);	6052	try self.genBinOpMir(.{ ._, .tzcnt }, Type.u64, tmp_mcv, lo_mat_src_mcv);
5693	try self.asmCmovccRegisterRegister(.nc, dst_reg.to32(), tmp_reg.to32());	6053	try self.asmCmovccRegisterRegister(.nc, dst_reg.to32(), tmp_reg.to32());
5694	} else return self.fail("TODO airCtz of {}", .{src_ty.fmt(mod)});	6054	}
5695	break :result dst_mcv;	6055	break :result dst_mcv;
5696	}	6056	}
5697		6057
5698	if (src_bits > 64) return self.fail("TODO airCtz of {}", .{src_ty.fmt(mod)});	6058	assert(src_bits <= 64);
5699
5700	const width_reg = try self.copyToTmpRegister(dst_ty, .{ .immediate = src_bits });	6059	const width_reg = try self.copyToTmpRegister(dst_ty, .{ .immediate = src_bits });
5701	const width_lock = self.register_manager.lockRegAssumeUnused(width_reg);	6060	const width_lock = self.register_manager.lockRegAssumeUnused(width_reg);
5702	defer self.register_manager.unlockReg(width_lock);	6061	defer self.register_manager.unlockReg(width_lock);
...	@@ -5793,7 +6152,7 @@ fn genPopCount(	...	@@ -5793,7 +6152,7 @@ fn genPopCount(
5793	if (src_abi_size > 1) src_ty else Type.u32,	6152	if (src_abi_size > 1) src_ty else Type.u32,
5794	.{ .register = dst_reg },	6153	.{ .register = dst_reg },
5795	if (src_abi_size > 1) src_mcv else src: {	6154	if (src_abi_size > 1) src_mcv else src: {
5796	if (!dst_contains_src) try self.genSetReg(dst_reg, src_ty, src_mcv);	6155	if (!dst_contains_src) try self.genSetReg(dst_reg, src_ty, src_mcv, .{});
5797	try self.truncateRegister(try src_ty.toUnsigned(mod), dst_reg);	6156	try self.truncateRegister(try src_ty.toUnsigned(mod), dst_reg);
5798	break :src .{ .register = dst_reg };	6157	break :src .{ .register = dst_reg };
5799	},	6158	},
...	@@ -5816,7 +6175,7 @@ fn genPopCount(	...	@@ -5816,7 +6175,7 @@ fn genPopCount(
5816	else	6175	else
5817	undefined;	6176	undefined;
5818		6177
5819	if (!dst_contains_src) try self.genSetReg(dst, src_ty, src_mcv);	6178	if (!dst_contains_src) try self.genSetReg(dst, src_ty, src_mcv, .{});
5820	// dst = operand	6179	// dst = operand
5821	try self.asmRegisterRegister(.{ ._, .mov }, tmp, dst);	6180	try self.asmRegisterRegister(.{ ._, .mov }, tmp, dst);
5822	// tmp = operand	6181	// tmp = operand
...	@@ -5879,23 +6238,22 @@ fn genByteSwap(	...	@@ -5879,23 +6238,22 @@ fn genByteSwap(
5879	) !MCValue {	6238	) !MCValue {
5880	const mod = self.bin_file.comp.module.?;	6239	const mod = self.bin_file.comp.module.?;
5881	const ty_op = self.air.instructions.items(.data)[@intFromEnum(inst)].ty_op;	6240	const ty_op = self.air.instructions.items(.data)[@intFromEnum(inst)].ty_op;
5882	const have_movbe = self.hasFeature(.movbe);	6241	const has_movbe = self.hasFeature(.movbe);
5883		6242
5884	if (src_ty.zigTypeTag(mod) == .Vector) return self.fail(	6243	if (src_ty.zigTypeTag(mod) == .Vector) return self.fail(
5885	"TODO implement genByteSwap for {}",	6244	"TODO implement genByteSwap for {}",
5886	.{src_ty.fmt(mod)},	6245	.{src_ty.fmt(mod)},
5887	);	6246	);
5888	const abi_size: u32 = @intCast(src_ty.abiSize(mod));	6247
5889	const src_lock = switch (src_mcv) {	6248	const src_lock = switch (src_mcv) {
5890	.register => \|reg\| self.register_manager.lockRegAssumeUnused(reg),	6249	.register => \|reg\| self.register_manager.lockRegAssumeUnused(reg),
5891	else => null,	6250	else => null,
5892	};	6251	};
5893	defer if (src_lock) \|lock\| self.register_manager.unlockReg(lock);	6252	defer if (src_lock) \|lock\| self.register_manager.unlockReg(lock);
5894		6253
		6254	const abi_size: u32 = @intCast(src_ty.abiSize(mod));
5895	switch (abi_size) {	6255	switch (abi_size) {
5896	else => return self.fail("TODO implement genByteSwap for {}", .{	6256	0 => unreachable,
5897	src_ty.fmt(mod),
5898	}),
5899	1 => return if ((mem_ok or src_mcv.isRegister()) and	6257	1 => return if ((mem_ok or src_mcv.isRegister()) and
5900	self.reuseOperand(inst, ty_op.operand, 0, src_mcv))	6258	self.reuseOperand(inst, ty_op.operand, 0, src_mcv))
5901	src_mcv	6259	src_mcv
...	@@ -5928,11 +6286,11 @@ fn genByteSwap(	...	@@ -5928,11 +6286,11 @@ fn genByteSwap(
5928	for (dst_regs, 0..) \|dst_reg, limb_index\| {	6286	for (dst_regs, 0..) \|dst_reg, limb_index\| {
5929	if (src_mcv.isMemory()) {	6287	if (src_mcv.isMemory()) {
5930	try self.asmRegisterMemory(	6288	try self.asmRegisterMemory(
5931	.{ ._, if (have_movbe) .movbe else .mov },	6289	.{ ._, if (has_movbe) .movbe else .mov },
5932	dst_reg.to64(),	6290	dst_reg.to64(),
5933	try src_mcv.address().offset(@intCast(limb_index * 8)).deref().mem(self, .qword),	6291	try src_mcv.address().offset(@intCast(limb_index * 8)).deref().mem(self, .qword),
5934	);	6292	);
5935	if (!have_movbe) try self.asmRegister(.{ ._, .bswap }, dst_reg.to64());	6293	if (!has_movbe) try self.asmRegister(.{ ._, .bswap }, dst_reg.to64());
5936	} else {	6294	} else {
5937	try self.asmRegisterRegister(	6295	try self.asmRegisterRegister(
5938	.{ ._, .mov },	6296	.{ ._, .mov },
...	@@ -5944,9 +6302,85 @@ fn genByteSwap(	...	@@ -5944,9 +6302,85 @@ fn genByteSwap(
5944	}	6302	}
5945	return .{ .register_pair = .{ dst_regs[1], dst_regs[0] } };	6303	return .{ .register_pair = .{ dst_regs[1], dst_regs[0] } };
5946	},	6304	},
		6305	else => {
		6306	const limbs_len = math.divCeil(u32, abi_size, 8) catch unreachable;
		6307
		6308	const temp_regs =
		6309	try self.register_manager.allocRegs(4, .{null} ** 4, abi.RegisterClass.gp);
		6310	const temp_locks = self.register_manager.lockRegsAssumeUnused(4, temp_regs);
		6311	defer for (temp_locks) \|lock\| self.register_manager.unlockReg(lock);
		6312
		6313	const dst_mcv = try self.allocRegOrMem(inst, false);
		6314	try self.asmRegisterRegister(.{ ._, .xor }, temp_regs[0].to32(), temp_regs[0].to32());
		6315	try self.asmRegisterImmediate(
		6316	.{ ._, .mov },
		6317	temp_regs[1].to32(),
		6318	Immediate.u(limbs_len - 1),
		6319	);
		6320
		6321	const loop: Mir.Inst.Index = @intCast(self.mir_instructions.len);
		6322	try self.asmRegisterMemory(
		6323	.{ ._, if (has_movbe) .movbe else .mov },
		6324	temp_regs[2].to64(),
		6325	.{
		6326	.base = .{ .frame = dst_mcv.load_frame.index },
		6327	.mod = .{ .rm = .{
		6328	.size = .qword,
		6329	.index = temp_regs[0].to64(),
		6330	.scale = .@"8",
		6331	.disp = dst_mcv.load_frame.off,
		6332	} },
		6333	},
		6334	);
		6335	try self.asmRegisterMemory(
		6336	.{ ._, if (has_movbe) .movbe else .mov },
		6337	temp_regs[3].to64(),
		6338	.{
		6339	.base = .{ .frame = dst_mcv.load_frame.index },
		6340	.mod = .{ .rm = .{
		6341	.size = .qword,
		6342	.index = temp_regs[1].to64(),
		6343	.scale = .@"8",
		6344	.disp = dst_mcv.load_frame.off,
		6345	} },
		6346	},
		6347	);
		6348	if (!has_movbe) {
		6349	try self.asmRegister(.{ ._, .bswap }, temp_regs[2].to64());
		6350	try self.asmRegister(.{ ._, .bswap }, temp_regs[3].to64());
		6351	}
		6352	try self.asmMemoryRegister(.{ ._, .mov }, .{
		6353	.base = .{ .frame = dst_mcv.load_frame.index },
		6354	.mod = .{ .rm = .{
		6355	.size = .qword,
		6356	.index = temp_regs[0].to64(),
		6357	.scale = .@"8",
		6358	.disp = dst_mcv.load_frame.off,
		6359	} },
		6360	}, temp_regs[3].to64());
		6361	try self.asmMemoryRegister(.{ ._, .mov }, .{
		6362	.base = .{ .frame = dst_mcv.load_frame.index },
		6363	.mod = .{ .rm = .{
		6364	.size = .qword,
		6365	.index = temp_regs[1].to64(),
		6366	.scale = .@"8",
		6367	.disp = dst_mcv.load_frame.off,
		6368	} },
		6369	}, temp_regs[2].to64());
		6370	if (self.hasFeature(.slow_incdec)) {
		6371	try self.asmRegisterImmediate(.{ ._, .add }, temp_regs[0].to32(), Immediate.u(1));
		6372	try self.asmRegisterImmediate(.{ ._, .sub }, temp_regs[1].to32(), Immediate.u(1));
		6373	} else {
		6374	try self.asmRegister(.{ ._, .inc }, temp_regs[0].to32());
		6375	try self.asmRegister(.{ ._, .dec }, temp_regs[1].to32());
		6376	}
		6377	try self.asmRegisterRegister(.{ ._, .cmp }, temp_regs[0].to32(), temp_regs[1].to32());
		6378	_ = try self.asmJccReloc(.be, loop);
		6379	return dst_mcv;
		6380	},
5947	}	6381	}
5948		6382
5949	const dst_mcv: MCValue = if (mem_ok and have_movbe and src_mcv.isRegister())	6383	const dst_mcv: MCValue = if (mem_ok and has_movbe and src_mcv.isRegister())
5950	try self.allocRegOrMem(inst, true)	6384	try self.allocRegOrMem(inst, true)
5951	else	6385	else
5952	.{ .register = try self.register_manager.allocReg(inst, abi.RegisterClass.gp) };	6386	.{ .register = try self.register_manager.allocReg(inst, abi.RegisterClass.gp) };
...	@@ -5954,7 +6388,7 @@ fn genByteSwap(	...	@@ -5954,7 +6388,7 @@ fn genByteSwap(
5954	const dst_lock = self.register_manager.lockRegAssumeUnused(dst_mcv.register);	6388	const dst_lock = self.register_manager.lockRegAssumeUnused(dst_mcv.register);
5955	defer self.register_manager.unlockReg(dst_lock);	6389	defer self.register_manager.unlockReg(dst_lock);
5956		6390
5957	try self.genSetReg(dst_reg, src_ty, src_mcv);	6391	try self.genSetReg(dst_reg, src_ty, src_mcv, .{});
5958	switch (abi_size) {	6392	switch (abi_size) {
5959	else => unreachable,	6393	else => unreachable,
5960	2 => try self.genBinOpMir(.{ ._l, .ro }, src_ty, dst_mcv, .{ .immediate = 8 }),	6394	2 => try self.genBinOpMir(.{ ._l, .ro }, src_ty, dst_mcv, .{ .immediate = 8 }),
...	@@ -5969,20 +6403,20 @@ fn airByteSwap(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -5969,20 +6403,20 @@ fn airByteSwap(self: *Self, inst: Air.Inst.Index) !void {
5969	const ty_op = self.air.instructions.items(.data)[@intFromEnum(inst)].ty_op;	6403	const ty_op = self.air.instructions.items(.data)[@intFromEnum(inst)].ty_op;
5970		6404
5971	const src_ty = self.typeOf(ty_op.operand);	6405	const src_ty = self.typeOf(ty_op.operand);
5972	const abi_size: u32 = @intCast(src_ty.abiSize(mod));	6406	const src_bits: u32 = @intCast(src_ty.bitSize(mod));
5973	const bit_size: u32 = @intCast(src_ty.bitSize(mod));
5974	const src_mcv = try self.resolveInst(ty_op.operand);	6407	const src_mcv = try self.resolveInst(ty_op.operand);
5975		6408
5976	const dst_mcv = try self.genByteSwap(inst, src_ty, src_mcv, true);	6409	const dst_mcv = try self.genByteSwap(inst, src_ty, src_mcv, true);
5977		6410	try self.genShiftBinOpMir(
5978	const extra_bits = abi_size * 8 - bit_size;	6411	.{ ._r, switch (if (src_ty.isAbiInt(mod)) src_ty.intInfo(mod).signedness else .unsigned) {
5979	const signedness: std.builtin.Signedness =	6412	.signed => .sa,
5980	if (src_ty.isAbiInt(mod)) src_ty.intInfo(mod).signedness else .unsigned;	6413	.unsigned => .sh,
5981	if (extra_bits > 0) try self.genShiftBinOpMir(switch (signedness) {	6414	} },
5982	.signed => .{ ._r, .sa },	6415	src_ty,
5983	.unsigned => .{ ._r, .sh },	6416	dst_mcv,
5984	}, src_ty, dst_mcv, .{ .immediate = extra_bits });	6417	if (src_bits > 256) Type.u16 else Type.u8,
5985		6418	.{ .immediate = src_ty.abiSize(mod) * 8 - src_bits },
		6419	);
5986	return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });	6420	return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });
5987	}	6421	}
5988		6422
...	@@ -6004,8 +6438,8 @@ fn airBitReverse(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -6004,8 +6438,8 @@ fn airBitReverse(self: *Self, inst: Air.Inst.Index) !void {
6004	defer for (dst_locks) \|dst_lock\| if (dst_lock) \|lock\| self.register_manager.unlockReg(lock);	6438	defer for (dst_locks) \|dst_lock\| if (dst_lock) \|lock\| self.register_manager.unlockReg(lock);
6005		6439
6006	const tmp_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);	6440	const tmp_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
6007	const tmp_lock = self.register_manager.lockReg(tmp_reg);	6441	const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
6008	defer if (tmp_lock) \|lock\| self.register_manager.unlockReg(lock);	6442	defer self.register_manager.unlockReg(tmp_lock);
6009		6443
6010	const limb_abi_size: u32 = @min(abi_size, 8);	6444	const limb_abi_size: u32 = @min(abi_size, 8);
6011	const tmp = registerAlias(tmp_reg, limb_abi_size);	6445	const tmp = registerAlias(tmp_reg, limb_abi_size);
...	@@ -6103,7 +6537,7 @@ fn airBitReverse(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -6103,7 +6537,7 @@ fn airBitReverse(self: *Self, inst: Air.Inst.Index) !void {
6103	if (extra_bits > 0) try self.genShiftBinOpMir(switch (signedness) {	6537	if (extra_bits > 0) try self.genShiftBinOpMir(switch (signedness) {
6104	.signed => .{ ._r, .sa },	6538	.signed => .{ ._r, .sa },
6105	.unsigned => .{ ._r, .sh },	6539	.unsigned => .{ ._r, .sh },
6106	}, src_ty, dst_mcv, .{ .immediate = extra_bits });	6540	}, src_ty, dst_mcv, Type.u8, .{ .immediate = extra_bits });
6107		6541
6108	return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });	6542	return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });
6109	}	6543	}
...	@@ -6127,7 +6561,7 @@ fn floatSign(self: *Self, inst: Air.Inst.Index, operand: Air.Inst.Ref, ty: Type)	...	@@ -6127,7 +6561,7 @@ fn floatSign(self: *Self, inst: Air.Inst.Index, operand: Air.Inst.Ref, ty: Type)
6127	if (!std.meta.eql(src_mcv, dst_mcv) or !self.reuseOperand(inst, operand, 0, src_mcv))	6561	if (!std.meta.eql(src_mcv, dst_mcv) or !self.reuseOperand(inst, operand, 0, src_mcv))
6128	try self.register_manager.getReg(.st0, inst);	6562	try self.register_manager.getReg(.st0, inst);
6129		6563
6130	try self.genCopy(ty, dst_mcv, src_mcv);	6564	try self.genCopy(ty, dst_mcv, src_mcv, .{});
6131	switch (tag) {	6565	switch (tag) {
6132	.neg => try self.asmOpOnly(.{ .f_, .chs }),	6566	.neg => try self.asmOpOnly(.{ .f_, .chs }),
6133	.abs => try self.asmOpOnly(.{ .f_, .abs }),	6567	.abs => try self.asmOpOnly(.{ .f_, .abs }),
...	@@ -6344,7 +6778,7 @@ fn genRound(self: *Self, ty: Type, dst_reg: Register, src_mcv: MCValue, mode: Ro	...	@@ -6344,7 +6778,7 @@ fn genRound(self: *Self, ty: Type, dst_reg: Register, src_mcv: MCValue, mode: Ro
6344	const mod = self.bin_file.comp.module.?;	6778	const mod = self.bin_file.comp.module.?;
6345	const mir_tag = self.getRoundTag(ty) orelse {	6779	const mir_tag = self.getRoundTag(ty) orelse {
6346	const result = try self.genRoundLibcall(ty, src_mcv, mode);	6780	const result = try self.genRoundLibcall(ty, src_mcv, mode);
6347	return self.genSetReg(dst_reg, ty, result);	6781	return self.genSetReg(dst_reg, ty, result, .{});
6348	};	6782	};
6349	const abi_size: u32 = @intCast(ty.abiSize(mod));	6783	const abi_size: u32 = @intCast(ty.abiSize(mod));
6350	const dst_alias = registerAlias(dst_reg, abi_size);	6784	const dst_alias = registerAlias(dst_reg, abi_size);
...	@@ -6391,6 +6825,7 @@ fn airAbs(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -6391,6 +6825,7 @@ fn airAbs(self: *Self, inst: Air.Inst.Index) !void {
6391	const mir_tag = @as(?Mir.Inst.FixedTag, switch (ty.zigTypeTag(mod)) {	6825	const mir_tag = @as(?Mir.Inst.FixedTag, switch (ty.zigTypeTag(mod)) {
6392	else => null,	6826	else => null,
6393	.Int => switch (ty.abiSize(mod)) {	6827	.Int => switch (ty.abiSize(mod)) {
		6828	0 => unreachable,
6394	1...8 => {	6829	1...8 => {
6395	try self.spillEflagsIfOccupied();	6830	try self.spillEflagsIfOccupied();
6396	const src_mcv = try self.resolveInst(ty_op.operand);	6831	const src_mcv = try self.resolveInst(ty_op.operand);
...	@@ -6435,7 +6870,7 @@ fn airAbs(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -6435,7 +6870,7 @@ fn airAbs(self: *Self, inst: Air.Inst.Index) !void {
6435	const dst_locks = self.register_manager.lockRegsAssumeUnused(2, dst_regs);	6870	const dst_locks = self.register_manager.lockRegsAssumeUnused(2, dst_regs);
6436	defer for (dst_locks) \|lock\| self.register_manager.unlockReg(lock);	6871	defer for (dst_locks) \|lock\| self.register_manager.unlockReg(lock);
6437		6872
6438	try self.genCopy(ty, dst_mcv, src_mcv);	6873	try self.genCopy(ty, dst_mcv, src_mcv, .{});
6439	break :dst dst_mcv;	6874	break :dst dst_mcv;
6440	};	6875	};
6441	const dst_regs = dst_mcv.register_pair;	6876	const dst_regs = dst_mcv.register_pair;
...	@@ -6456,7 +6891,66 @@ fn airAbs(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -6456,7 +6891,66 @@ fn airAbs(self: *Self, inst: Air.Inst.Index) !void {
6456		6891
6457	break :result dst_mcv;	6892	break :result dst_mcv;
6458	},	6893	},
6459	else => return self.fail("TODO implement abs for {}", .{ty.fmt(mod)}),	6894	else => {
		6895	const abi_size: u31 = @intCast(ty.abiSize(mod));
		6896	const limb_len = std.math.divCeil(u31, abi_size, 8) catch unreachable;
		6897
		6898	const tmp_regs =
		6899	try self.register_manager.allocRegs(3, .{null} ** 3, abi.RegisterClass.gp);
		6900	const tmp_locks = self.register_manager.lockRegsAssumeUnused(3, tmp_regs);
		6901	defer for (tmp_locks) \|lock\| self.register_manager.unlockReg(lock);
		6902
		6903	try self.spillEflagsIfOccupied();
		6904	const src_mcv = try self.resolveInst(ty_op.operand);
		6905	const dst_mcv = if (self.reuseOperand(inst, ty_op.operand, 0, src_mcv))
		6906	src_mcv
		6907	else
		6908	try self.allocRegOrMem(inst, false);
		6909
		6910	try self.asmMemoryImmediate(
		6911	.{ ._, .cmp },
		6912	try dst_mcv.address().offset((limb_len - 1) * 8).deref().mem(self, .qword),
		6913	Immediate.u(0),
		6914	);
		6915	const positive = try self.asmJccReloc(.ns, undefined);
		6916
		6917	try self.asmRegisterRegister(.{ ._, .xor }, tmp_regs[0].to32(), tmp_regs[0].to32());
		6918	try self.asmRegisterRegister(.{ ._, .xor }, tmp_regs[1].to8(), tmp_regs[1].to8());
		6919
		6920	const neg_loop: Mir.Inst.Index = @intCast(self.mir_instructions.len);
		6921	try self.asmRegisterRegister(.{ ._, .xor }, tmp_regs[2].to32(), tmp_regs[2].to32());
		6922	try self.asmRegisterImmediate(.{ ._r, .sh }, tmp_regs[1].to8(), Immediate.u(1));
		6923	try self.asmRegisterMemory(.{ ._, .sbb }, tmp_regs[2].to64(), .{
		6924	.base = .{ .frame = dst_mcv.load_frame.index },
		6925	.mod = .{ .rm = .{
		6926	.size = .qword,
		6927	.index = tmp_regs[0].to64(),
		6928	.scale = .@"8",
		6929	.disp = dst_mcv.load_frame.off,
		6930	} },
		6931	});
		6932	try self.asmSetccRegister(.c, tmp_regs[1].to8());
		6933	try self.asmMemoryRegister(.{ ._, .mov }, .{
		6934	.base = .{ .frame = dst_mcv.load_frame.index },
		6935	.mod = .{ .rm = .{
		6936	.size = .qword,
		6937	.index = tmp_regs[0].to64(),
		6938	.scale = .@"8",
		6939	.disp = dst_mcv.load_frame.off,
		6940	} },
		6941	}, tmp_regs[2].to64());
		6942
		6943	if (self.hasFeature(.slow_incdec)) {
		6944	try self.asmRegisterImmediate(.{ ._, .add }, tmp_regs[0].to32(), Immediate.u(1));
		6945	} else {
		6946	try self.asmRegister(.{ ._, .inc }, tmp_regs[0].to32());
		6947	}
		6948	try self.asmRegisterImmediate(.{ ._, .cmp }, tmp_regs[0].to32(), Immediate.u(limb_len));
		6949	_ = try self.asmJccReloc(.b, neg_loop);
		6950
		6951	self.performReloc(positive);
		6952	break :result dst_mcv;
		6953	},
6460	},	6954	},
6461	.Float => return self.floatSign(inst, ty_op.operand, ty),	6955	.Float => return self.floatSign(inst, ty_op.operand, ty),
6462	.Vector => switch (ty.childType(mod).zigTypeTag(mod)) {	6956	.Vector => switch (ty.childType(mod).zigTypeTag(mod)) {
...	@@ -6792,9 +7286,9 @@ fn packedLoad(self: *Self, dst_mcv: MCValue, ptr_ty: Type, ptr_mcv: MCValue) Inn	...	@@ -6792,9 +7286,9 @@ fn packedLoad(self: *Self, dst_mcv: MCValue, ptr_ty: Type, ptr_mcv: MCValue) Inn
6792	defer self.register_manager.unlockReg(tmp_lock);	7286	defer self.register_manager.unlockReg(tmp_lock);
6793		7287
6794	const hi_mcv = dst_mcv.address().offset(@intCast(val_bit_size / 64 * 8)).deref();	7288	const hi_mcv = dst_mcv.address().offset(@intCast(val_bit_size / 64 * 8)).deref();
6795	try self.genSetReg(tmp_reg, Type.usize, hi_mcv);	7289	try self.genSetReg(tmp_reg, Type.usize, hi_mcv, .{});
6796	try self.truncateRegister(val_ty, tmp_reg);	7290	try self.truncateRegister(val_ty, tmp_reg);
6797	try self.genCopy(Type.usize, hi_mcv, .{ .register = tmp_reg });	7291	try self.genCopy(Type.usize, hi_mcv, .{ .register = tmp_reg }, .{});
6798	}	7292	}
6799	}	7293	}
6800	return;	7294	return;
...	@@ -6802,7 +7296,7 @@ fn packedLoad(self: *Self, dst_mcv: MCValue, ptr_ty: Type, ptr_mcv: MCValue) Inn	...	@@ -6802,7 +7296,7 @@ fn packedLoad(self: *Self, dst_mcv: MCValue, ptr_ty: Type, ptr_mcv: MCValue) Inn
6802		7296
6803	if (val_abi_size > 8) return self.fail("TODO implement packed load of {}", .{val_ty.fmt(mod)});	7297	if (val_abi_size > 8) return self.fail("TODO implement packed load of {}", .{val_ty.fmt(mod)});
6804		7298
6805	const limb_abi_size: u32 = @min(val_abi_size, 8);	7299	const limb_abi_size: u31 = @min(val_abi_size, 8);
6806	const limb_abi_bits = limb_abi_size * 8;	7300	const limb_abi_bits = limb_abi_size * 8;
6807	const val_byte_off: i32 = @intCast(ptr_bit_off / limb_abi_bits * limb_abi_size);	7301	const val_byte_off: i32 = @intCast(ptr_bit_off / limb_abi_bits * limb_abi_size);
6808	const val_bit_off = ptr_bit_off % limb_abi_bits;	7302	const val_bit_off = ptr_bit_off % limb_abi_bits;
...	@@ -6850,7 +7344,7 @@ fn packedLoad(self: *Self, dst_mcv: MCValue, ptr_ty: Type, ptr_mcv: MCValue) Inn	...	@@ -6850,7 +7344,7 @@ fn packedLoad(self: *Self, dst_mcv: MCValue, ptr_ty: Type, ptr_mcv: MCValue) Inn
6850	.base = .{ .reg = ptr_reg },	7344	.base = .{ .reg = ptr_reg },
6851	.mod = .{ .rm = .{	7345	.mod = .{ .rm = .{
6852	.size = Memory.Size.fromSize(val_abi_size),	7346	.size = Memory.Size.fromSize(val_abi_size),
6853	.disp = val_byte_off + 1,	7347	.disp = val_byte_off + limb_abi_size,
6854	} },	7348	} },
6855	});	7349	});
6856	try self.spillEflagsIfOccupied();	7350	try self.spillEflagsIfOccupied();
...	@@ -6863,7 +7357,7 @@ fn packedLoad(self: *Self, dst_mcv: MCValue, ptr_ty: Type, ptr_mcv: MCValue) Inn	...	@@ -6863,7 +7357,7 @@ fn packedLoad(self: *Self, dst_mcv: MCValue, ptr_ty: Type, ptr_mcv: MCValue) Inn
6863	}	7357	}
6864		7358
6865	if (val_extra_bits > 0) try self.truncateRegister(val_ty, dst_reg);	7359	if (val_extra_bits > 0) try self.truncateRegister(val_ty, dst_reg);
6866	try self.genCopy(val_ty, dst_mcv, .{ .register = dst_reg });	7360	try self.genCopy(val_ty, dst_mcv, .{ .register = dst_reg }, .{});
6867	}	7361	}
6868		7362
6869	fn load(self: *Self, dst_mcv: MCValue, ptr_ty: Type, ptr_mcv: MCValue) InnerError!void {	7363	fn load(self: *Self, dst_mcv: MCValue, ptr_ty: Type, ptr_mcv: MCValue) InnerError!void {
...	@@ -6878,6 +7372,7 @@ fn load(self: *Self, dst_mcv: MCValue, ptr_ty: Type, ptr_mcv: MCValue) InnerErro	...	@@ -6878,6 +7372,7 @@ fn load(self: *Self, dst_mcv: MCValue, ptr_ty: Type, ptr_mcv: MCValue) InnerErro
6878	.eflags,	7372	.eflags,
6879	.register_pair,	7373	.register_pair,
6880	.register_overflow,	7374	.register_overflow,
		7375	.elementwise_regs_then_frame,
6881	.reserved_frame,	7376	.reserved_frame,
6882	=> unreachable, // not a valid pointer	7377	=> unreachable, // not a valid pointer
6883	.immediate,	7378	.immediate,
...	@@ -6888,7 +7383,7 @@ fn load(self: *Self, dst_mcv: MCValue, ptr_ty: Type, ptr_mcv: MCValue) InnerErro	...	@@ -6888,7 +7383,7 @@ fn load(self: *Self, dst_mcv: MCValue, ptr_ty: Type, ptr_mcv: MCValue) InnerErro
6888	.lea_got,	7383	.lea_got,
6889	.lea_tlv,	7384	.lea_tlv,
6890	.lea_frame,	7385	.lea_frame,
6891	=> try self.genCopy(dst_ty, dst_mcv, ptr_mcv.deref()),	7386	=> try self.genCopy(dst_ty, dst_mcv, ptr_mcv.deref(), .{}),
6892	.memory,	7387	.memory,
6893	.indirect,	7388	.indirect,
6894	.load_symbol,	7389	.load_symbol,
...	@@ -6901,7 +7396,7 @@ fn load(self: *Self, dst_mcv: MCValue, ptr_ty: Type, ptr_mcv: MCValue) InnerErro	...	@@ -6901,7 +7396,7 @@ fn load(self: *Self, dst_mcv: MCValue, ptr_ty: Type, ptr_mcv: MCValue) InnerErro
6901	const addr_lock = self.register_manager.lockRegAssumeUnused(addr_reg);	7396	const addr_lock = self.register_manager.lockRegAssumeUnused(addr_reg);
6902	defer self.register_manager.unlockReg(addr_lock);	7397	defer self.register_manager.unlockReg(addr_lock);
6903		7398
6904	try self.genCopy(dst_ty, dst_mcv, .{ .indirect = .{ .reg = addr_reg } });	7399	try self.genCopy(dst_ty, dst_mcv, .{ .indirect = .{ .reg = addr_reg } }, .{});
6905	},	7400	},
6906	.air_ref => \|ptr_ref\| try self.load(dst_mcv, ptr_ty, try self.resolveInst(ptr_ref)),	7401	.air_ref => \|ptr_ref\| try self.load(dst_mcv, ptr_ty, try self.resolveInst(ptr_ref)),
6907	}	7402	}
...	@@ -6957,6 +7452,7 @@ fn airLoad(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -6957,6 +7452,7 @@ fn airLoad(self: *Self, inst: Air.Inst.Index) !void {
6957	if (elem_size <= 8) elem_ty else Type.usize,	7452	if (elem_size <= 8) elem_ty else Type.usize,
6958	high_mcv,	7453	high_mcv,
6959	.{ .register = high_reg },	7454	.{ .register = high_reg },
		7455	.{},
6960	);	7456	);
6961	}	7457	}
6962	break :result dst_mcv;	7458	break :result dst_mcv;
...	@@ -7019,18 +7515,20 @@ fn packedStore(self: *Self, ptr_ty: Type, ptr_mcv: MCValue, src_mcv: MCValue) In	...	@@ -7019,18 +7515,20 @@ fn packedStore(self: *Self, ptr_ty: Type, ptr_mcv: MCValue, src_mcv: MCValue) In
7019	const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);	7515	const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
7020	defer self.register_manager.unlockReg(tmp_lock);	7516	defer self.register_manager.unlockReg(tmp_lock);
7021		7517
7022	try self.genSetReg(tmp_reg, limb_ty, src_mcv);	7518	try self.genSetReg(tmp_reg, limb_ty, src_mcv, .{});
7023	switch (limb_i) {	7519	switch (limb_i) {
7024	0 => try self.genShiftBinOpMir(	7520	0 => try self.genShiftBinOpMir(
7025	.{ ._l, .sh },	7521	.{ ._l, .sh },
7026	limb_ty,	7522	limb_ty,
7027	tmp_mcv,	7523	tmp_mcv,
		7524	Type.u8,
7028	.{ .immediate = src_bit_off },	7525	.{ .immediate = src_bit_off },
7029	),	7526	),
7030	1 => try self.genShiftBinOpMir(	7527	1 => try self.genShiftBinOpMir(
7031	.{ ._r, .sh },	7528	.{ ._r, .sh },
7032	limb_ty,	7529	limb_ty,
7033	tmp_mcv,	7530	tmp_mcv,
		7531	Type.u8,
7034	.{ .immediate = limb_abi_bits - src_bit_off },	7532	.{ .immediate = limb_abi_bits - src_bit_off },
7035	),	7533	),
7036	else => unreachable,	7534	else => unreachable,
...	@@ -7050,7 +7548,7 @@ fn packedStore(self: *Self, ptr_ty: Type, ptr_mcv: MCValue, src_mcv: MCValue) In	...	@@ -7050,7 +7548,7 @@ fn packedStore(self: *Self, ptr_ty: Type, ptr_mcv: MCValue, src_mcv: MCValue) In
7050	try self.genSetReg(tmp_reg, limb_ty, switch (limb_i) {	7548	try self.genSetReg(tmp_reg, limb_ty, switch (limb_i) {
7051	0 => src_mcv,	7549	0 => src_mcv,
7052	else => src_mcv.address().offset(limb_i * limb_abi_size).deref(),	7550	else => src_mcv.address().offset(limb_i * limb_abi_size).deref(),
7053	});	7551	}, .{});
7054	try self.genBinOpMir(.{ ._, .@"and" }, limb_ty, tmp_mcv, .{ .immediate = part_mask });	7552	try self.genBinOpMir(.{ ._, .@"and" }, limb_ty, tmp_mcv, .{ .immediate = part_mask });
7055	try self.asmMemoryRegister(	7553	try self.asmMemoryRegister(
7056	.{ ._, .@"or" },	7554	.{ ._, .@"or" },
...	@@ -7061,7 +7559,13 @@ fn packedStore(self: *Self, ptr_ty: Type, ptr_mcv: MCValue, src_mcv: MCValue) In	...	@@ -7061,7 +7559,13 @@ fn packedStore(self: *Self, ptr_ty: Type, ptr_mcv: MCValue, src_mcv: MCValue) In
7061	}	7559	}
7062	}	7560	}
7063		7561
7064	fn store(self: *Self, ptr_ty: Type, ptr_mcv: MCValue, src_mcv: MCValue) InnerError!void {	7562	fn store(
		7563	self: *Self,
		7564	ptr_ty: Type,
		7565	ptr_mcv: MCValue,
		7566	src_mcv: MCValue,
		7567	opts: CopyOptions,
		7568	) InnerError!void {
7065	const mod = self.bin_file.comp.module.?;	7569	const mod = self.bin_file.comp.module.?;
7066	const src_ty = ptr_ty.childType(mod);	7570	const src_ty = ptr_ty.childType(mod);
7067	if (!src_ty.hasRuntimeBitsIgnoreComptime(mod)) return;	7571	if (!src_ty.hasRuntimeBitsIgnoreComptime(mod)) return;
...	@@ -7073,6 +7577,7 @@ fn store(self: *Self, ptr_ty: Type, ptr_mcv: MCValue, src_mcv: MCValue) InnerErr	...	@@ -7073,6 +7577,7 @@ fn store(self: *Self, ptr_ty: Type, ptr_mcv: MCValue, src_mcv: MCValue) InnerErr
7073	.eflags,	7577	.eflags,
7074	.register_pair,	7578	.register_pair,
7075	.register_overflow,	7579	.register_overflow,
		7580	.elementwise_regs_then_frame,
7076	.reserved_frame,	7581	.reserved_frame,
7077	=> unreachable, // not a valid pointer	7582	=> unreachable, // not a valid pointer
7078	.immediate,	7583	.immediate,
...	@@ -7083,7 +7588,7 @@ fn store(self: *Self, ptr_ty: Type, ptr_mcv: MCValue, src_mcv: MCValue) InnerErr	...	@@ -7083,7 +7588,7 @@ fn store(self: *Self, ptr_ty: Type, ptr_mcv: MCValue, src_mcv: MCValue) InnerErr
7083	.lea_got,	7588	.lea_got,
7084	.lea_tlv,	7589	.lea_tlv,
7085	.lea_frame,	7590	.lea_frame,
7086	=> try self.genCopy(src_ty, ptr_mcv.deref(), src_mcv),	7591	=> try self.genCopy(src_ty, ptr_mcv.deref(), src_mcv, opts),
7087	.memory,	7592	.memory,
7088	.indirect,	7593	.indirect,
7089	.load_symbol,	7594	.load_symbol,
...	@@ -7096,9 +7601,9 @@ fn store(self: *Self, ptr_ty: Type, ptr_mcv: MCValue, src_mcv: MCValue) InnerErr	...	@@ -7096,9 +7601,9 @@ fn store(self: *Self, ptr_ty: Type, ptr_mcv: MCValue, src_mcv: MCValue) InnerErr
7096	const addr_lock = self.register_manager.lockRegAssumeUnused(addr_reg);	7601	const addr_lock = self.register_manager.lockRegAssumeUnused(addr_reg);
7097	defer self.register_manager.unlockReg(addr_lock);	7602	defer self.register_manager.unlockReg(addr_lock);
7098		7603
7099	try self.genCopy(src_ty, .{ .indirect = .{ .reg = addr_reg } }, src_mcv);	7604	try self.genCopy(src_ty, .{ .indirect = .{ .reg = addr_reg } }, src_mcv, opts);
7100	},	7605	},
7101	.air_ref => \|ptr_ref\| try self.store(ptr_ty, try self.resolveInst(ptr_ref), src_mcv),	7606	.air_ref => \|ptr_ref\| try self.store(ptr_ty, try self.resolveInst(ptr_ref), src_mcv, opts),
7102	}	7607	}
7103	}	7608	}
7104		7609
...	@@ -7121,7 +7626,7 @@ fn airStore(self: *Self, inst: Air.Inst.Index, safety: bool) !void {	...	@@ -7121,7 +7626,7 @@ fn airStore(self: *Self, inst: Air.Inst.Index, safety: bool) !void {
7121	if (ptr_info.flags.vector_index != .none or ptr_info.packed_offset.host_size > 0) {	7626	if (ptr_info.flags.vector_index != .none or ptr_info.packed_offset.host_size > 0) {
7122	try self.packedStore(ptr_ty, ptr_mcv, src_mcv);	7627	try self.packedStore(ptr_ty, ptr_mcv, src_mcv);
7123	} else {	7628	} else {
7124	try self.store(ptr_ty, ptr_mcv, src_mcv);	7629	try self.store(ptr_ty, ptr_mcv, src_mcv, .{ .safety = safety });
7125	}	7630	}
7126	}	7631	}
7127	return self.finishAir(inst, .none, .{ bin_op.lhs, bin_op.rhs, .none });	7632	return self.finishAir(inst, .none, .{ bin_op.lhs, bin_op.rhs, .none });
...	@@ -7212,6 +7717,7 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -7212,6 +7717,7 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
7212	.{ ._r, .sh },	7717	.{ ._r, .sh },
7213	Type.usize,	7718	Type.usize,
7214	dst_mcv,	7719	dst_mcv,
		7720	Type.u8,
7215	.{ .immediate = field_off },	7721	.{ .immediate = field_off },
7216	);	7722	);
7217	}	7723	}
...	@@ -7237,11 +7743,11 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -7237,11 +7743,11 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
7237	const dst_regs: [2]Register = if (field_rc.supersetOf(container_rc) and	7743	const dst_regs: [2]Register = if (field_rc.supersetOf(container_rc) and
7238	self.reuseOperand(inst, operand, 0, src_mcv)) src_regs else dst: {	7744	self.reuseOperand(inst, operand, 0, src_mcv)) src_regs else dst: {
7239	const dst_regs =	7745	const dst_regs =
7240	try self.register_manager.allocRegs(2, .{ null, null }, field_rc);	7746	try self.register_manager.allocRegs(2, .{null} ** 2, field_rc);
7241	const dst_locks = self.register_manager.lockRegsAssumeUnused(2, dst_regs);	7747	const dst_locks = self.register_manager.lockRegsAssumeUnused(2, dst_regs);
7242	defer for (dst_locks) \|lock\| self.register_manager.unlockReg(lock);	7748	defer for (dst_locks) \|lock\| self.register_manager.unlockReg(lock);
7243		7749
7244	try self.genCopy(container_ty, .{ .register_pair = dst_regs }, src_mcv);	7750	try self.genCopy(container_ty, .{ .register_pair = dst_regs }, src_mcv, .{});
7245	break :dst dst_regs;	7751	break :dst dst_regs;
7246	};	7752	};
7247	const dst_mcv = MCValue{ .register_pair = dst_regs };	7753	const dst_mcv = MCValue{ .register_pair = dst_regs };
...	@@ -7255,6 +7761,7 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -7255,6 +7761,7 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
7255	.{ ._r, .sh },	7761	.{ ._r, .sh },
7256	Type.u128,	7762	Type.u128,
7257	dst_mcv,	7763	dst_mcv,
		7764	Type.u8,
7258	.{ .immediate = field_off },	7765	.{ .immediate = field_off },
7259	);	7766	);
7260	}	7767	}
...	@@ -7291,6 +7798,7 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -7291,6 +7798,7 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
7291	.{ ._r, .sh },	7798	.{ ._r, .sh },
7292	Type.usize,	7799	Type.usize,
7293	dst_mcv,	7800	dst_mcv,
		7801	Type.u8,
7294	.{ .immediate = field_off % 64 },	7802	.{ .immediate = field_off % 64 },
7295	);	7803	);
7296	}	7804	}
...	@@ -7345,7 +7853,7 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -7345,7 +7853,7 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
7345	const dst_lock = self.register_manager.lockRegAssumeUnused(dst_reg);	7853	const dst_lock = self.register_manager.lockRegAssumeUnused(dst_reg);
7346	defer self.register_manager.unlockReg(dst_lock);	7854	defer self.register_manager.unlockReg(dst_lock);
7347		7855
7348	try self.genCopy(int_ty, dst_mcv, off_mcv);	7856	try self.genCopy(int_ty, dst_mcv, off_mcv, .{});
7349	if (self.regExtraBits(field_ty) > 0) try self.truncateRegister(int_ty, dst_reg);	7857	if (self.regExtraBits(field_ty) > 0) try self.truncateRegister(int_ty, dst_reg);
7350	break :result if (field_is_gp)	7858	break :result if (field_is_gp)
7351	dst_mcv	7859	dst_mcv
...	@@ -7359,7 +7867,7 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -7359,7 +7867,7 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
7359	off_mcv	7867	off_mcv
7360	else dst: {	7868	else dst: {
7361	const dst_mcv = try self.allocRegOrMem(inst, true);	7869	const dst_mcv = try self.allocRegOrMem(inst, true);
7362	try self.genCopy(field_ty, dst_mcv, off_mcv);	7870	try self.genCopy(field_ty, dst_mcv, off_mcv, .{});
7363	break :dst dst_mcv;	7871	break :dst dst_mcv;
7364	};	7872	};
7365	if (field_abi_size * 8 > field_bit_size and dst_mcv.isMemory()) {	7873	if (field_abi_size * 8 > field_bit_size and dst_mcv.isMemory()) {
...	@@ -7369,9 +7877,9 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -7369,9 +7877,9 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
7369		7877
7370	const hi_mcv =	7878	const hi_mcv =
7371	dst_mcv.address().offset(@intCast(field_bit_size / 64 * 8)).deref();	7879	dst_mcv.address().offset(@intCast(field_bit_size / 64 * 8)).deref();
7372	try self.genSetReg(tmp_reg, Type.usize, hi_mcv);	7880	try self.genSetReg(tmp_reg, Type.usize, hi_mcv, .{});
7373	try self.truncateRegister(field_ty, tmp_reg);	7881	try self.truncateRegister(field_ty, tmp_reg);
7374	try self.genCopy(Type.usize, hi_mcv, .{ .register = tmp_reg });	7882	try self.genCopy(Type.usize, hi_mcv, .{ .register = tmp_reg }, .{});
7375	}	7883	}
7376	break :result dst_mcv;	7884	break :result dst_mcv;
7377	}	7885	}
...	@@ -7502,7 +8010,7 @@ fn genUnOp(self: *Self, maybe_inst: ?Air.Inst.Index, tag: Air.Inst.Tag, src_air:	...	@@ -7502,7 +8010,7 @@ fn genUnOp(self: *Self, maybe_inst: ?Air.Inst.Index, tag: Air.Inst.Tag, src_air:
7502	if (maybe_inst) \|inst\| if (self.reuseOperand(inst, src_air, 0, src_mcv)) break :dst src_mcv;	8010	if (maybe_inst) \|inst\| if (self.reuseOperand(inst, src_air, 0, src_mcv)) break :dst src_mcv;
7503		8011
7504	const dst_mcv = try self.allocRegOrMemAdvanced(src_ty, maybe_inst, true);	8012	const dst_mcv = try self.allocRegOrMemAdvanced(src_ty, maybe_inst, true);
7505	try self.genCopy(src_ty, dst_mcv, src_mcv);	8013	try self.genCopy(src_ty, dst_mcv, src_mcv, .{});
7506	break :dst dst_mcv;	8014	break :dst dst_mcv;
7507	};	8015	};
7508	const dst_lock = switch (dst_mcv) {	8016	const dst_lock = switch (dst_mcv) {
...	@@ -7549,9 +8057,9 @@ fn genUnOp(self: *Self, maybe_inst: ?Air.Inst.Index, tag: Air.Inst.Tag, src_air:	...	@@ -7549,9 +8057,9 @@ fn genUnOp(self: *Self, maybe_inst: ?Air.Inst.Index, tag: Air.Inst.Tag, src_air:
7549	defer self.register_manager.unlockReg(tmp_lock);	8057	defer self.register_manager.unlockReg(tmp_lock);
7550		8058
7551	const hi_mcv = dst_mcv.address().offset(@intCast(bit_size / 64 * 8)).deref();	8059	const hi_mcv = dst_mcv.address().offset(@intCast(bit_size / 64 * 8)).deref();
7552	try self.genSetReg(tmp_reg, Type.usize, hi_mcv);	8060	try self.genSetReg(tmp_reg, Type.usize, hi_mcv, .{});
7553	try self.truncateRegister(src_ty, tmp_reg);	8061	try self.truncateRegister(src_ty, tmp_reg);
7554	try self.genCopy(Type.usize, hi_mcv, .{ .register = tmp_reg });	8062	try self.genCopy(Type.usize, hi_mcv, .{ .register = tmp_reg }, .{});
7555	}	8063	}
7556	}	8064	}
7557	},	8065	},
...	@@ -7573,13 +8081,14 @@ fn genUnOpMir(self: *Self, mir_tag: Mir.Inst.FixedTag, dst_ty: Type, dst_mcv: MC	...	@@ -7573,13 +8081,14 @@ fn genUnOpMir(self: *Self, mir_tag: Mir.Inst.FixedTag, dst_ty: Type, dst_mcv: MC
7573	.register_offset,	8081	.register_offset,
7574	.eflags,	8082	.eflags,
7575	.register_overflow,	8083	.register_overflow,
		8084	.lea_symbol,
7576	.lea_direct,	8085	.lea_direct,
7577	.lea_got,	8086	.lea_got,
7578	.lea_tlv,	8087	.lea_tlv,
7579	.lea_frame,	8088	.lea_frame,
		8089	.elementwise_regs_then_frame,
7580	.reserved_frame,	8090	.reserved_frame,
7581	.air_ref,	8091	.air_ref,
7582	.lea_symbol,
7583	=> unreachable, // unmodifiable destination	8092	=> unreachable, // unmodifiable destination
7584	.register => \|dst_reg\| try self.asmRegister(mir_tag, registerAlias(dst_reg, abi_size)),	8093	.register => \|dst_reg\| try self.asmRegister(mir_tag, registerAlias(dst_reg, abi_size)),
7585	.register_pair => unreachable, // unimplemented	8094	.register_pair => unreachable, // unimplemented
...	@@ -7588,7 +8097,7 @@ fn genUnOpMir(self: *Self, mir_tag: Mir.Inst.FixedTag, dst_ty: Type, dst_mcv: MC	...	@@ -7588,7 +8097,7 @@ fn genUnOpMir(self: *Self, mir_tag: Mir.Inst.FixedTag, dst_ty: Type, dst_mcv: MC
7588	const addr_reg_lock = self.register_manager.lockRegAssumeUnused(addr_reg);	8097	const addr_reg_lock = self.register_manager.lockRegAssumeUnused(addr_reg);
7589	defer self.register_manager.unlockReg(addr_reg_lock);	8098	defer self.register_manager.unlockReg(addr_reg_lock);
7590		8099
7591	try self.genSetReg(addr_reg, Type.usize, dst_mcv.address());	8100	try self.genSetReg(addr_reg, Type.usize, dst_mcv.address(), .{});
7592	try self.asmMemory(mir_tag, .{ .base = .{ .reg = addr_reg }, .mod = .{ .rm = .{	8101	try self.asmMemory(mir_tag, .{ .base = .{ .reg = addr_reg }, .mod = .{ .rm = .{
7593	.size = Memory.Size.fromSize(abi_size),	8102	.size = Memory.Size.fromSize(abi_size),
7594	} } });	8103	} } });
...	@@ -7604,117 +8113,350 @@ fn genUnOpMir(self: *Self, mir_tag: Mir.Inst.FixedTag, dst_ty: Type, dst_mcv: MC	...	@@ -7604,117 +8113,350 @@ fn genUnOpMir(self: *Self, mir_tag: Mir.Inst.FixedTag, dst_ty: Type, dst_mcv: MC
7604	fn genShiftBinOpMir(	8113	fn genShiftBinOpMir(
7605	self: *Self,	8114	self: *Self,
7606	tag: Mir.Inst.FixedTag,	8115	tag: Mir.Inst.FixedTag,
7607	ty: Type,	8116	lhs_ty: Type,
7608	lhs_mcv: MCValue,	8117	lhs_mcv: MCValue,
7609	shift_mcv: MCValue,	8118	rhs_ty: Type,
		8119	rhs_mcv: MCValue,
7610	) !void {	8120	) !void {
7611	const mod = self.bin_file.comp.module.?;	8121	const mod = self.bin_file.comp.module.?;
7612	const rhs_mcv: MCValue = rhs: {	8122	const abi_size: u32 = @intCast(lhs_ty.abiSize(mod));
7613	switch (shift_mcv) {	8123	const shift_abi_size: u32 = @intCast(rhs_ty.abiSize(mod));
7614	.immediate => \|imm\| switch (imm) {	8124	try self.spillEflagsIfOccupied();
		8125
		8126	if (abi_size > 16) {
		8127	const limbs_len = math.divCeil(u32, abi_size, 8) catch unreachable;
		8128	assert(shift_abi_size >= 1 and shift_abi_size <= 2);
		8129
		8130	const rcx_lock: ?RegisterLock = switch (rhs_mcv) {
		8131	.immediate => \|shift_imm\| switch (shift_imm) {
7615	0 => return,	8132	0 => return,
7616	else => break :rhs shift_mcv,	8133	else => null,
7617	},	8134	},
7618	.register => \|shift_reg\| if (shift_reg == .rcx) break :rhs shift_mcv,	8135	else => lock: {
7619	else => {},	8136	if (switch (rhs_mcv) {
7620	}	8137	.register => \|rhs_reg\| rhs_reg.id() != Register.rcx.id(),
7621	self.register_manager.getRegAssumeFree(.rcx, null);	8138	else => true,
7622	try self.genSetReg(.cl, Type.u8, shift_mcv);	8139	}) {
7623	break :rhs .{ .register = .rcx };	8140	self.register_manager.getRegAssumeFree(.rcx, null);
7624	};	8141	try self.genSetReg(.rcx, rhs_ty, rhs_mcv, .{});
		8142	}
		8143	break :lock self.register_manager.lockReg(.rcx);
		8144	},
		8145	};
		8146	defer if (rcx_lock) \|lock\| self.register_manager.unlockReg(lock);
7625		8147
7626	const abi_size: u32 = @intCast(ty.abiSize(mod));	8148	const temp_regs = try self.register_manager.allocRegs(4, .{null} ** 4, abi.RegisterClass.gp);
7627	if (abi_size <= 8) {	8149	const temp_locks = self.register_manager.lockRegsAssumeUnused(4, temp_regs);
7628	switch (lhs_mcv) {	8150	defer for (temp_locks) \|lock\| self.register_manager.unlockReg(lock);
7629	.register => \|lhs_reg\| switch (rhs_mcv) {	8151
7630	.immediate => \|rhs_imm\| try self.asmRegisterImmediate(	8152	switch (tag[0]) {
7631	tag,	8153	._l => {
7632	registerAlias(lhs_reg, abi_size),	8154	try self.asmRegisterImmediate(.{ ._, .mov }, temp_regs[1].to32(), Immediate.u(limbs_len - 1));
7633	Immediate.u(rhs_imm),	8155	switch (rhs_mcv) {
7634	),	8156	.immediate => \|shift_imm\| try self.asmRegisterImmediate(
7635	.register => \|rhs_reg\| try self.asmRegisterRegister(	8157	.{ ._, .mov },
7636	tag,	8158	temp_regs[0].to32(),
7637	registerAlias(lhs_reg, abi_size),	8159	Immediate.u(limbs_len - (shift_imm >> 6) - 1),
7638	registerAlias(rhs_reg, 1),	8160	),
7639	),	8161	else => {
7640	else => return self.fail("TODO genShiftBinOpMir between {s} and {s}", .{	8162	try self.asmRegisterRegister(
7641	@tagName(lhs_mcv),	8163	.{ ._, .movzx },
7642	@tagName(rhs_mcv),	8164	temp_regs[2].to32(),
7643	}),	8165	registerAlias(.rcx, shift_abi_size),
		8166	);
		8167	try self.asmRegisterImmediate(
		8168	.{ ._, .@"and" },
		8169	.cl,
		8170	Immediate.u(std.math.maxInt(u6)),
		8171	);
		8172	try self.asmRegisterImmediate(
		8173	.{ ._r, .sh },
		8174	temp_regs[2].to32(),
		8175	Immediate.u(6),
		8176	);
		8177	try self.asmRegisterRegister(
		8178	.{ ._, .mov },
		8179	temp_regs[0].to32(),
		8180	temp_regs[1].to32(),
		8181	);
		8182	try self.asmRegisterRegister(
		8183	.{ ._, .sub },
		8184	temp_regs[0].to32(),
		8185	temp_regs[2].to32(),
		8186	);
		8187	},
		8188	}
7644	},	8189	},
7645	.memory, .indirect, .load_frame => {	8190	._r => {
7646	const lhs_mem: Memory = switch (lhs_mcv) {	8191	try self.asmRegisterRegister(.{ ._, .xor }, temp_regs[1].to32(), temp_regs[1].to32());
7647	.memory => \|addr\| .{	8192	switch (rhs_mcv) {
7648	.base = .{ .reg = .ds },	8193	.immediate => \|shift_imm\| try self.asmRegisterImmediate(
7649	.mod = .{ .rm = .{	8194	.{ ._, .mov },
7650	.size = Memory.Size.fromSize(abi_size),	8195	temp_regs[0].to32(),
7651	.disp = math.cast(i32, @as(i64, @bitCast(addr))) orelse	8196	Immediate.u(shift_imm >> 6),
7652	return self.fail("TODO genShiftBinOpMir between {s} and {s}", .{	8197	),
7653	@tagName(lhs_mcv),	8198	else => {
7654	@tagName(rhs_mcv),	8199	try self.asmRegisterRegister(
7655	}),	8200	.{ ._, .movzx },
7656	} },	8201	temp_regs[0].to32(),
		8202	registerAlias(.rcx, shift_abi_size),
		8203	);
		8204	try self.asmRegisterImmediate(
		8205	.{ ._, .@"and" },
		8206	.cl,
		8207	Immediate.u(std.math.maxInt(u6)),
		8208	);
		8209	try self.asmRegisterImmediate(
		8210	.{ ._r, .sh },
		8211	temp_regs[0].to32(),
		8212	Immediate.u(6),
		8213	);
7657	},	8214	},
7658	.indirect => \|reg_off\| .{	8215	}
7659	.base = .{ .reg = reg_off.reg },	8216	},
7660	.mod = .{ .rm = .{	8217	else => unreachable,
7661	.size = Memory.Size.fromSize(abi_size),	8218	}
7662	.disp = reg_off.off,	8219
7663	} },	8220	const slow_inc_dec = self.hasFeature(.slow_incdec);
		8221	if (switch (rhs_mcv) {
		8222	.immediate => \|shift_imm\| shift_imm >> 6 < limbs_len - 1,
		8223	else => true,
		8224	}) {
		8225	try self.asmRegisterMemory(.{ ._, .mov }, temp_regs[2].to64(), .{
		8226	.base = .{ .frame = lhs_mcv.load_frame.index },
		8227	.mod = .{ .rm = .{
		8228	.size = .qword,
		8229	.index = temp_regs[0].to64(),
		8230	.scale = .@"8",
		8231	.disp = lhs_mcv.load_frame.off,
		8232	} },
		8233	});
		8234	const skip = switch (rhs_mcv) {
		8235	.immediate => undefined,
		8236	else => switch (tag[0]) {
		8237	._l => try self.asmJccReloc(.z, undefined),
		8238	._r => skip: {
		8239	try self.asmRegisterImmediate(
		8240	.{ ._, .cmp },
		8241	temp_regs[0].to32(),
		8242	Immediate.u(limbs_len - 1),
		8243	);
		8244	break :skip try self.asmJccReloc(.nb, undefined);
7664	},	8245	},
7665	.load_frame => \|frame_addr\| .{	8246	else => unreachable,
7666	.base = .{ .frame = frame_addr.index },	8247	},
7667	.mod = .{ .rm = .{	8248	};
7668	.size = Memory.Size.fromSize(abi_size),	8249	const loop: Mir.Inst.Index = @intCast(self.mir_instructions.len);
7669	.disp = frame_addr.off,	8250	try self.asmRegisterMemory(.{ ._, .mov }, temp_regs[3].to64(), .{
7670	} },	8251	.base = .{ .frame = lhs_mcv.load_frame.index },
		8252	.mod = .{ .rm = .{
		8253	.size = .qword,
		8254	.index = temp_regs[0].to64(),
		8255	.scale = .@"8",
		8256	.disp = switch (tag[0]) {
		8257	._l => lhs_mcv.load_frame.off - 8,
		8258	._r => lhs_mcv.load_frame.off + 8,
		8259	else => unreachable,
7671	},	8260	},
		8261	} },
		8262	});
		8263	switch (rhs_mcv) {
		8264	.immediate => \|shift_imm\| try self.asmRegisterRegisterImmediate(
		8265	.{ switch (tag[0]) {
		8266	._l => ._ld,
		8267	._r => ._rd,
		8268	else => unreachable,
		8269	}, .sh },
		8270	temp_regs[2].to64(),
		8271	temp_regs[3].to64(),
		8272	Immediate.u(shift_imm & std.math.maxInt(u6)),
		8273	),
		8274	else => try self.asmRegisterRegisterRegister(.{ switch (tag[0]) {
		8275	._l => ._ld,
		8276	._r => ._rd,
7672	else => unreachable,	8277	else => unreachable,
7673	};	8278	}, .sh }, temp_regs[2].to64(), temp_regs[3].to64(), .cl),
7674	switch (rhs_mcv) {	8279	}
7675	.immediate => \|rhs_imm\| try self.asmMemoryImmediate(	8280	try self.asmMemoryRegister(.{ ._, .mov }, .{
7676	tag,	8281	.base = .{ .frame = lhs_mcv.load_frame.index },
7677	lhs_mem,	8282	.mod = .{ .rm = .{
7678	Immediate.u(rhs_imm),	8283	.size = .qword,
7679	),	8284	.index = temp_regs[1].to64(),
7680	.register => \|rhs_reg\| try self.asmMemoryRegister(	8285	.scale = .@"8",
7681	tag,	8286	.disp = lhs_mcv.load_frame.off,
7682	lhs_mem,	8287	} },
7683	registerAlias(rhs_reg, 1),	8288	}, temp_regs[2].to64());
7684	),	8289	try self.asmRegisterRegister(.{ ._, .mov }, temp_regs[2].to64(), temp_regs[3].to64());
7685	else => return self.fail("TODO genShiftBinOpMir between {s} and {s}", .{	8290	switch (tag[0]) {
7686	@tagName(lhs_mcv),	8291	._l => {
7687	@tagName(rhs_mcv),	8292	if (slow_inc_dec) {
7688	}),	8293	try self.asmRegisterImmediate(.{ ._, .sub }, temp_regs[1].to32(), Immediate.u(1));
7689	}	8294	try self.asmRegisterImmediate(.{ ._, .sub }, temp_regs[0].to32(), Immediate.u(1));
		8295	} else {
		8296	try self.asmRegister(.{ ._, .dec }, temp_regs[1].to32());
		8297	try self.asmRegister(.{ ._, .dec }, temp_regs[0].to32());
		8298	}
		8299	_ = try self.asmJccReloc(.nz, loop);
		8300	},
		8301	._r => {
		8302	if (slow_inc_dec) {
		8303	try self.asmRegisterImmediate(.{ ._, .add }, temp_regs[1].to32(), Immediate.u(1));
		8304	try self.asmRegisterImmediate(.{ ._, .add }, temp_regs[0].to32(), Immediate.u(1));
		8305	} else {
		8306	try self.asmRegister(.{ ._, .inc }, temp_regs[1].to32());
		8307	try self.asmRegister(.{ ._, .inc }, temp_regs[0].to32());
		8308	}
		8309	try self.asmRegisterImmediate(
		8310	.{ ._, .cmp },
		8311	temp_regs[0].to32(),
		8312	Immediate.u(limbs_len - 1),
		8313	);
		8314	_ = try self.asmJccReloc(.b, loop);
		8315	},
		8316	else => unreachable,
		8317	}
		8318	switch (rhs_mcv) {
		8319	.immediate => {},
		8320	else => self.performReloc(skip),
		8321	}
		8322	}
		8323	switch (rhs_mcv) {
		8324	.immediate => \|shift_imm\| try self.asmRegisterImmediate(
		8325	tag,
		8326	temp_regs[2].to64(),
		8327	Immediate.u(shift_imm & std.math.maxInt(u6)),
		8328	),
		8329	else => try self.asmRegisterRegister(tag, temp_regs[2].to64(), .cl),
		8330	}
		8331	try self.asmMemoryRegister(.{ ._, .mov }, .{
		8332	.base = .{ .frame = lhs_mcv.load_frame.index },
		8333	.mod = .{ .rm = .{
		8334	.size = .qword,
		8335	.index = temp_regs[1].to64(),
		8336	.scale = .@"8",
		8337	.disp = lhs_mcv.load_frame.off,
		8338	} },
		8339	}, temp_regs[2].to64());
		8340	if (tag[0] == ._r and tag[1] == .sa) try self.asmRegisterImmediate(
		8341	tag,
		8342	temp_regs[2].to64(),
		8343	Immediate.u(63),
		8344	);
		8345	if (switch (rhs_mcv) {
		8346	.immediate => \|shift_imm\| shift_imm >> 6 > 0,
		8347	else => true,
		8348	}) {
		8349	const skip = switch (rhs_mcv) {
		8350	.immediate => undefined,
		8351	else => switch (tag[0]) {
		8352	._l => skip: {
		8353	try self.asmRegisterRegister(
		8354	.{ ._, .@"test" },
		8355	temp_regs[1].to32(),
		8356	temp_regs[1].to32(),
		8357	);
		8358	break :skip try self.asmJccReloc(.z, undefined);
		8359	},
		8360	._r => skip: {
		8361	try self.asmRegisterImmediate(
		8362	.{ ._, .cmp },
		8363	temp_regs[1].to32(),
		8364	Immediate.u(limbs_len - 1),
		8365	);
		8366	break :skip try self.asmJccReloc(.nb, undefined);
		8367	},
		8368	else => unreachable,
		8369	},
		8370	};
		8371	const loop: Mir.Inst.Index = @intCast(self.mir_instructions.len);
		8372	switch (tag[0]) {
		8373	._l => if (slow_inc_dec) {
		8374	try self.asmRegisterImmediate(.{ ._, .sub }, temp_regs[1].to32(), Immediate.u(1));
		8375	} else {
		8376	try self.asmRegister(.{ ._, .dec }, temp_regs[1].to32());
		8377	},
		8378	._r => if (slow_inc_dec) {
		8379	try self.asmRegisterImmediate(.{ ._, .add }, temp_regs[1].to32(), Immediate.u(1));
		8380	} else {
		8381	try self.asmRegister(.{ ._, .inc }, temp_regs[1].to32());
		8382	},
		8383	else => unreachable,
		8384	}
		8385	if (tag[0] == ._r and tag[1] == .sa) try self.asmMemoryRegister(.{ ._, .mov }, .{
		8386	.base = .{ .frame = lhs_mcv.load_frame.index },
		8387	.mod = .{ .rm = .{
		8388	.size = .qword,
		8389	.index = temp_regs[1].to64(),
		8390	.scale = .@"8",
		8391	.disp = lhs_mcv.load_frame.off,
		8392	} },
		8393	}, temp_regs[2].to64()) else try self.asmMemoryImmediate(.{ ._, .mov }, .{
		8394	.base = .{ .frame = lhs_mcv.load_frame.index },
		8395	.mod = .{ .rm = .{
		8396	.size = .qword,
		8397	.index = temp_regs[1].to64(),
		8398	.scale = .@"8",
		8399	.disp = lhs_mcv.load_frame.off,
		8400	} },
		8401	}, Immediate.u(0));
		8402	switch (tag[0]) {
		8403	._l => _ = try self.asmJccReloc(.nz, loop),
		8404	._r => {
		8405	try self.asmRegisterImmediate(
		8406	.{ ._, .cmp },
		8407	temp_regs[1].to32(),
		8408	Immediate.u(limbs_len - 1),
		8409	);
		8410	_ = try self.asmJccReloc(.b, loop);
		8411	},
		8412	else => unreachable,
		8413	}
		8414	switch (rhs_mcv) {
		8415	.immediate => {},
		8416	else => self.performReloc(skip),
		8417	}
		8418	}
		8419	return;
		8420	}
		8421
		8422	assert(shift_abi_size == 1);
		8423	const shift_mcv: MCValue = shift: {
		8424	switch (rhs_mcv) {
		8425	.immediate => \|shift_imm\| switch (shift_imm) {
		8426	0 => return,
		8427	else => break :shift rhs_mcv,
7690	},	8428	},
7691	else => return self.fail("TODO genShiftBinOpMir between {s} and {s}", .{	8429	.register => \|rhs_reg\| if (rhs_reg.id() == Register.rcx.id())
7692	@tagName(lhs_mcv),	8430	break :shift rhs_mcv,
7693	@tagName(rhs_mcv),	8431	else => {},
7694	}),
7695	}	8432	}
7696	} else if (abi_size <= 16) {	8433	self.register_manager.getRegAssumeFree(.rcx, null);
		8434	try self.genSetReg(.cl, rhs_ty, rhs_mcv, .{});
		8435	break :shift .{ .register = .rcx };
		8436	};
		8437	if (abi_size > 8) {
7697	const info: struct { indices: [2]u31, double_tag: Mir.Inst.FixedTag } = switch (tag[0]) {	8438	const info: struct { indices: [2]u31, double_tag: Mir.Inst.FixedTag } = switch (tag[0]) {
7698	._l => .{ .indices = .{ 0, 1 }, .double_tag = .{ ._ld, .sh } },	8439	._l => .{ .indices = .{ 0, 1 }, .double_tag = .{ ._ld, .sh } },
7699	._r => .{ .indices = .{ 1, 0 }, .double_tag = .{ ._rd, .sh } },	8440	._r => .{ .indices = .{ 1, 0 }, .double_tag = .{ ._rd, .sh } },
7700	else => unreachable,	8441	else => unreachable,
7701	};	8442	};
7702	switch (lhs_mcv) {	8443	switch (lhs_mcv) {
7703	.register_pair => \|lhs_regs\| switch (rhs_mcv) {	8444	.register_pair => \|lhs_regs\| switch (shift_mcv) {
7704	.immediate => \|rhs_imm\| if (rhs_imm > 0 and rhs_imm < 64) {	8445	.immediate => \|shift_imm\| if (shift_imm > 0 and shift_imm < 64) {
7705	try self.asmRegisterRegisterImmediate(	8446	try self.asmRegisterRegisterImmediate(
7706	info.double_tag,	8447	info.double_tag,
7707	lhs_regs[info.indices[1]],	8448	lhs_regs[info.indices[1]],
7708	lhs_regs[info.indices[0]],	8449	lhs_regs[info.indices[0]],
7709	Immediate.u(rhs_imm),	8450	Immediate.u(shift_imm),
7710	);	8451	);
7711	try self.asmRegisterImmediate(	8452	try self.asmRegisterImmediate(
7712	tag,	8453	tag,
7713	lhs_regs[info.indices[0]],	8454	lhs_regs[info.indices[0]],
7714	Immediate.u(rhs_imm),	8455	Immediate.u(shift_imm),
7715	);	8456	);
		8457	return;
7716	} else {	8458	} else {
7717	assert(rhs_imm < 128);	8459	assert(shift_imm < 128);
7718	try self.asmRegisterRegister(	8460	try self.asmRegisterRegister(
7719	.{ ._, .mov },	8461	.{ ._, .mov },
7720	lhs_regs[info.indices[1]],	8462	lhs_regs[info.indices[1]],
...	@@ -7729,13 +8471,14 @@ fn genShiftBinOpMir(	...	@@ -7729,13 +8471,14 @@ fn genShiftBinOpMir(
7729	lhs_regs[info.indices[0]],	8471	lhs_regs[info.indices[0]],
7730	lhs_regs[info.indices[0]],	8472	lhs_regs[info.indices[0]],
7731	);	8473	);
7732	if (rhs_imm > 64) try self.asmRegisterImmediate(	8474	if (shift_imm > 64) try self.asmRegisterImmediate(
7733	tag,	8475	tag,
7734	lhs_regs[info.indices[1]],	8476	lhs_regs[info.indices[1]],
7735	Immediate.u(rhs_imm - 64),	8477	Immediate.u(shift_imm - 64),
7736	);	8478	);
		8479	return;
7737	},	8480	},
7738	.register => \|rhs_reg\| {	8481	.register => \|shift_reg\| {
7739	const tmp_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);	8482	const tmp_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
7740	const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);	8483	const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
7741	defer self.register_manager.unlockReg(tmp_lock);	8484	defer self.register_manager.unlockReg(tmp_lock);
...	@@ -7752,16 +8495,16 @@ fn genShiftBinOpMir(	...	@@ -7752,16 +8495,16 @@ fn genShiftBinOpMir(
7752	info.double_tag,	8495	info.double_tag,
7753	lhs_regs[info.indices[1]],	8496	lhs_regs[info.indices[1]],
7754	lhs_regs[info.indices[0]],	8497	lhs_regs[info.indices[0]],
7755	registerAlias(rhs_reg, 1),	8498	registerAlias(shift_reg, 1),
7756	);	8499	);
7757	try self.asmRegisterRegister(	8500	try self.asmRegisterRegister(
7758	tag,	8501	tag,
7759	lhs_regs[info.indices[0]],	8502	lhs_regs[info.indices[0]],
7760	registerAlias(rhs_reg, 1),	8503	registerAlias(shift_reg, 1),
7761	);	8504	);
7762	try self.asmRegisterImmediate(	8505	try self.asmRegisterImmediate(
7763	.{ ._, .cmp },	8506	.{ ._, .cmp },
7764	registerAlias(rhs_reg, 1),	8507	registerAlias(shift_reg, 1),
7765	Immediate.u(64),	8508	Immediate.u(64),
7766	);	8509	);
7767	try self.asmCmovccRegisterRegister(	8510	try self.asmCmovccRegisterRegister(
...	@@ -7770,19 +8513,17 @@ fn genShiftBinOpMir(	...	@@ -7770,19 +8513,17 @@ fn genShiftBinOpMir(
7770	lhs_regs[info.indices[0]],	8513	lhs_regs[info.indices[0]],
7771	);	8514	);
7772	try self.asmCmovccRegisterRegister(.ae, lhs_regs[info.indices[0]], tmp_reg);	8515	try self.asmCmovccRegisterRegister(.ae, lhs_regs[info.indices[0]], tmp_reg);
		8516	return;
7773	},	8517	},
7774	else => return self.fail("TODO genShiftBinOpMir between {s} and {s}", .{	8518	else => {},
7775	@tagName(lhs_mcv),
7776	@tagName(rhs_mcv),
7777	}),
7778	},	8519	},
7779	.load_frame => \|dst_frame_addr\| {	8520	.load_frame => \|dst_frame_addr\| {
7780	const tmp_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);	8521	const tmp_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
7781	const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);	8522	const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
7782	defer self.register_manager.unlockReg(tmp_lock);	8523	defer self.register_manager.unlockReg(tmp_lock);
7783		8524
7784	switch (rhs_mcv) {	8525	switch (shift_mcv) {
7785	.immediate => \|rhs_imm\| if (rhs_imm > 0 and rhs_imm < 64) {	8526	.immediate => \|shift_imm\| if (shift_imm > 0 and shift_imm < 64) {
7786	try self.asmRegisterMemory(	8527	try self.asmRegisterMemory(
7787	.{ ._, .mov },	8528	.{ ._, .mov },
7788	tmp_reg,	8529	tmp_reg,
...	@@ -7804,7 +8545,7 @@ fn genShiftBinOpMir(	...	@@ -7804,7 +8545,7 @@ fn genShiftBinOpMir(
7804	} },	8545	} },
7805	},	8546	},
7806	tmp_reg,	8547	tmp_reg,
7807	Immediate.u(rhs_imm),	8548	Immediate.u(shift_imm),
7808	);	8549	);
7809	try self.asmMemoryImmediate(	8550	try self.asmMemoryImmediate(
7810	tag,	8551	tag,
...	@@ -7815,10 +8556,11 @@ fn genShiftBinOpMir(	...	@@ -7815,10 +8556,11 @@ fn genShiftBinOpMir(
7815	.disp = dst_frame_addr.off + info.indices[0] * 8,	8556	.disp = dst_frame_addr.off + info.indices[0] * 8,
7816	} },	8557	} },
7817	},	8558	},
7818	Immediate.u(rhs_imm),	8559	Immediate.u(shift_imm),
7819	);	8560	);
		8561	return;
7820	} else {	8562	} else {
7821	assert(rhs_imm < 128);	8563	assert(shift_imm < 128);
7822	try self.asmRegisterMemory(	8564	try self.asmRegisterMemory(
7823	.{ ._, .mov },	8565	.{ ._, .mov },
7824	tmp_reg,	8566	tmp_reg,
...	@@ -7830,10 +8572,10 @@ fn genShiftBinOpMir(	...	@@ -7830,10 +8572,10 @@ fn genShiftBinOpMir(
7830	} },	8572	} },
7831	},	8573	},
7832	);	8574	);
7833	if (rhs_imm > 64) try self.asmRegisterImmediate(	8575	if (shift_imm > 64) try self.asmRegisterImmediate(
7834	tag,	8576	tag,
7835	tmp_reg,	8577	tmp_reg,
7836	Immediate.u(rhs_imm - 64),	8578	Immediate.u(shift_imm - 64),
7837	);	8579	);
7838	try self.asmMemoryRegister(	8580	try self.asmMemoryRegister(
7839	.{ ._, .mov },	8581	.{ ._, .mov },
...	@@ -7870,8 +8612,9 @@ fn genShiftBinOpMir(	...	@@ -7870,8 +8612,9 @@ fn genShiftBinOpMir(
7870	tmp_reg,	8612	tmp_reg,
7871	);	8613	);
7872	}	8614	}
		8615	return;
7873	},	8616	},
7874	.register => \|rhs_reg\| {	8617	.register => \|shift_reg\| {
7875	const first_reg =	8618	const first_reg =
7876	try self.register_manager.allocReg(null, abi.RegisterClass.gp);	8619	try self.register_manager.allocReg(null, abi.RegisterClass.gp);
7877	const first_lock = self.register_manager.lockRegAssumeUnused(first_reg);	8620	const first_lock = self.register_manager.lockRegAssumeUnused(first_reg);
...	@@ -7916,12 +8659,12 @@ fn genShiftBinOpMir(	...	@@ -7916,12 +8659,12 @@ fn genShiftBinOpMir(
7916	info.double_tag,	8659	info.double_tag,
7917	second_reg,	8660	second_reg,
7918	first_reg,	8661	first_reg,
7919	registerAlias(rhs_reg, 1),	8662	registerAlias(shift_reg, 1),
7920	);	8663	);
7921	try self.asmRegisterRegister(tag, first_reg, registerAlias(rhs_reg, 1));	8664	try self.asmRegisterRegister(tag, first_reg, registerAlias(shift_reg, 1));
7922	try self.asmRegisterImmediate(	8665	try self.asmRegisterImmediate(
7923	.{ ._, .cmp },	8666	.{ ._, .cmp },
7924	registerAlias(rhs_reg, 1),	8667	registerAlias(shift_reg, 1),
7925	Immediate.u(64),	8668	Immediate.u(64),
7926	);	8669	);
7927	try self.asmCmovccRegisterRegister(.ae, second_reg, first_reg);	8670	try self.asmCmovccRegisterRegister(.ae, second_reg, first_reg);
...	@@ -7948,21 +8691,75 @@ fn genShiftBinOpMir(	...	@@ -7948,21 +8691,75 @@ fn genShiftBinOpMir(
7948	},	8691	},
7949	first_reg,	8692	first_reg,
7950	);	8693	);
		8694	return;
7951	},	8695	},
7952	else => return self.fail("TODO genShiftBinOpMir between {s} and {s}", .{	8696	else => {},
7953	@tagName(lhs_mcv),
7954	@tagName(rhs_mcv),
7955	}),
7956	}	8697	}
7957	},	8698	},
7958	else => return self.fail("TODO genShiftBinOpMir between {s} and {s}", .{	8699	else => {},
7959	@tagName(lhs_mcv),
7960	@tagName(rhs_mcv),
7961	}),
7962	}	8700	}
7963	} else return self.fail("TODO genShiftBinOpMir between {s} and {s}", .{	8701	} else switch (lhs_mcv) {
		8702	.register => \|lhs_reg\| switch (shift_mcv) {
		8703	.immediate => \|shift_imm\| return self.asmRegisterImmediate(
		8704	tag,
		8705	registerAlias(lhs_reg, abi_size),
		8706	Immediate.u(shift_imm),
		8707	),
		8708	.register => \|shift_reg\| return self.asmRegisterRegister(
		8709	tag,
		8710	registerAlias(lhs_reg, abi_size),
		8711	registerAlias(shift_reg, 1),
		8712	),
		8713	else => {},
		8714	},
		8715	.memory, .indirect, .load_frame => {
		8716	const lhs_mem: Memory = switch (lhs_mcv) {
		8717	.memory => \|addr\| .{
		8718	.base = .{ .reg = .ds },
		8719	.mod = .{ .rm = .{
		8720	.size = Memory.Size.fromSize(abi_size),
		8721	.disp = math.cast(i32, @as(i64, @bitCast(addr))) orelse
		8722	return self.fail("TODO genShiftBinOpMir between {s} and {s}", .{
		8723	@tagName(lhs_mcv),
		8724	@tagName(shift_mcv),
		8725	}),
		8726	} },
		8727	},
		8728	.indirect => \|reg_off\| .{
		8729	.base = .{ .reg = reg_off.reg },
		8730	.mod = .{ .rm = .{
		8731	.size = Memory.Size.fromSize(abi_size),
		8732	.disp = reg_off.off,
		8733	} },
		8734	},
		8735	.load_frame => \|frame_addr\| .{
		8736	.base = .{ .frame = frame_addr.index },
		8737	.mod = .{ .rm = .{
		8738	.size = Memory.Size.fromSize(abi_size),
		8739	.disp = frame_addr.off,
		8740	} },
		8741	},
		8742	else => unreachable,
		8743	};
		8744	switch (shift_mcv) {
		8745	.immediate => \|shift_imm\| return self.asmMemoryImmediate(
		8746	tag,
		8747	lhs_mem,
		8748	Immediate.u(shift_imm),
		8749	),
		8750	.register => \|shift_reg\| return self.asmMemoryRegister(
		8751	tag,
		8752	lhs_mem,
		8753	registerAlias(shift_reg, 1),
		8754	),
		8755	else => {},
		8756	}
		8757	},
		8758	else => {},
		8759	}
		8760	return self.fail("TODO genShiftBinOpMir between {s} and {s}", .{
7964	@tagName(lhs_mcv),	8761	@tagName(lhs_mcv),
7965	@tagName(rhs_mcv),	8762	@tagName(shift_mcv),
7966	});	8763	});
7967	}	8764	}
7968		8765
...	@@ -7983,17 +8780,9 @@ fn genShiftBinOp(	...	@@ -7983,17 +8780,9 @@ fn genShiftBinOp(
7983	lhs_ty.fmt(mod),	8780	lhs_ty.fmt(mod),
7984	});	8781	});
7985		8782
7986	assert(rhs_ty.abiSize(mod) == 1);
7987	try self.spillEflagsIfOccupied();
7988
7989	const lhs_abi_size = lhs_ty.abiSize(mod);
7990	if (lhs_abi_size > 16) return self.fail("TODO implement genShiftBinOp for {}", .{
7991	lhs_ty.fmt(mod),
7992	});
7993
7994	try self.register_manager.getReg(.rcx, null);	8783	try self.register_manager.getReg(.rcx, null);
7995	const rcx_lock = self.register_manager.lockRegAssumeUnused(.rcx);	8784	const rcx_lock = self.register_manager.lockReg(.rcx);
7996	defer self.register_manager.unlockReg(rcx_lock);	8785	defer if (rcx_lock) \|lock\| self.register_manager.unlockReg(lock);
7997		8786
7998	const lhs_lock = switch (lhs_mcv) {	8787	const lhs_lock = switch (lhs_mcv) {
7999	.register => \|reg\| self.register_manager.lockReg(reg),	8788	.register => \|reg\| self.register_manager.lockReg(reg),
...	@@ -8013,7 +8802,7 @@ fn genShiftBinOp(	...	@@ -8013,7 +8802,7 @@ fn genShiftBinOp(
8013	if (self.reuseOperand(inst, bin_op.lhs, 0, lhs_mcv)) break :dst lhs_mcv;	8802	if (self.reuseOperand(inst, bin_op.lhs, 0, lhs_mcv)) break :dst lhs_mcv;
8014	}	8803	}
8015	const dst_mcv = try self.allocRegOrMemAdvanced(lhs_ty, maybe_inst, true);	8804	const dst_mcv = try self.allocRegOrMemAdvanced(lhs_ty, maybe_inst, true);
8016	try self.genCopy(lhs_ty, dst_mcv, lhs_mcv);	8805	try self.genCopy(lhs_ty, dst_mcv, lhs_mcv, .{});
8017	break :dst dst_mcv;	8806	break :dst dst_mcv;
8018	};	8807	};
8019		8808
...	@@ -8028,7 +8817,7 @@ fn genShiftBinOp(	...	@@ -8028,7 +8817,7 @@ fn genShiftBinOp(
8028	.unsigned => .{ ._r, .sh },	8817	.unsigned => .{ ._r, .sh },
8029	},	8818	},
8030	else => unreachable,	8819	else => unreachable,
8031	}, lhs_ty, dst_mcv, rhs_mcv);	8820	}, lhs_ty, dst_mcv, rhs_ty, rhs_mcv);
8032	return dst_mcv;	8821	return dst_mcv;
8033	}	8822	}
8034		8823
...	@@ -8053,13 +8842,14 @@ fn genMulDivBinOp(	...	@@ -8053,13 +8842,14 @@ fn genMulDivBinOp(
8053	const src_abi_size: u32 = @intCast(src_ty.abiSize(mod));	8842	const src_abi_size: u32 = @intCast(src_ty.abiSize(mod));
8054		8843
8055	assert(self.register_manager.isRegFree(.rax));	8844	assert(self.register_manager.isRegFree(.rax));
		8845	assert(self.register_manager.isRegFree(.rcx));
8056	assert(self.register_manager.isRegFree(.rdx));	8846	assert(self.register_manager.isRegFree(.rdx));
8057	assert(self.eflags_inst == null);	8847	assert(self.eflags_inst == null);
8058		8848
8059	if (dst_abi_size == 16 and src_abi_size == 16) {	8849	if (dst_abi_size == 16 and src_abi_size == 16) {
8060	assert(tag == .mul or tag == .mul_wrap);	8850	assert(tag == .mul or tag == .mul_wrap);
8061	const reg_locks = self.register_manager.lockRegsAssumeUnused(2, .{ .rax, .rdx });	8851	const reg_locks = self.register_manager.lockRegs(2, .{ .rax, .rdx });
8062	defer for (reg_locks) \|lock\| self.register_manager.unlockReg(lock);	8852	defer for (reg_locks) \|reg_lock\| if (reg_lock) \|lock\| self.register_manager.unlockReg(lock);
8063		8853
8064	const mat_lhs_mcv = switch (lhs_mcv) {	8854	const mat_lhs_mcv = switch (lhs_mcv) {
8065	.load_symbol => mat_lhs_mcv: {	8855	.load_symbol => mat_lhs_mcv: {
...	@@ -8124,10 +8914,172 @@ fn genMulDivBinOp(	...	@@ -8124,10 +8914,172 @@ fn genMulDivBinOp(
8124	else => unreachable,	8914	else => unreachable,
8125	.mul, .mul_wrap => dst_abi_size != src_abi_size and dst_abi_size != src_abi_size * 2,	8915	.mul, .mul_wrap => dst_abi_size != src_abi_size and dst_abi_size != src_abi_size * 2,
8126	.div_trunc, .div_floor, .div_exact, .rem, .mod => dst_abi_size != src_abi_size,	8916	.div_trunc, .div_floor, .div_exact, .rem, .mod => dst_abi_size != src_abi_size,
8127	} or src_abi_size > 8) return self.fail(	8917	} or src_abi_size > 8) {
8128	"TODO implement genMulDivBinOp for {s} from {} to {}",	8918	const src_info = src_ty.intInfo(mod);
8129	.{ @tagName(tag), src_ty.fmt(mod), dst_ty.fmt(mod) },	8919	switch (tag) {
8130	);	8920	.mul, .mul_wrap => {
		8921	const slow_inc = self.hasFeature(.slow_incdec);
		8922	const limb_len = std.math.divCeil(u32, src_abi_size, 8) catch unreachable;
		8923
		8924	try self.spillRegisters(&.{ .rax, .rcx, .rdx });
		8925	const reg_locks = self.register_manager.lockRegs(3, .{ .rax, .rcx, .rdx });
		8926	defer for (reg_locks) \|reg_lock\| if (reg_lock) \|lock\|
		8927	self.register_manager.unlockReg(lock);
		8928
		8929	const dst_mcv = try self.allocRegOrMemAdvanced(dst_ty, maybe_inst, false);
		8930	try self.genInlineMemset(
		8931	dst_mcv.address(),
		8932	.{ .immediate = 0 },
		8933	.{ .immediate = src_abi_size },
		8934	.{},
		8935	);
		8936
		8937	const temp_regs =
		8938	try self.register_manager.allocRegs(4, .{null} ** 4, abi.RegisterClass.gp);
		8939	const temp_locks = self.register_manager.lockRegsAssumeUnused(4, temp_regs);
		8940	defer for (temp_locks) \|lock\| self.register_manager.unlockReg(lock);
		8941
		8942	try self.asmRegisterRegister(.{ ._, .xor }, temp_regs[0].to32(), temp_regs[0].to32());
		8943
		8944	const outer_loop: Mir.Inst.Index = @intCast(self.mir_instructions.len);
		8945	try self.asmRegisterMemory(.{ ._, .mov }, temp_regs[1].to64(), .{
		8946	.base = .{ .frame = rhs_mcv.load_frame.index },
		8947	.mod = .{ .rm = .{
		8948	.size = .qword,
		8949	.index = temp_regs[0].to64(),
		8950	.scale = .@"8",
		8951	.disp = rhs_mcv.load_frame.off,
		8952	} },
		8953	});
		8954	try self.asmRegisterRegister(.{ ._, .@"test" }, temp_regs[1].to64(), temp_regs[1].to64());
		8955	const skip_inner = try self.asmJccReloc(.z, undefined);
		8956
		8957	try self.asmRegisterRegister(.{ ._, .xor }, temp_regs[2].to32(), temp_regs[2].to32());
		8958	try self.asmRegisterRegister(.{ ._, .mov }, temp_regs[3].to32(), temp_regs[0].to32());
		8959	try self.asmRegisterRegister(.{ ._, .xor }, .ecx, .ecx);
		8960	try self.asmRegisterRegister(.{ ._, .xor }, .edx, .edx);
		8961
		8962	const inner_loop: Mir.Inst.Index = @intCast(self.mir_instructions.len);
		8963	try self.asmRegisterImmediate(.{ ._r, .sh }, .cl, Immediate.u(1));
		8964	try self.asmMemoryRegister(.{ ._, .adc }, .{
		8965	.base = .{ .frame = dst_mcv.load_frame.index },
		8966	.mod = .{ .rm = .{
		8967	.size = .qword,
		8968	.index = temp_regs[3].to64(),
		8969	.scale = .@"8",
		8970	.disp = dst_mcv.load_frame.off,
		8971	} },
		8972	}, .rdx);
		8973	try self.asmSetccRegister(.c, .cl);
		8974
		8975	try self.asmRegisterMemory(.{ ._, .mov }, .rax, .{
		8976	.base = .{ .frame = lhs_mcv.load_frame.index },
		8977	.mod = .{ .rm = .{
		8978	.size = .qword,
		8979	.index = temp_regs[2].to64(),
		8980	.scale = .@"8",
		8981	.disp = lhs_mcv.load_frame.off,
		8982	} },
		8983	});
		8984	try self.asmRegister(.{ ._, .mul }, temp_regs[1].to64());
		8985
		8986	try self.asmRegisterImmediate(.{ ._r, .sh }, .ch, Immediate.u(1));
		8987	try self.asmMemoryRegister(.{ ._, .adc }, .{
		8988	.base = .{ .frame = dst_mcv.load_frame.index },
		8989	.mod = .{ .rm = .{
		8990	.size = .qword,
		8991	.index = temp_regs[3].to64(),
		8992	.scale = .@"8",
		8993	.disp = dst_mcv.load_frame.off,
		8994	} },
		8995	}, .rax);
		8996	try self.asmSetccRegister(.c, .ch);
		8997
		8998	if (slow_inc) {
		8999	try self.asmRegisterImmediate(.{ ._, .add }, temp_regs[2].to32(), Immediate.u(1));
		9000	try self.asmRegisterImmediate(.{ ._, .add }, temp_regs[3].to32(), Immediate.u(1));
		9001	} else {
		9002	try self.asmRegister(.{ ._, .inc }, temp_regs[2].to32());
		9003	try self.asmRegister(.{ ._, .inc }, temp_regs[3].to32());
		9004	}
		9005	try self.asmRegisterImmediate(
		9006	.{ ._, .cmp },
		9007	temp_regs[3].to32(),
		9008	Immediate.u(limb_len),
		9009	);
		9010	_ = try self.asmJccReloc(.b, inner_loop);
		9011
		9012	self.performReloc(skip_inner);
		9013	if (slow_inc) {
		9014	try self.asmRegisterImmediate(.{ ._, .add }, temp_regs[0].to32(), Immediate.u(1));
		9015	} else {
		9016	try self.asmRegister(.{ ._, .inc }, temp_regs[0].to32());
		9017	}
		9018	try self.asmRegisterImmediate(
		9019	.{ ._, .cmp },
		9020	temp_regs[0].to32(),
		9021	Immediate.u(limb_len),
		9022	);
		9023	_ = try self.asmJccReloc(.b, outer_loop);
		9024
		9025	return dst_mcv;
		9026	},
		9027	.div_trunc, .div_floor, .div_exact, .rem, .mod => switch (src_info.signedness) {
		9028	.signed => {},
		9029	.unsigned => {
		9030	const dst_mcv = try self.allocRegOrMemAdvanced(dst_ty, maybe_inst, false);
		9031	const manyptr_u32_ty = try mod.ptrType(.{
		9032	.child = .u32_type,
		9033	.flags = .{
		9034	.size = .Many,
		9035	},
		9036	});
		9037	const manyptr_const_u32_ty = try mod.ptrType(.{
		9038	.child = .u32_type,
		9039	.flags = .{
		9040	.size = .Many,
		9041	.is_const = true,
		9042	},
		9043	});
		9044	_ = try self.genCall(.{ .lib = .{
		9045	.return_type = .void_type,
		9046	.param_types = &.{
		9047	manyptr_u32_ty.toIntern(),
		9048	manyptr_const_u32_ty.toIntern(),
		9049	manyptr_const_u32_ty.toIntern(),
		9050	.usize_type,
		9051	},
		9052	.callee = switch (tag) {
		9053	.div_trunc,
		9054	.div_floor,
		9055	.div_exact,
		9056	=> "__udivei4",
		9057	.rem,
		9058	.mod,
		9059	=> "__umodei4",
		9060	else => unreachable,
		9061	},
		9062	} }, &.{
		9063	manyptr_u32_ty,
		9064	manyptr_const_u32_ty,
		9065	manyptr_const_u32_ty,
		9066	Type.usize,
		9067	}, &.{
		9068	dst_mcv.address(),
		9069	lhs_mcv.address(),
		9070	rhs_mcv.address(),
		9071	.{ .immediate = src_info.bits },
		9072	});
		9073	return dst_mcv;
		9074	},
		9075	},
		9076	else => {},
		9077	}
		9078	return self.fail(
		9079	"TODO implement genMulDivBinOp for {s} from {} to {}",
		9080	.{ @tagName(tag), src_ty.fmt(mod), dst_ty.fmt(mod) },
		9081	);
		9082	}
8131	const ty = if (dst_abi_size <= 8) dst_ty else src_ty;	9083	const ty = if (dst_abi_size <= 8) dst_ty else src_ty;
8132	const abi_size = if (dst_abi_size <= 8) dst_abi_size else src_abi_size;	9084	const abi_size = if (dst_abi_size <= 8) dst_abi_size else src_abi_size;
8133		9085
...	@@ -8311,6 +9263,7 @@ fn genBinOp(	...	@@ -8311,6 +9263,7 @@ fn genBinOp(
8311	.div_float,	9263	.div_float,
8312	.div_trunc,	9264	.div_trunc,
8313	.div_floor,	9265	.div_floor,
		9266	.div_exact,
8314	=> std.fmt.bufPrint(&callee_buf, "__{s}{c}f3", .{	9267	=> std.fmt.bufPrint(&callee_buf, "__{s}{c}f3", .{
8315	@tagName(air_tag)[0..3],	9268	@tagName(air_tag)[0..3],
8316	floatCompilerRtAbiName(float_bits),	9269	floatCompilerRtAbiName(float_bits),
...	@@ -8464,7 +9417,7 @@ fn genBinOp(	...	@@ -8464,7 +9417,7 @@ fn genBinOp(
8464	else => false,	9417	else => false,
8465	.Float => true,	9418	.Float => true,
8466	.Vector => switch (lhs_ty.childType(mod).toIntern()) {	9419	.Vector => switch (lhs_ty.childType(mod).toIntern()) {
8467	.bool_type => false,	9420	.bool_type, .u1_type => false,
8468	else => true,	9421	else => true,
8469	},	9422	},
8470	};	9423	};
...	@@ -8490,6 +9443,7 @@ fn genBinOp(	...	@@ -8490,6 +9443,7 @@ fn genBinOp(
8490		9443
8491	const ordered_air: [2]Air.Inst.Ref = if (lhs_ty.isVector(mod) and	9444	const ordered_air: [2]Air.Inst.Ref = if (lhs_ty.isVector(mod) and
8492	switch (lhs_ty.childType(mod).zigTypeTag(mod)) {	9445	switch (lhs_ty.childType(mod).zigTypeTag(mod)) {
		9446	.Bool => false,
8493	.Int => switch (air_tag) {	9447	.Int => switch (air_tag) {
8494	.cmp_lt, .cmp_gte => true,	9448	.cmp_lt, .cmp_gte => true,
8495	else => false,	9449	else => false,
...	@@ -8548,14 +9502,14 @@ fn genBinOp(	...	@@ -8548,14 +9502,14 @@ fn genBinOp(
8548	const locks = self.register_manager.lockRegsAssumeUnused(2, lhs_regs);	9502	const locks = self.register_manager.lockRegsAssumeUnused(2, lhs_regs);
8549	break :locks .{ locks[0], locks[1] };	9503	break :locks .{ locks[0], locks[1] };
8550	},	9504	},
8551	else => .{ null, null },	9505	else => .{null} ** 2,
8552	};	9506	};
8553	defer for (lhs_locks) \|lhs_lock\| if (lhs_lock) \|lock\| self.register_manager.unlockReg(lock);	9507	defer for (lhs_locks) \|lhs_lock\| if (lhs_lock) \|lock\| self.register_manager.unlockReg(lock);
8554		9508
8555	const rhs_locks: [2]?RegisterLock = switch (rhs_mcv) {	9509	const rhs_locks: [2]?RegisterLock = switch (rhs_mcv) {
8556	.register => \|rhs_reg\| .{ self.register_manager.lockReg(rhs_reg), null },	9510	.register => \|rhs_reg\| .{ self.register_manager.lockReg(rhs_reg), null },
8557	.register_pair => \|rhs_regs\| self.register_manager.lockRegs(2, rhs_regs),	9511	.register_pair => \|rhs_regs\| self.register_manager.lockRegs(2, rhs_regs),
8558	else => .{ null, null },	9512	else => .{null} ** 2,
8559	};	9513	};
8560	defer for (rhs_locks) \|rhs_lock\| if (rhs_lock) \|lock\| self.register_manager.unlockReg(lock);	9514	defer for (rhs_locks) \|rhs_lock\| if (rhs_lock) \|lock\| self.register_manager.unlockReg(lock);
8561		9515
...	@@ -8581,14 +9535,14 @@ fn genBinOp(	...	@@ -8581,14 +9535,14 @@ fn genBinOp(
8581	if (sse_op and lhs_mcv.isRegister() and self.hasFeature(.avx))	9535	if (sse_op and lhs_mcv.isRegister() and self.hasFeature(.avx))
8582	copied_to_dst = false	9536	copied_to_dst = false
8583	else	9537	else
8584	try self.genCopy(lhs_ty, dst_mcv, lhs_mcv);	9538	try self.genCopy(lhs_ty, dst_mcv, lhs_mcv, .{});
8585	rhs_mcv = try self.resolveInst(ordered_air[1]);	9539	rhs_mcv = try self.resolveInst(ordered_air[1]);
8586	break :dst dst_mcv;	9540	break :dst dst_mcv;
8587	};	9541	};
8588	const dst_locks: [2]?RegisterLock = switch (dst_mcv) {	9542	const dst_locks: [2]?RegisterLock = switch (dst_mcv) {
8589	.register => \|dst_reg\| .{ self.register_manager.lockReg(dst_reg), null },	9543	.register => \|dst_reg\| .{ self.register_manager.lockReg(dst_reg), null },
8590	.register_pair => \|dst_regs\| self.register_manager.lockRegs(2, dst_regs),	9544	.register_pair => \|dst_regs\| self.register_manager.lockRegs(2, dst_regs),
8591	else => .{ null, null },	9545	else => .{null} ** 2,
8592	};	9546	};
8593	defer for (dst_locks) \|dst_lock\| if (dst_lock) \|lock\| self.register_manager.unlockReg(lock);	9547	defer for (dst_locks) \|dst_lock\| if (dst_lock) \|lock\| self.register_manager.unlockReg(lock);
8594		9548
...	@@ -8596,7 +9550,7 @@ fn genBinOp(	...	@@ -8596,7 +9550,7 @@ fn genBinOp(
8596	const src_mcv: MCValue = if (maybe_mask_reg) \|mask_reg\|	9550	const src_mcv: MCValue = if (maybe_mask_reg) \|mask_reg\|
8597	if (self.hasFeature(.avx) and unmat_src_mcv.isRegister() and maybe_inst != null and	9551	if (self.hasFeature(.avx) and unmat_src_mcv.isRegister() and maybe_inst != null and
8598	self.liveness.operandDies(maybe_inst.?, if (flipped) 0 else 1)) unmat_src_mcv else src: {	9552	self.liveness.operandDies(maybe_inst.?, if (flipped) 0 else 1)) unmat_src_mcv else src: {
8599	try self.genSetReg(mask_reg, rhs_ty, unmat_src_mcv);	9553	try self.genSetReg(mask_reg, rhs_ty, unmat_src_mcv, .{});
8600	break :src .{ .register = mask_reg };	9554	break :src .{ .register = mask_reg };
8601	}	9555	}
8602	else	9556	else
...	@@ -8604,7 +9558,7 @@ fn genBinOp(	...	@@ -8604,7 +9558,7 @@ fn genBinOp(
8604	const src_locks: [2]?RegisterLock = switch (src_mcv) {	9558	const src_locks: [2]?RegisterLock = switch (src_mcv) {
8605	.register => \|src_reg\| .{ self.register_manager.lockReg(src_reg), null },	9559	.register => \|src_reg\| .{ self.register_manager.lockReg(src_reg), null },
8606	.register_pair => \|src_regs\| self.register_manager.lockRegs(2, src_regs),	9560	.register_pair => \|src_regs\| self.register_manager.lockRegs(2, src_regs),
8607	else => .{ null, null },	9561	else => .{null} ** 2,
8608	};	9562	};
8609	defer for (src_locks) \|src_lock\| if (src_lock) \|lock\| self.register_manager.unlockReg(lock);	9563	defer for (src_locks) \|src_lock\| if (src_lock) \|lock\| self.register_manager.unlockReg(lock);
8610		9564
...	@@ -8664,14 +9618,13 @@ fn genBinOp(	...	@@ -8664,14 +9618,13 @@ fn genBinOp(
8664	else => dst: {	9618	else => dst: {
8665	const dst_regs = try self.register_manager.allocRegs(	9619	const dst_regs = try self.register_manager.allocRegs(
8666	2,	9620	2,
8667	.{ null, null },	9621	.{null} ** 2,
8668	abi.RegisterClass.gp,	9622	abi.RegisterClass.gp,
8669	);	9623	);
8670	const dst_regs_locks = self.register_manager.lockRegs(2, dst_regs);	9624	const dst_regs_locks = self.register_manager.lockRegsAssumeUnused(2, dst_regs);
8671	defer for (dst_regs_locks) \|dst_lock\| if (dst_lock) \|lock\|	9625	defer for (dst_regs_locks) \|lock\| self.register_manager.unlockReg(lock);
8672	self.register_manager.unlockReg(lock);
8673		9626
8674	try self.genCopy(lhs_ty, .{ .register_pair = dst_regs }, dst_mcv);	9627	try self.genCopy(lhs_ty, .{ .register_pair = dst_regs }, dst_mcv, .{});
8675	break :dst dst_regs;	9628	break :dst dst_regs;
8676	},	9629	},
8677	};	9630	};
...	@@ -8726,7 +9679,7 @@ fn genBinOp(	...	@@ -8726,7 +9679,7 @@ fn genBinOp(
8726	try self.asmCmovccRegisterRegister(cc, dst_regs[0], src_mcv.register_pair[0]);	9679	try self.asmCmovccRegisterRegister(cc, dst_regs[0], src_mcv.register_pair[0]);
8727	try self.asmCmovccRegisterRegister(cc, dst_regs[1], src_mcv.register_pair[1]);	9680	try self.asmCmovccRegisterRegister(cc, dst_regs[1], src_mcv.register_pair[1]);
8728	}	9681	}
8729	try self.genCopy(lhs_ty, dst_mcv, .{ .register_pair = dst_regs });	9682	try self.genCopy(lhs_ty, dst_mcv, .{ .register_pair = dst_regs }, .{});
8730	} else {	9683	} else {
8731	const mat_src_mcv: MCValue = if (switch (resolved_src_mcv) {	9684	const mat_src_mcv: MCValue = if (switch (resolved_src_mcv) {
8732	.immediate,	9685	.immediate,
...	@@ -8799,6 +9752,7 @@ fn genBinOp(	...	@@ -8799,6 +9752,7 @@ fn genBinOp(
8799	.load_tlv,	9752	.load_tlv,
8800	.lea_tlv,	9753	.lea_tlv,
8801	.lea_frame,	9754	.lea_frame,
		9755	.elementwise_regs_then_frame,
8802	.reserved_frame,	9756	.reserved_frame,
8803	.air_ref,	9757	.air_ref,
8804	=> unreachable,	9758	=> unreachable,
...	@@ -8836,7 +9790,17 @@ fn genBinOp(	...	@@ -8836,7 +9790,17 @@ fn genBinOp(
8836	},	9790	},
8837	),	9791	),
8838	}	9792	}
8839	try self.genCopy(lhs_ty, dst_mcv, .{ .register = tmp_reg });	9793	try self.genCopy(lhs_ty, dst_mcv, .{ .register = tmp_reg }, .{});
		9794	}
		9795	},
		9796
		9797	.cmp_eq, .cmp_neq => {
		9798	assert(lhs_ty.isVector(mod) and lhs_ty.childType(mod).toIntern() == .bool_type);
		9799	try self.genBinOpMir(.{ ._, .xor }, lhs_ty, dst_mcv, src_mcv);
		9800	switch (air_tag) {
		9801	.cmp_eq => try self.genUnOpMir(.{ ._, .not }, lhs_ty, dst_mcv),
		9802	.cmp_neq => {},
		9803	else => unreachable,
8840	}	9804	}
8841	},	9805	},
8842		9806
...	@@ -10034,6 +10998,7 @@ fn genBinOpMir(	...	@@ -10034,6 +10998,7 @@ fn genBinOpMir(
10034	.lea_tlv,	10998	.lea_tlv,
10035	.lea_frame,	10999	.lea_frame,
10036	.lea_symbol,	11000	.lea_symbol,
		11001	.elementwise_regs_then_frame,
10037	.reserved_frame,	11002	.reserved_frame,
10038	.air_ref,	11003	.air_ref,
10039	=> unreachable, // unmodifiable destination	11004	=> unreachable, // unmodifiable destination
...	@@ -10068,6 +11033,7 @@ fn genBinOpMir(	...	@@ -10068,6 +11033,7 @@ fn genBinOpMir(
10068	.dead,	11033	.dead,
10069	.undef,	11034	.undef,
10070	.register_overflow,	11035	.register_overflow,
		11036	.elementwise_regs_then_frame,
10071	.reserved_frame,	11037	.reserved_frame,
10072	=> unreachable,	11038	=> unreachable,
10073	.register, .register_pair => try self.asmRegisterRegister(	11039	.register, .register_pair => try self.asmRegisterRegister(
...	@@ -10209,7 +11175,7 @@ fn genBinOpMir(	...	@@ -10209,7 +11175,7 @@ fn genBinOpMir(
10209	const dst_addr_lock = self.register_manager.lockRegAssumeUnused(dst_addr_reg);	11175	const dst_addr_lock = self.register_manager.lockRegAssumeUnused(dst_addr_reg);
10210	errdefer self.register_manager.unlockReg(dst_addr_lock);	11176	errdefer self.register_manager.unlockReg(dst_addr_lock);
10211		11177
10212	try self.genSetReg(dst_addr_reg, Type.usize, dst_mcv.address());	11178	try self.genSetReg(dst_addr_reg, Type.usize, dst_mcv.address(), .{});
10213	break :dst .{ .addr_reg = dst_addr_reg, .addr_lock = dst_addr_lock };	11179	break :dst .{ .addr_reg = dst_addr_reg, .addr_lock = dst_addr_lock };
10214	},	11180	},
10215	.load_frame => null,	11181	.load_frame => null,
...	@@ -10226,6 +11192,7 @@ fn genBinOpMir(	...	@@ -10226,6 +11192,7 @@ fn genBinOpMir(
10226	.dead,	11192	.dead,
10227	.undef,	11193	.undef,
10228	.register_overflow,	11194	.register_overflow,
		11195	.elementwise_regs_then_frame,
10229	.reserved_frame,	11196	.reserved_frame,
10230	.air_ref,	11197	.air_ref,
10231	=> unreachable,	11198	=> unreachable,
...	@@ -10256,7 +11223,7 @@ fn genBinOpMir(	...	@@ -10256,7 +11223,7 @@ fn genBinOpMir(
10256	const src_addr_lock = self.register_manager.lockRegAssumeUnused(src_addr_reg);	11223	const src_addr_lock = self.register_manager.lockRegAssumeUnused(src_addr_reg);
10257	errdefer self.register_manager.unlockReg(src_addr_lock);	11224	errdefer self.register_manager.unlockReg(src_addr_lock);
10258		11225
10259	try self.genSetReg(src_addr_reg, Type.usize, resolved_src_mcv.address());	11226	try self.genSetReg(src_addr_reg, Type.usize, resolved_src_mcv.address(), .{});
10260	break :src .{ .addr_reg = src_addr_reg, .addr_lock = src_addr_lock };	11227	break :src .{ .addr_reg = src_addr_reg, .addr_lock = src_addr_lock };
10261	},	11228	},
10262	};	11229	};
...	@@ -10320,6 +11287,7 @@ fn genBinOpMir(	...	@@ -10320,6 +11287,7 @@ fn genBinOpMir(
10320	.dead,	11287	.dead,
10321	.undef,	11288	.undef,
10322	.register_overflow,	11289	.register_overflow,
		11290	.elementwise_regs_then_frame,
10323	.reserved_frame,	11291	.reserved_frame,
10324	.air_ref,	11292	.air_ref,
10325	=> unreachable,	11293	=> unreachable,
...	@@ -10455,6 +11423,7 @@ fn genIntMulComplexOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: M	...	@@ -10455,6 +11423,7 @@ fn genIntMulComplexOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: M
10455	.lea_got,	11423	.lea_got,
10456	.lea_tlv,	11424	.lea_tlv,
10457	.lea_frame,	11425	.lea_frame,
		11426	.elementwise_regs_then_frame,
10458	.reserved_frame,	11427	.reserved_frame,
10459	.air_ref,	11428	.air_ref,
10460	=> unreachable, // unmodifiable destination	11429	=> unreachable, // unmodifiable destination
...	@@ -10474,6 +11443,7 @@ fn genIntMulComplexOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: M	...	@@ -10474,6 +11443,7 @@ fn genIntMulComplexOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: M
10474	.undef,	11443	.undef,
10475	.register_pair,	11444	.register_pair,
10476	.register_overflow,	11445	.register_overflow,
		11446	.elementwise_regs_then_frame,
10477	.reserved_frame,	11447	.reserved_frame,
10478	.air_ref,	11448	.air_ref,
10479	=> unreachable,	11449	=> unreachable,
...	@@ -10557,7 +11527,7 @@ fn genIntMulComplexOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: M	...	@@ -10557,7 +11527,7 @@ fn genIntMulComplexOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: M
10557	defer self.register_manager.unlockReg(tmp_lock);	11527	defer self.register_manager.unlockReg(tmp_lock);
10558		11528
10559	try self.genIntMulComplexOpMir(dst_ty, tmp_mcv, src_mcv);	11529	try self.genIntMulComplexOpMir(dst_ty, tmp_mcv, src_mcv);
10560	try self.genCopy(dst_ty, dst_mcv, tmp_mcv);	11530	try self.genCopy(dst_ty, dst_mcv, tmp_mcv, .{});
10561	},	11531	},
10562	}	11532	}
10563	}	11533	}
...	@@ -10580,7 +11550,93 @@ fn airArg(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -10580,7 +11550,93 @@ fn airArg(self: *Self, inst: Air.Inst.Index) !void {
10580	.indirect => \|reg_off\| dst: {	11550	.indirect => \|reg_off\| dst: {
10581	self.register_manager.getRegAssumeFree(reg_off.reg, inst);	11551	self.register_manager.getRegAssumeFree(reg_off.reg, inst);
10582	const dst_mcv = try self.allocRegOrMem(inst, false);	11552	const dst_mcv = try self.allocRegOrMem(inst, false);
10583	try self.genCopy(arg_ty, dst_mcv, src_mcv);	11553	try self.genCopy(arg_ty, dst_mcv, src_mcv, .{});
		11554	break :dst dst_mcv;
		11555	},
		11556	.elementwise_regs_then_frame => \|regs_frame_addr\| dst: {
		11557	try self.spillEflagsIfOccupied();
		11558
		11559	const fn_info = mod.typeToFunc(self.fn_type).?;
		11560	const cc = abi.resolveCallingConvention(fn_info.cc, self.target.*);
		11561	const param_int_regs = abi.getCAbiIntParamRegs(cc);
		11562	var prev_reg: Register = undefined;
		11563	for (
		11564	param_int_regs[param_int_regs.len - regs_frame_addr.regs ..],
		11565	0..,
		11566	) \|dst_reg, elem_index\| {
		11567	assert(self.register_manager.isRegFree(dst_reg));
		11568	if (elem_index > 0) {
		11569	try self.asmRegisterImmediate(
		11570	.{ ._l, .sh },
		11571	dst_reg.to8(),
		11572	Immediate.u(elem_index),
		11573	);
		11574	try self.asmRegisterRegister(
		11575	.{ ._, .@"or" },
		11576	dst_reg.to8(),
		11577	prev_reg.to8(),
		11578	);
		11579	}
		11580	prev_reg = dst_reg;
		11581	}
		11582
		11583	const prev_lock = if (regs_frame_addr.regs > 0)
		11584	self.register_manager.lockRegAssumeUnused(prev_reg)
		11585	else
		11586	null;
		11587	defer if (prev_lock) \|lock\| self.register_manager.unlockReg(lock);
		11588
		11589	const dst_mcv = try self.allocRegOrMem(inst, false);
		11590	if (regs_frame_addr.regs > 0) try self.asmMemoryRegister(
		11591	.{ ._, .mov },
		11592	try dst_mcv.mem(self, .byte),
		11593	prev_reg.to8(),
		11594	);
		11595	try self.genInlineMemset(
		11596	dst_mcv.address().offset(@intFromBool(regs_frame_addr.regs > 0)),
		11597	.{ .immediate = 0 },
		11598	.{ .immediate = arg_ty.abiSize(mod) - @intFromBool(regs_frame_addr.regs > 0) },
		11599	.{},
		11600	);
		11601
		11602	const index_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
		11603	const index_lock = self.register_manager.lockRegAssumeUnused(index_reg);
		11604	defer self.register_manager.unlockReg(index_lock);
		11605
		11606	try self.asmRegisterImmediate(
		11607	.{ ._, .mov },
		11608	index_reg.to32(),
		11609	Immediate.u(regs_frame_addr.regs),
		11610	);
		11611	const loop: Mir.Inst.Index = @intCast(self.mir_instructions.len);
		11612	try self.asmMemoryImmediate(.{ ._, .cmp }, .{
		11613	.base = .{ .frame = regs_frame_addr.frame_index },
		11614	.mod = .{ .rm = .{
		11615	.size = .byte,
		11616	.index = index_reg.to64(),
		11617	.scale = .@"8",
		11618	.disp = regs_frame_addr.frame_off - @as(u6, regs_frame_addr.regs) * 8,
		11619	} },
		11620	}, Immediate.u(0));
		11621	const unset = try self.asmJccReloc(.e, undefined);
		11622	try self.asmMemoryRegister(
		11623	.{ ._s, .bt },
		11624	try dst_mcv.mem(self, .dword),
		11625	index_reg.to32(),
		11626	);
		11627	self.performReloc(unset);
		11628	if (self.hasFeature(.slow_incdec)) {
		11629	try self.asmRegisterImmediate(.{ ._, .add }, index_reg.to32(), Immediate.u(1));
		11630	} else {
		11631	try self.asmRegister(.{ ._, .inc }, index_reg.to32());
		11632	}
		11633	try self.asmRegisterImmediate(
		11634	.{ ._, .cmp },
		11635	index_reg.to32(),
		11636	Immediate.u(arg_ty.vectorLen(mod)),
		11637	);
		11638	_ = try self.asmJccReloc(.b, loop);
		11639
10584	break :dst dst_mcv;	11640	break :dst dst_mcv;
10585	},	11641	},
10586	else => return self.fail("TODO implement arg for {}", .{src_mcv}),	11642	else => return self.fail("TODO implement arg for {}", .{src_mcv}),
...	@@ -10605,7 +11661,7 @@ fn genArgDbgInfo(self: Self, ty: Type, name: [:0]const u8, mcv: MCValue) !void {	...	@@ -10605,7 +11661,7 @@ fn genArgDbgInfo(self: Self, ty: Type, name: [:0]const u8, mcv: MCValue) !void {
10605	regs[0].dwarfNum(), regs[1].dwarfNum(),	11661	regs[0].dwarfNum(), regs[1].dwarfNum(),
10606	} },	11662	} },
10607	// TODO use a frame index	11663	// TODO use a frame index
10608	.load_frame => return,	11664	.load_frame, .elementwise_regs_then_frame => return,
10609	//.stack_offset => \|off\| .{	11665	//.stack_offset => \|off\| .{
10610	// .stack = .{	11666	// .stack = .{
10611	// // TODO handle -fomit-frame-pointer	11667	// // TODO handle -fomit-frame-pointer
...	@@ -10688,13 +11744,13 @@ fn airBreakpoint(self: *Self) !void {	...	@@ -10688,13 +11744,13 @@ fn airBreakpoint(self: *Self) !void {
10688		11744
10689	fn airRetAddr(self: *Self, inst: Air.Inst.Index) !void {	11745	fn airRetAddr(self: *Self, inst: Air.Inst.Index) !void {
10690	const dst_mcv = try self.allocRegOrMem(inst, true);	11746	const dst_mcv = try self.allocRegOrMem(inst, true);
10691	try self.genCopy(Type.usize, dst_mcv, .{ .load_frame = .{ .index = .ret_addr } });	11747	try self.genCopy(Type.usize, dst_mcv, .{ .load_frame = .{ .index = .ret_addr } }, .{});
10692	return self.finishAir(inst, dst_mcv, .{ .none, .none, .none });	11748	return self.finishAir(inst, dst_mcv, .{ .none, .none, .none });
10693	}	11749	}
10694		11750
10695	fn airFrameAddress(self: *Self, inst: Air.Inst.Index) !void {	11751	fn airFrameAddress(self: *Self, inst: Air.Inst.Index) !void {
10696	const dst_mcv = try self.allocRegOrMem(inst, true);	11752	const dst_mcv = try self.allocRegOrMem(inst, true);
10697	try self.genCopy(Type.usize, dst_mcv, .{ .lea_frame = .{ .index = .base_ptr } });	11753	try self.genCopy(Type.usize, dst_mcv, .{ .lea_frame = .{ .index = .base_ptr } }, .{});
10698	return self.finishAir(inst, dst_mcv, .{ .none, .none, .none });	11754	return self.finishAir(inst, dst_mcv, .{ .none, .none, .none });
10699	}	11755	}
10700		11756
...	@@ -10833,14 +11889,69 @@ fn genCall(self: *Self, info: union(enum) {	...	@@ -10833,14 +11889,69 @@ fn genCall(self: *Self, info: union(enum) {
10833	},	11889	},
10834	.indirect => \|reg_off\| {	11890	.indirect => \|reg_off\| {
10835	frame_index.* = try self.allocFrameIndex(FrameAlloc.initType(arg_ty, mod));	11891	frame_index.* = try self.allocFrameIndex(FrameAlloc.initType(arg_ty, mod));
10836	try self.genSetMem(.{ .frame = frame_index.* }, 0, arg_ty, src_arg);	11892	try self.genSetMem(.{ .frame = frame_index.* }, 0, arg_ty, src_arg, .{});
10837	try self.register_manager.getReg(reg_off.reg, null);	11893	try self.register_manager.getReg(reg_off.reg, null);
10838	try reg_locks.append(self.register_manager.lockReg(reg_off.reg));	11894	try reg_locks.append(self.register_manager.lockReg(reg_off.reg));
10839	},	11895	},
10840	.load_frame => {	11896	.load_frame => {
10841	try self.genCopy(arg_ty, dst_arg, src_arg);	11897	try self.genCopy(arg_ty, dst_arg, src_arg, .{});
10842	try self.freeValue(src_arg);	11898	try self.freeValue(src_arg);
10843	},	11899	},
		11900	.elementwise_regs_then_frame => \|regs_frame_addr\| {
		11901	const index_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
		11902	const index_lock = self.register_manager.lockRegAssumeUnused(index_reg);
		11903	defer self.register_manager.unlockReg(index_lock);
		11904
		11905	const src_mem: Memory = if (src_arg.isMemory()) try src_arg.mem(self, .dword) else .{
		11906	.base = .{ .reg = try self.copyToTmpRegister(
		11907	Type.usize,
		11908	switch (src_arg) {
		11909	else => src_arg,
		11910	.air_ref => \|src_ref\| try self.resolveInst(src_ref),
		11911	}.address(),
		11912	) },
		11913	.mod = .{ .rm = .{ .size = .dword } },
		11914	};
		11915	const src_lock = switch (src_mem.base) {
		11916	.reg => \|src_reg\| self.register_manager.lockReg(src_reg),
		11917	else => null,
		11918	};
		11919	defer if (src_lock) \|lock\| self.register_manager.unlockReg(lock);
		11920
		11921	try self.asmRegisterImmediate(
		11922	.{ ._, .mov },
		11923	index_reg.to32(),
		11924	Immediate.u(regs_frame_addr.regs),
		11925	);
		11926	const loop: Mir.Inst.Index = @intCast(self.mir_instructions.len);
		11927	try self.asmMemoryRegister(.{ ._, .bt }, src_mem, index_reg.to32());
		11928	try self.asmSetccMemory(.c, .{
		11929	.base = .{ .frame = regs_frame_addr.frame_index },
		11930	.mod = .{ .rm = .{
		11931	.size = .byte,
		11932	.index = index_reg.to64(),
		11933	.scale = .@"8",
		11934	.disp = regs_frame_addr.frame_off - @as(u6, regs_frame_addr.regs) * 8,
		11935	} },
		11936	});
		11937	if (self.hasFeature(.slow_incdec)) {
		11938	try self.asmRegisterImmediate(.{ ._, .add }, index_reg.to32(), Immediate.u(1));
		11939	} else {
		11940	try self.asmRegister(.{ ._, .inc }, index_reg.to32());
		11941	}
		11942	try self.asmRegisterImmediate(
		11943	.{ ._, .cmp },
		11944	index_reg.to32(),
		11945	Immediate.u(arg_ty.vectorLen(mod)),
		11946	);
		11947	_ = try self.asmJccReloc(.b, loop);
		11948
		11949	const param_int_regs = abi.getCAbiIntParamRegs(resolved_cc);
		11950	for (param_int_regs[param_int_regs.len - regs_frame_addr.regs ..]) \|dst_reg\| {
		11951	try self.register_manager.getReg(dst_reg, null);
		11952	try reg_locks.append(self.register_manager.lockReg(dst_reg));
		11953	}
		11954	},
10844	else => unreachable,	11955	else => unreachable,
10845	};	11956	};
10846		11957
...	@@ -10852,7 +11963,7 @@ fn genCall(self: *Self, info: union(enum) {	...	@@ -10852,7 +11963,7 @@ fn genCall(self: *Self, info: union(enum) {
10852	const frame_index = try self.allocFrameIndex(FrameAlloc.initSpill(ret_ty, mod));	11963	const frame_index = try self.allocFrameIndex(FrameAlloc.initSpill(ret_ty, mod));
10853	try self.genSetReg(reg_off.reg, Type.usize, .{	11964	try self.genSetReg(reg_off.reg, Type.usize, .{
10854	.lea_frame = .{ .index = frame_index, .off = -reg_off.off },	11965	.lea_frame = .{ .index = frame_index, .off = -reg_off.off },
10855	});	11966	}, .{});
10856	call_info.return_value.short = .{ .load_frame = .{ .index = frame_index } };	11967	call_info.return_value.short = .{ .load_frame = .{ .index = frame_index } };
10857	try reg_locks.append(self.register_manager.lockReg(reg_off.reg));	11968	try reg_locks.append(self.register_manager.lockReg(reg_off.reg));
10858	},	11969	},
...	@@ -10867,20 +11978,52 @@ fn genCall(self: *Self, info: union(enum) {	...	@@ -10867,20 +11978,52 @@ fn genCall(self: *Self, info: union(enum) {
10867	registerAlias(dst_reg, @intCast(arg_ty.abiSize(mod))),	11978	registerAlias(dst_reg, @intCast(arg_ty.abiSize(mod))),
10868	arg_ty,	11979	arg_ty,
10869	src_arg,	11980	src_arg,
		11981	.{},
10870	),	11982	),
10871	.C, .SysV, .Win64 => {	11983	.C, .SysV, .Win64 => {
10872	const promoted_ty = self.promoteInt(arg_ty);	11984	const promoted_ty = self.promoteInt(arg_ty);
10873	const promoted_abi_size: u32 = @intCast(promoted_ty.abiSize(mod));	11985	const promoted_abi_size: u32 = @intCast(promoted_ty.abiSize(mod));
10874	const dst_alias = registerAlias(dst_reg, promoted_abi_size);	11986	const dst_alias = registerAlias(dst_reg, promoted_abi_size);
10875	try self.genSetReg(dst_alias, promoted_ty, src_arg);	11987	try self.genSetReg(dst_alias, promoted_ty, src_arg, .{});
10876	if (promoted_ty.toIntern() != arg_ty.toIntern())	11988	if (promoted_ty.toIntern() != arg_ty.toIntern())
10877	try self.truncateRegister(arg_ty, dst_alias);	11989	try self.truncateRegister(arg_ty, dst_alias);
10878	},	11990	},
10879	},	11991	},
10880	.register_pair => try self.genCopy(arg_ty, dst_arg, src_arg),	11992	.register_pair => try self.genCopy(arg_ty, dst_arg, src_arg, .{}),
10881	.indirect => \|reg_off\| try self.genSetReg(reg_off.reg, Type.usize, .{	11993	.indirect => \|reg_off\| try self.genSetReg(reg_off.reg, Type.usize, .{
10882	.lea_frame = .{ .index = frame_index, .off = -reg_off.off },	11994	.lea_frame = .{ .index = frame_index, .off = -reg_off.off },
10883	}),	11995	}, .{}),
		11996	.elementwise_regs_then_frame => \|regs_frame_addr\| {
		11997	const src_mem: Memory = if (src_arg.isMemory()) try src_arg.mem(self, .dword) else .{
		11998	.base = .{ .reg = try self.copyToTmpRegister(
		11999	Type.usize,
		12000	switch (src_arg) {
		12001	else => src_arg,
		12002	.air_ref => \|src_ref\| try self.resolveInst(src_ref),
		12003	}.address(),
		12004	) },
		12005	.mod = .{ .rm = .{ .size = .dword } },
		12006	};
		12007	const src_lock = switch (src_mem.base) {
		12008	.reg => \|src_reg\| self.register_manager.lockReg(src_reg),
		12009	else => null,
		12010	};
		12011	defer if (src_lock) \|lock\| self.register_manager.unlockReg(lock);
		12012
		12013	const param_int_regs = abi.getCAbiIntParamRegs(resolved_cc);
		12014	for (
		12015	param_int_regs[param_int_regs.len - regs_frame_addr.regs ..],
		12016	0..,
		12017	) \|dst_reg, elem_index\| {
		12018	try self.asmRegisterRegister(.{ ._, .xor }, dst_reg.to32(), dst_reg.to32());
		12019	try self.asmMemoryImmediate(
		12020	.{ ._, .bt },
		12021	src_mem,
		12022	Immediate.u(elem_index),
		12023	);
		12024	try self.asmSetccRegister(.c, dst_reg.to8());
		12025	}
		12026	},
10884	else => unreachable,	12027	else => unreachable,
10885	};	12028	};
10886		12029
...	@@ -10921,6 +12064,7 @@ fn genCall(self: *Self, info: union(enum) {	...	@@ -10921,6 +12064,7 @@ fn genCall(self: *Self, info: union(enum) {
10921	callee_reg,	12064	callee_reg,
10922	Type.usize,	12065	Type.usize,
10923	.{ .load_symbol = .{ .sym = sym.esym_index } },	12066	.{ .load_symbol = .{ .sym = sym.esym_index } },
		12067	.{},
10924	);	12068	);
10925	try self.asmRegister(.{ ._, .call }, callee_reg);	12069	try self.asmRegister(.{ ._, .call }, callee_reg);
10926	} else try self.asmMemory(.{ ._, .call }, .{	12070	} else try self.asmMemory(.{ ._, .call }, .{
...	@@ -10933,12 +12077,17 @@ fn genCall(self: *Self, info: union(enum) {	...	@@ -10933,12 +12077,17 @@ fn genCall(self: *Self, info: union(enum) {
10933	} else if (self.bin_file.cast(link.File.Coff)) \|coff_file\| {	12077	} else if (self.bin_file.cast(link.File.Coff)) \|coff_file\| {
10934	const atom = try coff_file.getOrCreateAtomForDecl(func.owner_decl);	12078	const atom = try coff_file.getOrCreateAtomForDecl(func.owner_decl);
10935	const sym_index = coff_file.getAtom(atom).getSymbolIndex().?;	12079	const sym_index = coff_file.getAtom(atom).getSymbolIndex().?;
10936	try self.genSetReg(.rax, Type.usize, .{ .lea_got = sym_index });	12080	try self.genSetReg(.rax, Type.usize, .{ .lea_got = sym_index }, .{});
10937	try self.asmRegister(.{ ._, .call }, .rax);	12081	try self.asmRegister(.{ ._, .call }, .rax);
10938	} else if (self.bin_file.cast(link.File.MachO)) \|macho_file\| {	12082	} else if (self.bin_file.cast(link.File.MachO)) \|macho_file\| {
10939	const sym_index = try macho_file.getZigObject().?.getOrCreateMetadataForDecl(macho_file, func.owner_decl);	12083	const sym_index = try macho_file.getZigObject().?.getOrCreateMetadataForDecl(macho_file, func.owner_decl);
10940	const sym = macho_file.getSymbol(sym_index);	12084	const sym = macho_file.getSymbol(sym_index);
10941	try self.genSetReg(.rax, Type.usize, .{ .load_symbol = .{ .sym = sym.nlist_idx } });	12085	try self.genSetReg(
		12086	.rax,
		12087	Type.usize,
		12088	.{ .load_symbol = .{ .sym = sym.nlist_idx } },
		12089	.{},
		12090	);
10942	try self.asmRegister(.{ ._, .call }, .rax);	12091	try self.asmRegister(.{ ._, .call }, .rax);
10943	} else if (self.bin_file.cast(link.File.Plan9)) \|p9\| {	12092	} else if (self.bin_file.cast(link.File.Plan9)) \|p9\| {
10944	const atom_index = try p9.seeDecl(func.owner_decl);	12093	const atom_index = try p9.seeDecl(func.owner_decl);
...	@@ -10963,7 +12112,7 @@ fn genCall(self: *Self, info: union(enum) {	...	@@ -10963,7 +12112,7 @@ fn genCall(self: *Self, info: union(enum) {
10963	}	12112	}
10964	} else {	12113	} else {
10965	assert(self.typeOf(callee).zigTypeTag(mod) == .Pointer);	12114	assert(self.typeOf(callee).zigTypeTag(mod) == .Pointer);
10966	try self.genSetReg(.rax, Type.usize, .{ .air_ref = callee });	12115	try self.genSetReg(.rax, Type.usize, .{ .air_ref = callee }, .{});
10967	try self.asmRegister(.{ ._, .call }, .rax);	12116	try self.asmRegister(.{ ._, .call }, .rax);
10968	},	12117	},
10969	.lib => \|lib\| try self.genExternSymbolRef(.call, lib.lib, lib.callee),	12118	.lib => \|lib\| try self.genExternSymbolRef(.call, lib.lib, lib.callee),
...	@@ -10971,7 +12120,7 @@ fn genCall(self: *Self, info: union(enum) {	...	@@ -10971,7 +12120,7 @@ fn genCall(self: *Self, info: union(enum) {
10971	return call_info.return_value.short;	12120	return call_info.return_value.short;
10972	}	12121	}
10973		12122
10974	fn airRet(self: *Self, inst: Air.Inst.Index) !void {	12123	fn airRet(self: *Self, inst: Air.Inst.Index, safety: bool) !void {
10975	const mod = self.bin_file.comp.module.?;	12124	const mod = self.bin_file.comp.module.?;
10976	const un_op = self.air.instructions.items(.data)[@intFromEnum(inst)].un_op;	12125	const un_op = self.air.instructions.items(.data)[@intFromEnum(inst)].un_op;
10977		12126
...	@@ -10980,14 +12129,20 @@ fn airRet(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -10980,14 +12129,20 @@ fn airRet(self: *Self, inst: Air.Inst.Index) !void {
10980	.none => {},	12129	.none => {},
10981	.register,	12130	.register,
10982	.register_pair,	12131	.register_pair,
10983	=> try self.genCopy(ret_ty, self.ret_mcv.short, .{ .air_ref = un_op }),	12132	=> try self.genCopy(ret_ty, self.ret_mcv.short, .{ .air_ref = un_op }, .{ .safety = safety }),
10984	.indirect => \|reg_off\| {	12133	.indirect => \|reg_off\| {
10985	try self.register_manager.getReg(reg_off.reg, null);	12134	try self.register_manager.getReg(reg_off.reg, null);
10986	const lock = self.register_manager.lockRegAssumeUnused(reg_off.reg);	12135	const lock = self.register_manager.lockRegAssumeUnused(reg_off.reg);
10987	defer self.register_manager.unlockReg(lock);	12136	defer self.register_manager.unlockReg(lock);
10988		12137
10989	try self.genSetReg(reg_off.reg, Type.usize, self.ret_mcv.long);	12138	try self.genSetReg(reg_off.reg, Type.usize, self.ret_mcv.long, .{});
10990	try self.genSetMem(.{ .reg = reg_off.reg }, reg_off.off, ret_ty, .{ .air_ref = un_op });	12139	try self.genSetMem(
		12140	.{ .reg = reg_off.reg },
		12141	reg_off.off,
		12142	ret_ty,
		12143	.{ .air_ref = un_op },
		12144	.{ .safety = safety },
		12145	);
10991	},	12146	},
10992	else => unreachable,	12147	else => unreachable,
10993	}	12148	}
...	@@ -11008,7 +12163,7 @@ fn airRetLoad(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -11008,7 +12163,7 @@ fn airRetLoad(self: *Self, inst: Air.Inst.Index) !void {
11008	switch (self.ret_mcv.short) {	12163	switch (self.ret_mcv.short) {
11009	.none => {},	12164	.none => {},
11010	.register, .register_pair => try self.load(self.ret_mcv.short, ptr_ty, ptr),	12165	.register, .register_pair => try self.load(self.ret_mcv.short, ptr_ty, ptr),
11011	.indirect => \|reg_off\| try self.genSetReg(reg_off.reg, ptr_ty, ptr),	12166	.indirect => \|reg_off\| try self.genSetReg(reg_off.reg, ptr_ty, ptr, .{}),
11012	else => unreachable,	12167	else => unreachable,
11013	}	12168	}
11014	self.ret_mcv.liveOut(self, inst);	12169	self.ret_mcv.liveOut(self, inst);
...	@@ -11113,7 +12268,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {	...	@@ -11113,7 +12268,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
11113	const dst_mcv = if (unmat_dst_mcv.isRegister() or	12268	const dst_mcv = if (unmat_dst_mcv.isRegister() or
11114	(abi_size <= 8 and unmat_dst_mcv.isMemory())) unmat_dst_mcv else dst: {	12269	(abi_size <= 8 and unmat_dst_mcv.isMemory())) unmat_dst_mcv else dst: {
11115	const dst_mcv = try self.allocTempRegOrMem(ty, true);	12270	const dst_mcv = try self.allocTempRegOrMem(ty, true);
11116	try self.genCopy(ty, dst_mcv, unmat_dst_mcv);	12271	try self.genCopy(ty, dst_mcv, unmat_dst_mcv, .{});
11117	break :dst dst_mcv;	12272	break :dst dst_mcv;
11118	};	12273	};
11119	const dst_lock =	12274	const dst_lock =
...	@@ -11155,6 +12310,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {	...	@@ -11155,6 +12310,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
11155	.lea_tlv,	12310	.lea_tlv,
11156	.lea_frame,	12311	.lea_frame,
11157	.lea_symbol,	12312	.lea_symbol,
		12313	.elementwise_regs_then_frame,
11158	.reserved_frame,	12314	.reserved_frame,
11159	.air_ref,	12315	.air_ref,
11160	=> unreachable,	12316	=> unreachable,
...	@@ -11184,6 +12340,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {	...	@@ -11184,6 +12340,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
11184	dst_addr_reg,	12340	dst_addr_reg,
11185	Type.usize,	12341	Type.usize,
11186	resolved_dst_mcv.address(),	12342	resolved_dst_mcv.address(),
		12343	.{},
11187	);	12344	);
11188	break :dst .{	12345	break :dst .{
11189	.addr_reg = dst_addr_reg,	12346	.addr_reg = dst_addr_reg,
...	@@ -11214,6 +12371,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {	...	@@ -11214,6 +12371,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
11214	.lea_got,	12371	.lea_got,
11215	.lea_tlv,	12372	.lea_tlv,
11216	.lea_frame,	12373	.lea_frame,
		12374	.elementwise_regs_then_frame,
11217	.reserved_frame,	12375	.reserved_frame,
11218	.air_ref,	12376	.air_ref,
11219	=> unreachable,	12377	=> unreachable,
...	@@ -11243,6 +12401,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {	...	@@ -11243,6 +12401,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
11243	src_addr_reg,	12401	src_addr_reg,
11244	Type.usize,	12402	Type.usize,
11245	resolved_src_mcv.address(),	12403	resolved_src_mcv.address(),
		12404	.{},
11246	);	12405	);
11247	break :src .{	12406	break :src .{
11248	.addr_reg = src_addr_reg,	12407	.addr_reg = src_addr_reg,
...	@@ -11255,7 +12414,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {	...	@@ -11255,7 +12414,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
11255		12414
11256	const regs = try self.register_manager.allocRegs(	12415	const regs = try self.register_manager.allocRegs(
11257	2,	12416	2,
11258	.{ null, null },	12417	.{null} ** 2,
11259	abi.RegisterClass.gp,	12418	abi.RegisterClass.gp,
11260	);	12419	);
11261	const acc_reg = regs[0].to64();	12420	const acc_reg = regs[0].to64();
...	@@ -11284,7 +12443,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {	...	@@ -11284,7 +12443,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
11284	.off = frame_addr.off + off,	12443	.off = frame_addr.off + off,
11285	} },	12444	} },
11286	else => unreachable,	12445	else => unreachable,
11287	});	12446	}, .{});
11288		12447
11289	try self.genBinOpMir(	12448	try self.genBinOpMir(
11290	.{ ._, .xor },	12449	.{ ._, .xor },
...	@@ -11497,7 +12656,7 @@ fn genTry(	...	@@ -11497,7 +12656,7 @@ fn genTry(
11497	.close_scope = true,	12656	.close_scope = true,
11498	});	12657	});
11499		12658
11500	try self.performReloc(reloc);	12659	self.performReloc(reloc);
11501		12660
11502	for (liveness_cond_br.then_deaths) \|death\| try self.processDeath(death);	12661	for (liveness_cond_br.then_deaths) \|death\| try self.processDeath(death);
11503		12662
...	@@ -11611,7 +12770,7 @@ fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -11611,7 +12770,7 @@ fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {
11611	.close_scope = true,	12770	.close_scope = true,
11612	});	12771	});
11613		12772
11614	try self.performReloc(reloc);	12773	self.performReloc(reloc);
11615		12774
11616	for (liveness_cond_br.else_deaths) \|death\| try self.processDeath(death);	12775	for (liveness_cond_br.else_deaths) \|death\| try self.processDeath(death);
11617	try self.genBody(else_body);	12776	try self.genBody(else_body);
...	@@ -11658,6 +12817,7 @@ fn isNull(self: *Self, inst: Air.Inst.Index, opt_ty: Type, opt_mcv: MCValue) !MC	...	@@ -11658,6 +12817,7 @@ fn isNull(self: *Self, inst: Air.Inst.Index, opt_ty: Type, opt_mcv: MCValue) !MC
11658	.lea_tlv,	12817	.lea_tlv,
11659	.lea_frame,	12818	.lea_frame,
11660	.lea_symbol,	12819	.lea_symbol,
		12820	.elementwise_regs_then_frame,
11661	.reserved_frame,	12821	.reserved_frame,
11662	.air_ref,	12822	.air_ref,
11663	=> unreachable,	12823	=> unreachable,
...	@@ -11690,7 +12850,7 @@ fn isNull(self: *Self, inst: Air.Inst.Index, opt_ty: Type, opt_mcv: MCValue) !MC	...	@@ -11690,7 +12850,7 @@ fn isNull(self: *Self, inst: Air.Inst.Index, opt_ty: Type, opt_mcv: MCValue) !MC
11690	const addr_reg_lock = self.register_manager.lockRegAssumeUnused(addr_reg);	12850	const addr_reg_lock = self.register_manager.lockRegAssumeUnused(addr_reg);
11691	defer self.register_manager.unlockReg(addr_reg_lock);	12851	defer self.register_manager.unlockReg(addr_reg_lock);
11692		12852
11693	try self.genSetReg(addr_reg, Type.usize, opt_mcv.address());	12853	try self.genSetReg(addr_reg, Type.usize, opt_mcv.address(), .{});
11694	const some_abi_size: u32 = @intCast(some_info.ty.abiSize(mod));	12854	const some_abi_size: u32 = @intCast(some_info.ty.abiSize(mod));
11695	try self.asmMemoryImmediate(	12855	try self.asmMemoryImmediate(
11696	.{ ._, .cmp },	12856	.{ ._, .cmp },
...	@@ -11789,6 +12949,7 @@ fn isErr(self: *Self, maybe_inst: ?Air.Inst.Index, eu_ty: Type, eu_mcv: MCValue)	...	@@ -11789,6 +12949,7 @@ fn isErr(self: *Self, maybe_inst: ?Air.Inst.Index, eu_ty: Type, eu_mcv: MCValue)
11789	.{ ._r, .sh },	12949	.{ ._r, .sh },
11790	eu_ty,	12950	eu_ty,
11791	.{ .register = tmp_reg },	12951	.{ .register = tmp_reg },
		12952	Type.u8,
11792	.{ .immediate = @as(u6, @intCast(err_off * 8)) },	12953	.{ .immediate = @as(u6, @intCast(err_off * 8)) },
11793	);	12954	);
11794	} else {	12955	} else {
...	@@ -11994,7 +13155,7 @@ fn airBlock(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -11994,7 +13155,7 @@ fn airBlock(self: *Self, inst: Air.Inst.Index) !void {
11994	.resurrect = true,	13155	.resurrect = true,
11995	.close_scope = true,	13156	.close_scope = true,
11996	});	13157	});
11997	for (block_data.value.relocs.items) \|reloc\| try self.performReloc(reloc);	13158	for (block_data.value.relocs.items) \|reloc\| self.performReloc(reloc);
11998	}	13159	}
11999		13160
12000	if (std.debug.runtime_safety) assert(self.inst_tracking.getIndex(inst).? == inst_tracking_i);	13161	if (std.debug.runtime_safety) assert(self.inst_tracking.getIndex(inst).? == inst_tracking_i);
...	@@ -12054,7 +13215,7 @@ fn airSwitchBr(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -12054,7 +13215,7 @@ fn airSwitchBr(self: *Self, inst: Air.Inst.Index) !void {
12054		13215
12055	for (liveness.deaths[case_i]) \|operand\| try self.processDeath(operand);	13216	for (liveness.deaths[case_i]) \|operand\| try self.processDeath(operand);
12056		13217
12057	for (relocs[0 .. relocs.len - 1]) \|reloc\| try self.performReloc(reloc);	13218	for (relocs[0 .. relocs.len - 1]) \|reloc\| self.performReloc(reloc);
12058	try self.genBody(case_body);	13219	try self.genBody(case_body);
12059	try self.restoreState(state, &.{}, .{	13220	try self.restoreState(state, &.{}, .{
12060	.emit_instructions = false,	13221	.emit_instructions = false,
...	@@ -12063,7 +13224,7 @@ fn airSwitchBr(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -12063,7 +13224,7 @@ fn airSwitchBr(self: *Self, inst: Air.Inst.Index) !void {
12063	.close_scope = true,	13224	.close_scope = true,
12064	});	13225	});
12065		13226
12066	try self.performReloc(relocs[relocs.len - 1]);	13227	self.performReloc(relocs[relocs.len - 1]);
12067	}	13228	}
12068		13229
12069	if (switch_br.data.else_body_len > 0) {	13230	if (switch_br.data.else_body_len > 0) {
...	@@ -12086,7 +13247,7 @@ fn airSwitchBr(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -12086,7 +13247,7 @@ fn airSwitchBr(self: *Self, inst: Air.Inst.Index) !void {
12086	self.finishAirBookkeeping();	13247	self.finishAirBookkeeping();
12087	}	13248	}
12088		13249
12089	fn performReloc(self: *Self, reloc: Mir.Inst.Index) !void {	13250	fn performReloc(self: *Self, reloc: Mir.Inst.Index) void {
12090	const next_inst: u32 = @intCast(self.mir_instructions.len);	13251	const next_inst: u32 = @intCast(self.mir_instructions.len);
12091	switch (self.mir_instructions.items(.tag)[reloc]) {	13252	switch (self.mir_instructions.items(.tag)[reloc]) {
12092	.j, .jmp => {},	13253	.j, .jmp => {},
...	@@ -12130,7 +13291,7 @@ fn airBr(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -12130,7 +13291,7 @@ fn airBr(self: *Self, inst: Air.Inst.Index) !void {
12130	try self.getValue(block_tracking.short, br.block_inst);	13291	try self.getValue(block_tracking.short, br.block_inst);
12131	break :dst block_tracking.short;	13292	break :dst block_tracking.short;
12132	};	13293	};
12133	try self.genCopy(block_ty, dst_mcv, try self.resolveInst(br.operand));	13294	try self.genCopy(block_ty, dst_mcv, try self.resolveInst(br.operand), .{});
12134	break :result dst_mcv;	13295	break :result dst_mcv;
12135	};	13296	};
12136		13297
...	@@ -12294,7 +13455,7 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -12294,7 +13455,7 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
12294	rc.isSet(RegisterManager.indexOfRegIntoTracked(input_mcv.getReg().?).?))	13455	rc.isSet(RegisterManager.indexOfRegIntoTracked(input_mcv.getReg().?).?))
12295	break :arg input_mcv;	13456	break :arg input_mcv;
12296	const reg = try self.register_manager.allocReg(null, rc);	13457	const reg = try self.register_manager.allocReg(null, rc);
12297	try self.genSetReg(reg, ty, input_mcv);	13458	try self.genSetReg(reg, ty, input_mcv, .{});
12298	break :arg .{ .register = registerAlias(reg, @intCast(ty.abiSize(mod))) };	13459	break :arg .{ .register = registerAlias(reg, @intCast(ty.abiSize(mod))) };
12299	} else if (mem.eql(u8, constraint, "i") or mem.eql(u8, constraint, "n"))	13460	} else if (mem.eql(u8, constraint, "i") or mem.eql(u8, constraint, "n"))
12300	switch (input_mcv) {	13461	switch (input_mcv) {
...	@@ -12311,16 +13472,16 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -12311,16 +13472,16 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
12311	.load_symbol, .load_direct, .load_got, .load_tlv => {},	13472	.load_symbol, .load_direct, .load_got, .load_tlv => {},
12312	else => {	13473	else => {
12313	const temp_mcv = try self.allocTempRegOrMem(ty, false);	13474	const temp_mcv = try self.allocTempRegOrMem(ty, false);
12314	try self.genCopy(ty, temp_mcv, input_mcv);	13475	try self.genCopy(ty, temp_mcv, input_mcv, .{});
12315	break :arg temp_mcv;	13476	break :arg temp_mcv;
12316	},	13477	},
12317	}	13478	}
12318	const addr_reg = self.register_manager.tryAllocReg(null, abi.RegisterClass.gp) orelse {	13479	const addr_reg = self.register_manager.tryAllocReg(null, abi.RegisterClass.gp) orelse {
12319	const temp_mcv = try self.allocTempRegOrMem(ty, false);	13480	const temp_mcv = try self.allocTempRegOrMem(ty, false);
12320	try self.genCopy(ty, temp_mcv, input_mcv);	13481	try self.genCopy(ty, temp_mcv, input_mcv, .{});
12321	break :arg temp_mcv;	13482	break :arg temp_mcv;
12322	};	13483	};
12323	try self.genSetReg(addr_reg, Type.usize, input_mcv.address());	13484	try self.genSetReg(addr_reg, Type.usize, input_mcv.address(), .{});
12324	break :arg .{ .indirect = .{ .reg = addr_reg } };	13485	break :arg .{ .indirect = .{ .reg = addr_reg } };
12325	} else if (mem.eql(u8, constraint, "g") or	13486	} else if (mem.eql(u8, constraint, "g") or
12326	mem.eql(u8, constraint, "rm") or mem.eql(u8, constraint, "mr") or	13487	mem.eql(u8, constraint, "rm") or mem.eql(u8, constraint, "mr") or
...	@@ -12333,7 +13494,7 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -12333,7 +13494,7 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
12333	else => {},	13494	else => {},
12334	}	13495	}
12335	const temp_mcv = try self.allocTempRegOrMem(ty, true);	13496	const temp_mcv = try self.allocTempRegOrMem(ty, true);
12336	try self.genCopy(ty, temp_mcv, input_mcv);	13497	try self.genCopy(ty, temp_mcv, input_mcv, .{});
12337	break :arg temp_mcv;	13498	break :arg temp_mcv;
12338	} else if (mem.eql(u8, constraint, "X"))	13499	} else if (mem.eql(u8, constraint, "X"))
12339	input_mcv	13500	input_mcv
...	@@ -12341,7 +13502,7 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -12341,7 +13502,7 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
12341	const reg = parseRegName(constraint["{".len .. constraint.len - "}".len]) orelse	13502	const reg = parseRegName(constraint["{".len .. constraint.len - "}".len]) orelse
12342	return self.fail("invalid register constraint: '{s}'", .{constraint});	13503	return self.fail("invalid register constraint: '{s}'", .{constraint});
12343	try self.register_manager.getReg(reg, null);	13504	try self.register_manager.getReg(reg, null);
12344	try self.genSetReg(reg, ty, input_mcv);	13505	try self.genSetReg(reg, ty, input_mcv, .{});
12345	break :arg .{ .register = reg };	13506	break :arg .{ .register = reg };
12346	} else if (constraint.len == 1 and std.ascii.isDigit(constraint[0])) arg: {	13507	} else if (constraint.len == 1 and std.ascii.isDigit(constraint[0])) arg: {
12347	const index = std.fmt.charToDigit(constraint[0], 10) catch unreachable;	13508	const index = std.fmt.charToDigit(constraint[0], 10) catch unreachable;
...	@@ -12435,7 +13596,7 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -12435,7 +13596,7 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
12435	if (!anon and label_gop.value_ptr.pending_relocs.items.len == 0)	13596	if (!anon and label_gop.value_ptr.pending_relocs.items.len == 0)
12436	return self.fail("redefined label: '{s}'", .{label_name});	13597	return self.fail("redefined label: '{s}'", .{label_name});
12437	for (label_gop.value_ptr.pending_relocs.items) \|pending_reloc\|	13598	for (label_gop.value_ptr.pending_relocs.items) \|pending_reloc\|
12438	try self.performReloc(pending_reloc);	13599	self.performReloc(pending_reloc);
12439	if (anon)	13600	if (anon)
12440	label_gop.value_ptr.pending_relocs.clearRetainingCapacity()	13601	label_gop.value_ptr.pending_relocs.clearRetainingCapacity()
12441	else	13602	else
...	@@ -12795,7 +13956,7 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -12795,7 +13956,7 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
12795	if (output == .none) continue;	13956	if (output == .none) continue;
12796	if (arg_mcv != .register) continue;	13957	if (arg_mcv != .register) continue;
12797	if (constraint.len == 2 and std.ascii.isDigit(constraint[1])) continue;	13958	if (constraint.len == 2 and std.ascii.isDigit(constraint[1])) continue;
12798	try self.store(self.typeOf(output), .{ .air_ref = output }, arg_mcv);	13959	try self.store(self.typeOf(output), .{ .air_ref = output }, arg_mcv, .{});
12799	}	13960	}
12800		13961
12801	simple: {	13962	simple: {
...	@@ -12952,7 +14113,13 @@ fn moveStrategy(self: *Self, ty: Type, class: Register.Class, aligned: bool) !Mo	...	@@ -12952,7 +14113,13 @@ fn moveStrategy(self: *Self, ty: Type, class: Register.Class, aligned: bool) !Mo
12952	else => {},	14113	else => {},
12953	},	14114	},
12954	.Vector => switch (ty.childType(mod).zigTypeTag(mod)) {	14115	.Vector => switch (ty.childType(mod).zigTypeTag(mod)) {
12955	.Bool => {},	14116	.Bool => switch (ty.vectorLen(mod)) {
		14117	33...64 => return .{ .move = if (self.hasFeature(.avx))
		14118	.{ .v_q, .mov }
		14119	else
		14120	.{ ._q, .mov } },
		14121	else => {},
		14122	},
12956	.Int => switch (ty.childType(mod).intInfo(mod).bits) {	14123	.Int => switch (ty.childType(mod).intInfo(mod).bits) {
12957	8 => switch (ty.vectorLen(mod)) {	14124	8 => switch (ty.vectorLen(mod)) {
12958	1 => if (self.hasFeature(.avx)) return .{ .vex_insert_extract = .{	14125	1 => if (self.hasFeature(.avx)) return .{ .vex_insert_extract = .{
...	@@ -13167,7 +14334,11 @@ fn moveStrategy(self: *Self, ty: Type, class: Register.Class, aligned: bool) !Mo	...	@@ -13167,7 +14334,11 @@ fn moveStrategy(self: *Self, ty: Type, class: Register.Class, aligned: bool) !Mo
13167	return self.fail("TODO moveStrategy for {}", .{ty.fmt(mod)});	14334	return self.fail("TODO moveStrategy for {}", .{ty.fmt(mod)});
13168	}	14335	}
13169		14336
13170	fn genCopy(self: *Self, ty: Type, dst_mcv: MCValue, src_mcv: MCValue) InnerError!void {	14337	const CopyOptions = struct {
		14338	safety: bool = false,
		14339	};
		14340
		14341	fn genCopy(self: *Self, ty: Type, dst_mcv: MCValue, src_mcv: MCValue, opts: CopyOptions) InnerError!void {
13171	const mod = self.bin_file.comp.module.?;	14342	const mod = self.bin_file.comp.module.?;
13172		14343
13173	const src_lock = if (src_mcv.getReg()) \|reg\| self.register_manager.lockReg(reg) else null;	14344	const src_lock = if (src_mcv.getReg()) \|reg\| self.register_manager.lockReg(reg) else null;
...	@@ -13186,16 +14357,18 @@ fn genCopy(self: *Self, ty: Type, dst_mcv: MCValue, src_mcv: MCValue) InnerError	...	@@ -13186,16 +14357,18 @@ fn genCopy(self: *Self, ty: Type, dst_mcv: MCValue, src_mcv: MCValue) InnerError
13186	.lea_tlv,	14357	.lea_tlv,
13187	.lea_frame,	14358	.lea_frame,
13188	.lea_symbol,	14359	.lea_symbol,
		14360	.elementwise_regs_then_frame,
13189	.reserved_frame,	14361	.reserved_frame,
13190	.air_ref,	14362	.air_ref,
13191	=> unreachable, // unmodifiable destination	14363	=> unreachable, // unmodifiable destination
13192	.register => \|reg\| try self.genSetReg(reg, ty, src_mcv),	14364	.register => \|reg\| try self.genSetReg(reg, ty, src_mcv, opts),
13193	.register_offset => \|dst_reg_off\| try self.genSetReg(dst_reg_off.reg, ty, switch (src_mcv) {	14365	.register_offset => \|dst_reg_off\| try self.genSetReg(dst_reg_off.reg, ty, switch (src_mcv) {
13194	.none,	14366	.none,
13195	.unreach,	14367	.unreach,
13196	.dead,	14368	.dead,
13197	.undef,	14369	.undef,
13198	.register_overflow,	14370	.register_overflow,
		14371	.elementwise_regs_then_frame,
13199	.reserved_frame,	14372	.reserved_frame,
13200	=> unreachable,	14373	=> unreachable,
13201	.immediate,	14374	.immediate,
...	@@ -13207,7 +14380,7 @@ fn genCopy(self: *Self, ty: Type, dst_mcv: MCValue, src_mcv: MCValue) InnerError	...	@@ -13207,7 +14380,7 @@ fn genCopy(self: *Self, ty: Type, dst_mcv: MCValue, src_mcv: MCValue) InnerError
13207	.reg = try self.copyToTmpRegister(ty, src_mcv),	14380	.reg = try self.copyToTmpRegister(ty, src_mcv),
13208	.off = -dst_reg_off.off,	14381	.off = -dst_reg_off.off,
13209	} },	14382	} },
13210	}),	14383	}, opts),
13211	.register_pair => \|dst_regs\| {	14384	.register_pair => \|dst_regs\| {
13212	const src_info: ?struct { addr_reg: Register, addr_lock: RegisterLock } = switch (src_mcv) {	14385	const src_info: ?struct { addr_reg: Register, addr_lock: RegisterLock } = switch (src_mcv) {
13213	.register_pair, .memory, .indirect, .load_frame => null,	14386	.register_pair, .memory, .indirect, .load_frame => null,
...	@@ -13217,10 +14390,15 @@ fn genCopy(self: *Self, ty: Type, dst_mcv: MCValue, src_mcv: MCValue) InnerError	...	@@ -13217,10 +14390,15 @@ fn genCopy(self: *Self, ty: Type, dst_mcv: MCValue, src_mcv: MCValue) InnerError
13217	const src_addr_lock = self.register_manager.lockRegAssumeUnused(src_addr_reg);	14390	const src_addr_lock = self.register_manager.lockRegAssumeUnused(src_addr_reg);
13218	errdefer self.register_manager.unlockReg(src_addr_lock);	14391	errdefer self.register_manager.unlockReg(src_addr_lock);
13219		14392
13220	try self.genSetReg(src_addr_reg, Type.usize, src_mcv.address());	14393	try self.genSetReg(src_addr_reg, Type.usize, src_mcv.address(), opts);
13221	break :src .{ .addr_reg = src_addr_reg, .addr_lock = src_addr_lock };	14394	break :src .{ .addr_reg = src_addr_reg, .addr_lock = src_addr_lock };
13222	},	14395	},
13223	.air_ref => \|src_ref\| return self.genCopy(ty, dst_mcv, try self.resolveInst(src_ref)),	14396	.air_ref => \|src_ref\| return self.genCopy(
		14397	ty,
		14398	dst_mcv,
		14399	try self.resolveInst(src_ref),
		14400	opts,
		14401	),
13224	else => return self.fail("TODO implement genCopy for {s} of {}", .{	14402	else => return self.fail("TODO implement genCopy for {s} of {}", .{
13225	@tagName(src_mcv), ty.fmt(mod),	14403	@tagName(src_mcv), ty.fmt(mod),
13226	}),	14404	}),
...	@@ -13237,15 +14415,21 @@ fn genCopy(self: *Self, ty: Type, dst_mcv: MCValue, src_mcv: MCValue) InnerError	...	@@ -13237,15 +14415,21 @@ fn genCopy(self: *Self, ty: Type, dst_mcv: MCValue, src_mcv: MCValue) InnerError
13237	.off = part_disp,	14415	.off = part_disp,
13238	} },	14416	} },
13239	else => unreachable,	14417	else => unreachable,
13240	});	14418	}, opts);
13241	part_disp += @intCast(dst_ty.abiSize(mod));	14419	part_disp += @intCast(dst_ty.abiSize(mod));
13242	}	14420	}
13243	},	14421	},
13244	.indirect => \|reg_off\| try self.genSetMem(.{ .reg = reg_off.reg }, reg_off.off, ty, src_mcv),	14422	.indirect => \|reg_off\| try self.genSetMem(
		14423	.{ .reg = reg_off.reg },
		14424	reg_off.off,
		14425	ty,
		14426	src_mcv,
		14427	opts,
		14428	),
13245	.memory, .load_symbol, .load_direct, .load_got, .load_tlv => {	14429	.memory, .load_symbol, .load_direct, .load_got, .load_tlv => {
13246	switch (dst_mcv) {	14430	switch (dst_mcv) {
13247	.memory => \|addr\| if (math.cast(i32, @as(i64, @bitCast(addr)))) \|small_addr\|	14431	.memory => \|addr\| if (math.cast(i32, @as(i64, @bitCast(addr)))) \|small_addr\|
13248	return self.genSetMem(.{ .reg = .ds }, small_addr, ty, src_mcv),	14432	return self.genSetMem(.{ .reg = .ds }, small_addr, ty, src_mcv, opts),
13249	.load_symbol, .load_direct, .load_got, .load_tlv => {},	14433	.load_symbol, .load_direct, .load_got, .load_tlv => {},
13250	else => unreachable,	14434	else => unreachable,
13251	}	14435	}
...	@@ -13254,18 +14438,25 @@ fn genCopy(self: *Self, ty: Type, dst_mcv: MCValue, src_mcv: MCValue) InnerError	...	@@ -13254,18 +14438,25 @@ fn genCopy(self: *Self, ty: Type, dst_mcv: MCValue, src_mcv: MCValue) InnerError
13254	const addr_lock = self.register_manager.lockRegAssumeUnused(addr_reg);	14438	const addr_lock = self.register_manager.lockRegAssumeUnused(addr_reg);
13255	defer self.register_manager.unlockReg(addr_lock);	14439	defer self.register_manager.unlockReg(addr_lock);
13256		14440
13257	try self.genSetMem(.{ .reg = addr_reg }, 0, ty, src_mcv);	14441	try self.genSetMem(.{ .reg = addr_reg }, 0, ty, src_mcv, opts);
13258	},	14442	},
13259	.load_frame => \|frame_addr\| try self.genSetMem(	14443	.load_frame => \|frame_addr\| try self.genSetMem(
13260	.{ .frame = frame_addr.index },	14444	.{ .frame = frame_addr.index },
13261	frame_addr.off,	14445	frame_addr.off,
13262	ty,	14446	ty,
13263	src_mcv,	14447	src_mcv,
		14448	opts,
13264	),	14449	),
13265	}	14450	}
13266	}	14451	}
13267		14452
13268	fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerError!void {	14453	fn genSetReg(
		14454	self: *Self,
		14455	dst_reg: Register,
		14456	ty: Type,
		14457	src_mcv: MCValue,
		14458	opts: CopyOptions,
		14459	) InnerError!void {
13269	const mod = self.bin_file.comp.module.?;	14460	const mod = self.bin_file.comp.module.?;
13270	const abi_size: u32 = @intCast(ty.abiSize(mod));	14461	const abi_size: u32 = @intCast(ty.abiSize(mod));
13271	if (ty.bitSize(mod) > dst_reg.bitSize())	14462	if (ty.bitSize(mod) > dst_reg.bitSize())
...	@@ -13275,9 +14466,30 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr	...	@@ -13275,9 +14466,30 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
13275	.unreach,	14466	.unreach,
13276	.dead,	14467	.dead,
13277	.register_overflow,	14468	.register_overflow,
		14469	.elementwise_regs_then_frame,
13278	.reserved_frame,	14470	.reserved_frame,
13279	=> unreachable,	14471	=> unreachable,
13280	.undef => {},	14472	.undef => if (opts.safety) switch (dst_reg.class()) {
		14473	.general_purpose => switch (abi_size) {
		14474	1 => try self.asmRegisterImmediate(.{ ._, .mov }, dst_reg.to8(), Immediate.u(0xAA)),
		14475	2 => try self.asmRegisterImmediate(.{ ._, .mov }, dst_reg.to16(), Immediate.u(0xAAAA)),
		14476	3...4 => try self.asmRegisterImmediate(
		14477	.{ ._, .mov },
		14478	dst_reg.to32(),
		14479	Immediate.s(@as(i32, @bitCast(@as(u32, 0xAAAAAAAA)))),
		14480	),
		14481	5...8 => try self.asmRegisterImmediate(
		14482	.{ ._, .mov },
		14483	dst_reg.to64(),
		14484	Immediate.u(0xAAAAAAAAAAAAAAAA),
		14485	),
		14486	else => unreachable,
		14487	},
		14488	.segment, .x87, .mmx, .sse => try self.genSetReg(dst_reg, ty, try self.genTypedValue(.{
		14489	.ty = ty,
		14490	.val = try mod.undefValue(ty),
		14491	}), opts),
		14492	},
13281	.eflags => \|cc\| try self.asmSetccRegister(cc, dst_reg.to8()),	14493	.eflags => \|cc\| try self.asmSetccRegister(cc, dst_reg.to8()),
13282	.immediate => \|imm\| {	14494	.immediate => \|imm\| {
13283	if (imm == 0) {	14495	if (imm == 0) {
...	@@ -13362,6 +14574,7 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr	...	@@ -13362,6 +14574,7 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
13362	dst_reg,	14574	dst_reg,
13363	ty,	14575	ty,
13364	.{ .register = try self.copyToTmpRegister(ty, src_mcv) },	14576	.{ .register = try self.copyToTmpRegister(ty, src_mcv) },
		14577	opts,
13365	),	14578	),
13366	.x87, .mmx => unreachable,	14579	.x87, .mmx => unreachable,
13367	.sse => try self.asmRegisterRegister(	14580	.sse => try self.asmRegisterRegister(
...	@@ -13391,21 +14604,23 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr	...	@@ -13391,21 +14604,23 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
13391	),	14604	),
13392	},	14605	},
13393	},	14606	},
13394	.register_pair => \|src_regs\| try self.genSetReg(dst_reg, ty, .{ .register = src_regs[0] }),	14607	.register_pair => \|src_regs\| try self.genSetReg(dst_reg, ty, .{ .register = src_regs[0] }, opts),
13395	.register_offset,	14608	.register_offset,
13396	.indirect,	14609	.indirect,
13397	.load_frame,	14610	.load_frame,
13398	.lea_frame,	14611	.lea_frame,
13399	=> try @as(MoveStrategy, switch (src_mcv) {	14612	=> try @as(MoveStrategy, switch (src_mcv) {
13400	.register_offset => \|reg_off\| switch (reg_off.off) {	14613	.register_offset => \|reg_off\| switch (reg_off.off) {
13401	0 => return self.genSetReg(dst_reg, ty, .{ .register = reg_off.reg }),	14614	0 => return self.genSetReg(dst_reg, ty, .{ .register = reg_off.reg }, opts),
13402	else => .{ .move = .{ ._, .lea } },	14615	else => .{ .move = .{ ._, .lea } },
13403	},	14616	},
13404	.indirect => try self.moveStrategy(ty, dst_reg.class(), false),	14617	.indirect => try self.moveStrategy(ty, dst_reg.class(), false),
13405	.load_frame => \|frame_addr\| try self.moveStrategy(	14618	.load_frame => \|frame_addr\| try self.moveStrategy(
13406	ty,	14619	ty,
13407	dst_reg.class(),	14620	dst_reg.class(),
13408	self.getFrameAddrAlignment(frame_addr).compare(.gte, ty.abiAlignment(mod)),	14621	self.getFrameAddrAlignment(frame_addr).compare(.gte, Alignment.fromLog2Units(
		14622	std.math.log2_int_ceil(u10, @divExact(dst_reg.bitSize(), 8)),
		14623	)),
13409	),	14624	),
13410	.lea_frame => .{ .move = .{ ._, .lea } },	14625	.lea_frame => .{ .move = .{ ._, .lea } },
13411	else => unreachable,	14626	else => unreachable,
...	@@ -13540,11 +14755,18 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr	...	@@ -13540,11 +14755,18 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
13540	});	14755	});
13541	},	14756	},
13542	.lea_tlv => unreachable, // TODO: remove this	14757	.lea_tlv => unreachable, // TODO: remove this
13543	.air_ref => \|src_ref\| try self.genSetReg(dst_reg, ty, try self.resolveInst(src_ref)),	14758	.air_ref => \|src_ref\| try self.genSetReg(dst_reg, ty, try self.resolveInst(src_ref), opts),
13544	}	14759	}
13545	}	14760	}
13546		14761
13547	fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCValue) InnerError!void {	14762	fn genSetMem(
		14763	self: *Self,
		14764	base: Memory.Base,
		14765	disp: i32,
		14766	ty: Type,
		14767	src_mcv: MCValue,
		14768	opts: CopyOptions,
		14769	) InnerError!void {
13548	const mod = self.bin_file.comp.module.?;	14770	const mod = self.bin_file.comp.module.?;
13549	const abi_size: u32 = @intCast(ty.abiSize(mod));	14771	const abi_size: u32 = @intCast(ty.abiSize(mod));
13550	const dst_ptr_mcv: MCValue = switch (base) {	14772	const dst_ptr_mcv: MCValue = switch (base) {
...	@@ -13554,11 +14776,17 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal	...	@@ -13554,11 +14776,17 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal
13554	.reloc => \|base_symbol\| .{ .lea_symbol = .{ .sym = base_symbol.sym_index, .off = disp } },	14776	.reloc => \|base_symbol\| .{ .lea_symbol = .{ .sym = base_symbol.sym_index, .off = disp } },
13555	};	14777	};
13556	switch (src_mcv) {	14778	switch (src_mcv) {
13557	.none, .unreach, .dead, .reserved_frame => unreachable,	14779	.none,
13558	.undef => try self.genInlineMemset(	14780	.unreach,
		14781	.dead,
		14782	.elementwise_regs_then_frame,
		14783	.reserved_frame,
		14784	=> unreachable,
		14785	.undef => if (opts.safety) try self.genInlineMemset(
13559	dst_ptr_mcv,	14786	dst_ptr_mcv,
13560	.{ .immediate = 0xaa },	14787	src_mcv,
13561	.{ .immediate = abi_size },	14788	.{ .immediate = abi_size },
		14789	opts,
13562	),	14790	),
13563	.immediate => \|imm\| switch (abi_size) {	14791	.immediate => \|imm\| switch (abi_size) {
13564	1, 2, 4 => {	14792	1, 2, 4 => {
...	@@ -13639,7 +14867,7 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal	...	@@ -13639,7 +14867,7 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal
13639	} } },	14867	} } },
13640	src_alias,	14868	src_alias,
13641	);	14869	);
13642	try self.genSetMem(base, disp, ty, frame_mcv);	14870	try self.genSetMem(base, disp, ty, frame_mcv, opts);
13643	try self.freeValue(frame_mcv);	14871	try self.freeValue(frame_mcv);
13644	} else try (try self.moveStrategy(ty, src_alias.class(), switch (base) {	14872	} else try (try self.moveStrategy(ty, src_alias.class(), switch (base) {
13645	.none => ty.abiAlignment(mod).check(@as(u32, @bitCast(disp))),	14873	.none => ty.abiAlignment(mod).check(@as(u32, @bitCast(disp))),
...	@@ -13663,7 +14891,7 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal	...	@@ -13663,7 +14891,7 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal
13663	.register_pair => \|src_regs\| {	14891	.register_pair => \|src_regs\| {
13664	var part_disp: i32 = disp;	14892	var part_disp: i32 = disp;
13665	for (try self.splitType(ty), src_regs) \|src_ty, src_reg\| {	14893	for (try self.splitType(ty), src_regs) \|src_ty, src_reg\| {
13666	try self.genSetMem(base, part_disp, src_ty, .{ .register = src_reg });	14894	try self.genSetMem(base, part_disp, src_ty, .{ .register = src_reg }, opts);
13667	part_disp += @intCast(src_ty.abiSize(mod));	14895	part_disp += @intCast(src_ty.abiSize(mod));
13668	}	14896	}
13669	},	14897	},
...	@@ -13674,23 +14902,26 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal	...	@@ -13674,23 +14902,26 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal
13674	disp + @as(i32, @intCast(ty.structFieldOffset(0, mod))),	14902	disp + @as(i32, @intCast(ty.structFieldOffset(0, mod))),
13675	ty.structFieldType(0, mod),	14903	ty.structFieldType(0, mod),
13676	.{ .register = ro.reg },	14904	.{ .register = ro.reg },
		14905	opts,
13677	);	14906	);
13678	try self.genSetMem(	14907	try self.genSetMem(
13679	base,	14908	base,
13680	disp + @as(i32, @intCast(ty.structFieldOffset(1, mod))),	14909	disp + @as(i32, @intCast(ty.structFieldOffset(1, mod))),
13681	ty.structFieldType(1, mod),	14910	ty.structFieldType(1, mod),
13682	.{ .eflags = ro.eflags },	14911	.{ .eflags = ro.eflags },
		14912	opts,
13683	);	14913	);
13684	},	14914	},
13685	.Optional => {	14915	.Optional => {
13686	assert(!ty.optionalReprIsPayload(mod));	14916	assert(!ty.optionalReprIsPayload(mod));
13687	const child_ty = ty.optionalChild(mod);	14917	const child_ty = ty.optionalChild(mod);
13688	try self.genSetMem(base, disp, child_ty, .{ .register = ro.reg });	14918	try self.genSetMem(base, disp, child_ty, .{ .register = ro.reg }, opts);
13689	try self.genSetMem(	14919	try self.genSetMem(
13690	base,	14920	base,
13691	disp + @as(i32, @intCast(child_ty.abiSize(mod))),	14921	disp + @as(i32, @intCast(child_ty.abiSize(mod))),
13692	Type.bool,	14922	Type.bool,
13693	.{ .eflags = ro.eflags },	14923	.{ .eflags = ro.eflags },
		14924	opts,
13694	);	14925	);
13695	},	14926	},
13696	else => return self.fail("TODO implement genSetMem for {s} of {}", .{	14927	else => return self.fail("TODO implement genSetMem for {s} of {}", .{
...	@@ -13717,27 +14948,37 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal	...	@@ -13717,27 +14948,37 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal
13717	const src_lock = self.register_manager.lockRegAssumeUnused(src_reg);	14948	const src_lock = self.register_manager.lockRegAssumeUnused(src_reg);
13718	defer self.register_manager.unlockReg(src_lock);	14949	defer self.register_manager.unlockReg(src_lock);
13719		14950
13720	try self.genSetMem(base, disp, ty, .{ .register = src_reg });	14951	try self.genSetMem(base, disp, ty, .{ .register = src_reg }, opts);
13721	},	14952	},
13722	else => try self.genInlineMemcpy(dst_ptr_mcv, src_mcv.address(), .{ .immediate = abi_size }),	14953	else => try self.genInlineMemcpy(
		14954	dst_ptr_mcv,
		14955	src_mcv.address(),
		14956	.{ .immediate = abi_size },
		14957	),
13723	},	14958	},
13724	.air_ref => \|src_ref\| try self.genSetMem(base, disp, ty, try self.resolveInst(src_ref)),	14959	.air_ref => \|src_ref\| try self.genSetMem(base, disp, ty, try self.resolveInst(src_ref), opts),
13725	}	14960	}
13726	}	14961	}
13727		14962
13728	fn genInlineMemcpy(self: *Self, dst_ptr: MCValue, src_ptr: MCValue, len: MCValue) InnerError!void {	14963	fn genInlineMemcpy(self: *Self, dst_ptr: MCValue, src_ptr: MCValue, len: MCValue) InnerError!void {
13729	try self.spillRegisters(&.{ .rsi, .rdi, .rcx });	14964	try self.spillRegisters(&.{ .rsi, .rdi, .rcx });
13730	try self.genSetReg(.rsi, Type.usize, src_ptr);	14965	try self.genSetReg(.rsi, Type.usize, src_ptr, .{});
13731	try self.genSetReg(.rdi, Type.usize, dst_ptr);	14966	try self.genSetReg(.rdi, Type.usize, dst_ptr, .{});
13732	try self.genSetReg(.rcx, Type.usize, len);	14967	try self.genSetReg(.rcx, Type.usize, len, .{});
13733	try self.asmOpOnly(.{ .@"rep _sb", .mov });	14968	try self.asmOpOnly(.{ .@"rep _sb", .mov });
13734	}	14969	}
13735		14970
13736	fn genInlineMemset(self: *Self, dst_ptr: MCValue, value: MCValue, len: MCValue) InnerError!void {	14971	fn genInlineMemset(
		14972	self: *Self,
		14973	dst_ptr: MCValue,
		14974	value: MCValue,
		14975	len: MCValue,
		14976	opts: CopyOptions,
		14977	) InnerError!void {
13737	try self.spillRegisters(&.{ .rdi, .al, .rcx });	14978	try self.spillRegisters(&.{ .rdi, .al, .rcx });
13738	try self.genSetReg(.rdi, Type.usize, dst_ptr);	14979	try self.genSetReg(.rdi, Type.usize, dst_ptr, .{});
13739	try self.genSetReg(.al, Type.u8, value);	14980	try self.genSetReg(.al, Type.u8, value, opts);
13740	try self.genSetReg(.rcx, Type.usize, len);	14981	try self.genSetReg(.rcx, Type.usize, len, .{});
13741	try self.asmOpOnly(.{ .@"rep _sb", .sto });	14982	try self.asmOpOnly(.{ .@"rep _sb", .sto });
13742	}	14983	}
13743		14984
...	@@ -13801,10 +15042,10 @@ fn genLazySymbolRef(	...	@@ -13801,10 +15042,10 @@ fn genLazySymbolRef(
13801	switch (tag) {	15042	switch (tag) {
13802	.lea, .call => try self.genSetReg(reg, Type.usize, .{	15043	.lea, .call => try self.genSetReg(reg, Type.usize, .{
13803	.load_symbol = .{ .sym = sym.esym_index },	15044	.load_symbol = .{ .sym = sym.esym_index },
13804	}),	15045	}, .{}),
13805	.mov => try self.genSetReg(reg, Type.usize, .{	15046	.mov => try self.genSetReg(reg, Type.usize, .{
13806	.load_symbol = .{ .sym = sym.esym_index },	15047	.load_symbol = .{ .sym = sym.esym_index },
13807	}),	15048	}, .{}),
13808	else => unreachable,	15049	else => unreachable,
13809	}	15050	}
13810	switch (tag) {	15051	switch (tag) {
...	@@ -13861,8 +15102,8 @@ fn genLazySymbolRef(	...	@@ -13861,8 +15102,8 @@ fn genLazySymbolRef(
13861	return self.fail("{s} creating lazy symbol", .{@errorName(err)});	15102	return self.fail("{s} creating lazy symbol", .{@errorName(err)});
13862	const sym_index = coff_file.getAtom(atom_index).getSymbolIndex().?;	15103	const sym_index = coff_file.getAtom(atom_index).getSymbolIndex().?;
13863	switch (tag) {	15104	switch (tag) {
13864	.lea, .call => try self.genSetReg(reg, Type.usize, .{ .lea_got = sym_index }),	15105	.lea, .call => try self.genSetReg(reg, Type.usize, .{ .lea_got = sym_index }, .{}),
13865	.mov => try self.genSetReg(reg, Type.usize, .{ .load_got = sym_index }),	15106	.mov => try self.genSetReg(reg, Type.usize, .{ .load_got = sym_index }, .{}),
13866	else => unreachable,	15107	else => unreachable,
13867	}	15108	}
13868	switch (tag) {	15109	switch (tag) {
...	@@ -13875,8 +15116,13 @@ fn genLazySymbolRef(	...	@@ -13875,8 +15116,13 @@ fn genLazySymbolRef(
13875	return self.fail("{s} creating lazy symbol", .{@errorName(err)});	15116	return self.fail("{s} creating lazy symbol", .{@errorName(err)});
13876	const sym = macho_file.getSymbol(sym_index);	15117	const sym = macho_file.getSymbol(sym_index);
13877	switch (tag) {	15118	switch (tag) {
13878	.lea, .call => try self.genSetReg(reg, Type.usize, .{ .load_symbol = .{ .sym = sym.nlist_idx } }),	15119	.lea, .call => try self.genSetReg(
13879	.mov => try self.genSetReg(reg, Type.usize, .{ .load_symbol = .{ .sym = sym.nlist_idx } }),	15120	reg,
		15121	Type.usize,
		15122	.{ .load_symbol = .{ .sym = sym.nlist_idx } },
		15123	.{},
		15124	),
		15125	.mov => try self.genSetReg(reg, Type.usize, .{ .load_symbol = .{ .sym = sym.nlist_idx } }, .{}),
13880	else => unreachable,	15126	else => unreachable,
13881	}	15127	}
13882	switch (tag) {	15128	switch (tag) {
...	@@ -13898,7 +15144,7 @@ fn airIntFromPtr(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -13898,7 +15144,7 @@ fn airIntFromPtr(self: *Self, inst: Air.Inst.Index) !void {
13898		15144
13899	const dst_mcv = try self.allocRegOrMem(inst, true);	15145	const dst_mcv = try self.allocRegOrMem(inst, true);
13900	const dst_ty = self.typeOfIndex(inst);	15146	const dst_ty = self.typeOfIndex(inst);
13901	try self.genCopy(dst_ty, dst_mcv, src_mcv);	15147	try self.genCopy(dst_ty, dst_mcv, src_mcv, .{});
13902	break :result dst_mcv;	15148	break :result dst_mcv;
13903	};	15149	};
13904	return self.finishAir(inst, result, .{ un_op, .none, .none });	15150	return self.finishAir(inst, result, .{ un_op, .none, .none });
...	@@ -13925,7 +15171,7 @@ fn airBitCast(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -13925,7 +15171,7 @@ fn airBitCast(self: *Self, inst: Air.Inst.Index) !void {
13925	.lt => dst_ty,	15171	.lt => dst_ty,
13926	.eq => if (!dst_mcv.isMemory() or src_mcv.isMemory()) dst_ty else src_ty,	15172	.eq => if (!dst_mcv.isMemory() or src_mcv.isMemory()) dst_ty else src_ty,
13927	.gt => src_ty,	15173	.gt => src_ty,
13928	}, dst_mcv, src_mcv);	15174	}, dst_mcv, src_mcv, .{});
13929	break :dst dst_mcv;	15175	break :dst dst_mcv;
13930	};	15176	};
13931		15177
...	@@ -13956,6 +15202,7 @@ fn airBitCast(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -13956,6 +15202,7 @@ fn airBitCast(self: *Self, inst: Air.Inst.Index) !void {
13956	if (abi_size <= 8) dst_ty else Type.usize,	15202	if (abi_size <= 8) dst_ty else Type.usize,
13957	high_mcv,	15203	high_mcv,
13958	.{ .register = high_reg },	15204	.{ .register = high_reg },
		15205	.{},
13959	);	15206	);
13960	break :result dst_mcv;	15207	break :result dst_mcv;
13961	};	15208	};
...	@@ -13973,12 +15220,13 @@ fn airArrayToSlice(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -13973,12 +15220,13 @@ fn airArrayToSlice(self: *Self, inst: Air.Inst.Index) !void {
13973	const array_len = array_ty.arrayLen(mod);	15220	const array_len = array_ty.arrayLen(mod);
13974		15221
13975	const frame_index = try self.allocFrameIndex(FrameAlloc.initSpill(slice_ty, mod));	15222	const frame_index = try self.allocFrameIndex(FrameAlloc.initSpill(slice_ty, mod));
13976	try self.genSetMem(.{ .frame = frame_index }, 0, ptr_ty, ptr);	15223	try self.genSetMem(.{ .frame = frame_index }, 0, ptr_ty, ptr, .{});
13977	try self.genSetMem(	15224	try self.genSetMem(
13978	.{ .frame = frame_index },	15225	.{ .frame = frame_index },
13979	@intCast(ptr_ty.abiSize(mod)),	15226	@intCast(ptr_ty.abiSize(mod)),
13980	Type.usize,	15227	Type.usize,
13981	.{ .immediate = array_len },	15228	.{ .immediate = array_len },
		15229	.{},
13982	);	15230	);
13983		15231
13984	const result = MCValue{ .load_frame = .{ .index = frame_index } };	15232	const result = MCValue{ .load_frame = .{ .index = frame_index } };
...	@@ -14158,9 +15406,9 @@ fn airCmpxchg(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -14158,9 +15406,9 @@ fn airCmpxchg(self: *Self, inst: Air.Inst.Index) !void {
14158	if (exp_addr_mcv.getReg()) \|reg\| self.register_manager.lockReg(reg) else null;	15406	if (exp_addr_mcv.getReg()) \|reg\| self.register_manager.lockReg(reg) else null;
14159	defer if (exp_addr_lock) \|lock\| self.register_manager.unlockReg(lock);	15407	defer if (exp_addr_lock) \|lock\| self.register_manager.unlockReg(lock);
14160		15408
14161	try self.genSetReg(.rax, Type.usize, exp_addr_mcv.deref());	15409	try self.genSetReg(.rax, Type.usize, exp_addr_mcv.deref(), .{});
14162	try self.genSetReg(.rdx, Type.usize, exp_addr_mcv.offset(8).deref());	15410	try self.genSetReg(.rdx, Type.usize, exp_addr_mcv.offset(8).deref(), .{});
14163	} else try self.genSetReg(.rax, val_ty, exp_mcv);	15411	} else try self.genSetReg(.rax, val_ty, exp_mcv, .{});
14164		15412
14165	const new_mcv = try self.resolveInst(extra.new_value);	15413	const new_mcv = try self.resolveInst(extra.new_value);
14166	const new_reg = if (val_abi_size > 8) new: {	15414	const new_reg = if (val_abi_size > 8) new: {
...	@@ -14172,8 +15420,8 @@ fn airCmpxchg(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -14172,8 +15420,8 @@ fn airCmpxchg(self: *Self, inst: Air.Inst.Index) !void {
14172	if (new_addr_mcv.getReg()) \|reg\| self.register_manager.lockReg(reg) else null;	15420	if (new_addr_mcv.getReg()) \|reg\| self.register_manager.lockReg(reg) else null;
14173	defer if (new_addr_lock) \|lock\| self.register_manager.unlockReg(lock);	15421	defer if (new_addr_lock) \|lock\| self.register_manager.unlockReg(lock);
14174		15422
14175	try self.genSetReg(.rbx, Type.usize, new_addr_mcv.deref());	15423	try self.genSetReg(.rbx, Type.usize, new_addr_mcv.deref(), .{});
14176	try self.genSetReg(.rcx, Type.usize, new_addr_mcv.offset(8).deref());	15424	try self.genSetReg(.rcx, Type.usize, new_addr_mcv.offset(8).deref(), .{});
14177	break :new null;	15425	break :new null;
14178	} else try self.copyToTmpRegister(val_ty, new_mcv);	15426	} else try self.copyToTmpRegister(val_ty, new_mcv);
14179	const new_lock = if (new_reg) \|reg\| self.register_manager.lockRegAssumeUnused(reg) else null;	15427	const new_lock = if (new_reg) \|reg\| self.register_manager.lockRegAssumeUnused(reg) else null;
...	@@ -14214,9 +15462,9 @@ fn airCmpxchg(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -14214,9 +15462,9 @@ fn airCmpxchg(self: *Self, inst: Air.Inst.Index) !void {
14214	}	15462	}
14215		15463
14216	const dst_mcv = try self.allocRegOrMem(inst, false);	15464	const dst_mcv = try self.allocRegOrMem(inst, false);
14217	try self.genCopy(Type.usize, dst_mcv, .{ .register = .rax });	15465	try self.genCopy(Type.usize, dst_mcv, .{ .register = .rax }, .{});
14218	try self.genCopy(Type.usize, dst_mcv.address().offset(8).deref(), .{ .register = .rdx });	15466	try self.genCopy(Type.usize, dst_mcv.address().offset(8).deref(), .{ .register = .rdx }, .{});
14219	try self.genCopy(Type.bool, dst_mcv.address().offset(16).deref(), .{ .eflags = .ne });	15467	try self.genCopy(Type.bool, dst_mcv.address().offset(16).deref(), .{ .eflags = .ne }, .{});
14220	break :result dst_mcv;	15468	break :result dst_mcv;
14221	};	15469	};
14222	return self.finishAir(inst, result, .{ extra.ptr, extra.expected_value, extra.new_value });	15470	return self.finishAir(inst, result, .{ extra.ptr, extra.expected_value, extra.new_value });
...	@@ -14300,7 +15548,7 @@ fn atomicOp(	...	@@ -14300,7 +15548,7 @@ fn atomicOp(
14300	const dst_lock = self.register_manager.lockRegAssumeUnused(dst_reg);	15548	const dst_lock = self.register_manager.lockRegAssumeUnused(dst_reg);
14301	defer self.register_manager.unlockReg(dst_lock);	15549	defer self.register_manager.unlockReg(dst_lock);
14302		15550
14303	try self.genSetReg(dst_reg, val_ty, val_mcv);	15551	try self.genSetReg(dst_reg, val_ty, val_mcv, .{});
14304	if (rmw_op == std.builtin.AtomicRmwOp.Sub and tag == .xadd) {	15552	if (rmw_op == std.builtin.AtomicRmwOp.Sub and tag == .xadd) {
14305	try self.genUnOpMir(.{ ._, .neg }, val_ty, dst_mcv);	15553	try self.genUnOpMir(.{ ._, .neg }, val_ty, dst_mcv);
14306	}	15554	}
...	@@ -14333,7 +15581,7 @@ fn atomicOp(	...	@@ -14333,7 +15581,7 @@ fn atomicOp(
14333	try self.asmRegisterMemory(.{ ._, .mov }, registerAlias(.rax, val_abi_size), ptr_mem);	15581	try self.asmRegisterMemory(.{ ._, .mov }, registerAlias(.rax, val_abi_size), ptr_mem);
14334	const loop: Mir.Inst.Index = @intCast(self.mir_instructions.len);	15582	const loop: Mir.Inst.Index = @intCast(self.mir_instructions.len);
14335	if (!use_sse and rmw_op orelse .Xchg != .Xchg) {	15583	if (!use_sse and rmw_op orelse .Xchg != .Xchg) {
14336	try self.genSetReg(tmp_reg, val_ty, .{ .register = .rax });	15584	try self.genSetReg(tmp_reg, val_ty, .{ .register = .rax }, .{});
14337	}	15585	}
14338	if (rmw_op) \|op\| if (use_sse) {	15586	if (rmw_op) \|op\| if (use_sse) {
14339	const mir_tag = @as(?Mir.Inst.FixedTag, switch (op) {	15587	const mir_tag = @as(?Mir.Inst.FixedTag, switch (op) {
...	@@ -14361,7 +15609,7 @@ fn atomicOp(	...	@@ -14361,7 +15609,7 @@ fn atomicOp(
14361	}) orelse return self.fail("TODO implement atomicOp of {s} for {}", .{	15609	}) orelse return self.fail("TODO implement atomicOp of {s} for {}", .{
14362	@tagName(op), val_ty.fmt(mod),	15610	@tagName(op), val_ty.fmt(mod),
14363	});	15611	});
14364	try self.genSetReg(sse_reg, val_ty, .{ .register = .rax });	15612	try self.genSetReg(sse_reg, val_ty, .{ .register = .rax }, .{});
14365	switch (mir_tag[0]) {	15613	switch (mir_tag[0]) {
14366	.v_ss, .v_sd => if (val_mcv.isMemory()) try self.asmRegisterRegisterMemory(	15614	.v_ss, .v_sd => if (val_mcv.isMemory()) try self.asmRegisterRegisterMemory(
14367	mir_tag,	15615	mir_tag,
...	@@ -14391,9 +15639,9 @@ fn atomicOp(	...	@@ -14391,9 +15639,9 @@ fn atomicOp(
14391	),	15639	),
14392	else => unreachable,	15640	else => unreachable,
14393	}	15641	}
14394	try self.genSetReg(tmp_reg, val_ty, .{ .register = sse_reg });	15642	try self.genSetReg(tmp_reg, val_ty, .{ .register = sse_reg }, .{});
14395	} else switch (op) {	15643	} else switch (op) {
14396	.Xchg => try self.genSetReg(tmp_reg, val_ty, val_mcv),	15644	.Xchg => try self.genSetReg(tmp_reg, val_ty, val_mcv, .{}),
14397	.Add => try self.genBinOpMir(.{ ._, .add }, val_ty, tmp_mcv, val_mcv),	15645	.Add => try self.genBinOpMir(.{ ._, .add }, val_ty, tmp_mcv, val_mcv),
14398	.Sub => try self.genBinOpMir(.{ ._, .sub }, val_ty, tmp_mcv, val_mcv),	15646	.Sub => try self.genBinOpMir(.{ ._, .sub }, val_ty, tmp_mcv, val_mcv),
14399	.And => try self.genBinOpMir(.{ ._, .@"and" }, val_ty, tmp_mcv, val_mcv),	15647	.And => try self.genBinOpMir(.{ ._, .@"and" }, val_ty, tmp_mcv, val_mcv),
...	@@ -14683,7 +15931,7 @@ fn airMemset(self: *Self, inst: Air.Inst.Index, safety: bool) !void {	...	@@ -14683,7 +15931,7 @@ fn airMemset(self: *Self, inst: Air.Inst.Index, safety: bool) !void {
14683	};	15931	};
14684	defer if (len_lock) \|lock\| self.register_manager.unlockReg(lock);	15932	defer if (len_lock) \|lock\| self.register_manager.unlockReg(lock);
14685		15933
14686	try self.genInlineMemset(ptr, src_val, len);	15934	try self.genInlineMemset(ptr, src_val, len, .{ .safety = safety });
14687	break :result;	15935	break :result;
14688	}	15936	}
14689		15937
...	@@ -14705,11 +15953,11 @@ fn airMemset(self: *Self, inst: Air.Inst.Index, safety: bool) !void {	...	@@ -14705,11 +15953,11 @@ fn airMemset(self: *Self, inst: Air.Inst.Index, safety: bool) !void {
14705	const len_lock = self.register_manager.lockRegAssumeUnused(len_reg);	15953	const len_lock = self.register_manager.lockRegAssumeUnused(len_reg);
14706	defer self.register_manager.unlockReg(len_lock);	15954	defer self.register_manager.unlockReg(len_lock);
14707		15955
14708	try self.genSetReg(len_reg, Type.usize, len);	15956	try self.genSetReg(len_reg, Type.usize, len, .{});
14709	try self.asmRegisterRegister(.{ ._, .@"test" }, len_reg, len_reg);	15957	try self.asmRegisterRegister(.{ ._, .@"test" }, len_reg, len_reg);
14710		15958
14711	const skip_reloc = try self.asmJccReloc(.z, undefined);	15959	const skip_reloc = try self.asmJccReloc(.z, undefined);
14712	try self.store(slice_ptr_ty, ptr, src_val);	15960	try self.store(slice_ptr_ty, ptr, src_val, .{ .safety = safety });
14713		15961
14714	const second_elem_ptr_reg =	15962	const second_elem_ptr_reg =
14715	try self.register_manager.allocReg(null, abi.RegisterClass.gp);	15963	try self.register_manager.allocReg(null, abi.RegisterClass.gp);
...	@@ -14721,7 +15969,7 @@ fn airMemset(self: *Self, inst: Air.Inst.Index, safety: bool) !void {	...	@@ -14721,7 +15969,7 @@ fn airMemset(self: *Self, inst: Air.Inst.Index, safety: bool) !void {
14721	try self.genSetReg(second_elem_ptr_reg, Type.usize, .{ .register_offset = .{	15969	try self.genSetReg(second_elem_ptr_reg, Type.usize, .{ .register_offset = .{
14722	.reg = try self.copyToTmpRegister(Type.usize, ptr),	15970	.reg = try self.copyToTmpRegister(Type.usize, ptr),
14723	.off = elem_abi_size,	15971	.off = elem_abi_size,
14724	} });	15972	} }, .{});
14725		15973
14726	try self.genBinOpMir(.{ ._, .sub }, Type.usize, len_mcv, .{ .immediate = 1 });	15974	try self.genBinOpMir(.{ ._, .sub }, Type.usize, len_mcv, .{ .immediate = 1 });
14727	try self.asmRegisterRegisterImmediate(	15975	try self.asmRegisterRegisterImmediate(
...	@@ -14732,7 +15980,7 @@ fn airMemset(self: *Self, inst: Air.Inst.Index, safety: bool) !void {	...	@@ -14732,7 +15980,7 @@ fn airMemset(self: *Self, inst: Air.Inst.Index, safety: bool) !void {
14732	);	15980	);
14733	try self.genInlineMemcpy(second_elem_ptr_mcv, ptr, len_mcv);	15981	try self.genInlineMemcpy(second_elem_ptr_mcv, ptr, len_mcv);
14734		15982
14735	try self.performReloc(skip_reloc);	15983	self.performReloc(skip_reloc);
14736	},	15984	},
14737	.One => {	15985	.One => {
14738	const elem_ptr_ty = try mod.singleMutPtrType(elem_ty);	15986	const elem_ptr_ty = try mod.singleMutPtrType(elem_ty);
...	@@ -14740,7 +15988,7 @@ fn airMemset(self: *Self, inst: Air.Inst.Index, safety: bool) !void {	...	@@ -14740,7 +15988,7 @@ fn airMemset(self: *Self, inst: Air.Inst.Index, safety: bool) !void {
14740	const len = dst_ptr_ty.childType(mod).arrayLen(mod);	15988	const len = dst_ptr_ty.childType(mod).arrayLen(mod);
14741		15989
14742	assert(len != 0); // prevented by Sema	15990	assert(len != 0); // prevented by Sema
14743	try self.store(elem_ptr_ty, dst_ptr, src_val);	15991	try self.store(elem_ptr_ty, dst_ptr, src_val, .{ .safety = safety });
14744		15992
14745	const second_elem_ptr_reg =	15993	const second_elem_ptr_reg =
14746	try self.register_manager.allocReg(null, abi.RegisterClass.gp);	15994	try self.register_manager.allocReg(null, abi.RegisterClass.gp);
...	@@ -14752,7 +16000,7 @@ fn airMemset(self: *Self, inst: Air.Inst.Index, safety: bool) !void {	...	@@ -14752,7 +16000,7 @@ fn airMemset(self: *Self, inst: Air.Inst.Index, safety: bool) !void {
14752	try self.genSetReg(second_elem_ptr_reg, Type.usize, .{ .register_offset = .{	16000	try self.genSetReg(second_elem_ptr_reg, Type.usize, .{ .register_offset = .{
14753	.reg = try self.copyToTmpRegister(Type.usize, dst_ptr),	16001	.reg = try self.copyToTmpRegister(Type.usize, dst_ptr),
14754	.off = elem_abi_size,	16002	.off = elem_abi_size,
14755	} });	16003	} }, .{});
14756		16004
14757	const bytes_to_copy: MCValue = .{ .immediate = elem_abi_size * (len - 1) };	16005	const bytes_to_copy: MCValue = .{ .immediate = elem_abi_size * (len - 1) };
14758	try self.genInlineMemcpy(second_elem_ptr_mcv, dst_ptr, bytes_to_copy);	16006	try self.genInlineMemcpy(second_elem_ptr_mcv, dst_ptr, bytes_to_copy);
...	@@ -14846,10 +16094,10 @@ fn airTagName(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -14846,10 +16094,10 @@ fn airTagName(self: *Self, inst: Air.Inst.Index) !void {
14846	const param_regs = abi.getCAbiIntParamRegs(resolved_cc);	16094	const param_regs = abi.getCAbiIntParamRegs(resolved_cc);
14847		16095
14848	const dst_mcv = try self.allocRegOrMem(inst, false);	16096	const dst_mcv = try self.allocRegOrMem(inst, false);
14849	try self.genSetReg(param_regs[0], Type.usize, dst_mcv.address());	16097	try self.genSetReg(param_regs[0], Type.usize, dst_mcv.address(), .{});
14850		16098
14851	const operand = try self.resolveInst(un_op);	16099	const operand = try self.resolveInst(un_op);
14852	try self.genSetReg(param_regs[1], enum_ty, operand);	16100	try self.genSetReg(param_regs[1], enum_ty, operand, .{});
14853		16101
14854	try self.genLazySymbolRef(	16102	try self.genLazySymbolRef(
14855	.call,	16103	.call,
...	@@ -14979,11 +16227,12 @@ fn airSplat(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -14979,11 +16227,12 @@ fn airSplat(self: *Self, inst: Air.Inst.Index) !void {
14979	const reg_locks = self.register_manager.lockRegsAssumeUnused(2, regs);	16227	const reg_locks = self.register_manager.lockRegsAssumeUnused(2, regs);
14980	defer for (reg_locks) \|lock\| self.register_manager.unlockReg(lock);	16228	defer for (reg_locks) \|lock\| self.register_manager.unlockReg(lock);
14981		16229
14982	try self.genSetReg(regs[1], vector_ty, .{ .immediate = 0 });	16230	try self.genSetReg(regs[1], vector_ty, .{ .immediate = 0 }, .{});
14983	try self.genSetReg(	16231	try self.genSetReg(
14984	regs[1],	16232	regs[1],
14985	vector_ty,	16233	vector_ty,
14986	.{ .immediate = @as(u64, math.maxInt(u64)) >> @intCast(64 - vector_len) },	16234	.{ .immediate = @as(u64, math.maxInt(u64)) >> @intCast(64 - vector_len) },
		16235	.{},
14987	);	16236	);
14988	const src_mcv = try self.resolveInst(ty_op.operand);	16237	const src_mcv = try self.resolveInst(ty_op.operand);
14989	const abi_size = @max(math.divCeil(u32, vector_len, 8) catch unreachable, 4);	16238	const abi_size = @max(math.divCeil(u32, vector_len, 8) catch unreachable, 4);
...	@@ -15048,7 +16297,7 @@ fn airSplat(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -15048,7 +16297,7 @@ fn airSplat(self: *Self, inst: Air.Inst.Index) !void {
15048	try src_mcv.mem(self, self.memSize(scalar_ty)),	16297	try src_mcv.mem(self, self.memSize(scalar_ty)),
15049	) else {	16298	) else {
15050	if (mir_tag[0] == .vp_i128) break :avx2;	16299	if (mir_tag[0] == .vp_i128) break :avx2;
15051	try self.genSetReg(dst_reg, scalar_ty, src_mcv);	16300	try self.genSetReg(dst_reg, scalar_ty, src_mcv, .{});
15052	try self.asmRegisterRegister(	16301	try self.asmRegisterRegister(
15053	mir_tag,	16302	mir_tag,
15054	registerAlias(dst_reg, @intCast(vector_ty.abiSize(mod))),	16303	registerAlias(dst_reg, @intCast(vector_ty.abiSize(mod))),
...	@@ -15061,7 +16310,7 @@ fn airSplat(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -15061,7 +16310,7 @@ fn airSplat(self: *Self, inst: Air.Inst.Index) !void {
15061	const dst_lock = self.register_manager.lockRegAssumeUnused(dst_reg);	16310	const dst_lock = self.register_manager.lockRegAssumeUnused(dst_reg);
15062	defer self.register_manager.unlockReg(dst_lock);	16311	defer self.register_manager.unlockReg(dst_lock);
15063		16312
15064	try self.genSetReg(dst_reg, scalar_ty, .{ .air_ref = ty_op.operand });	16313	try self.genSetReg(dst_reg, scalar_ty, .{ .air_ref = ty_op.operand }, .{});
15065	if (vector_len == 1) break :result .{ .register = dst_reg };	16314	if (vector_len == 1) break :result .{ .register = dst_reg };
15066		16315
15067	const dst_alias = registerAlias(dst_reg, @intCast(vector_ty.abiSize(mod)));	16316	const dst_alias = registerAlias(dst_reg, @intCast(vector_ty.abiSize(mod)));
...	@@ -15111,7 +16360,7 @@ fn airSplat(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -15111,7 +16360,7 @@ fn airSplat(self: *Self, inst: Air.Inst.Index) !void {
15111	const src_mcv = try self.resolveInst(ty_op.operand);	16360	const src_mcv = try self.resolveInst(ty_op.operand);
15112	if (self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) break :result src_mcv;	16361	if (self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) break :result src_mcv;
15113	const dst_reg = try self.register_manager.allocReg(inst, dst_rc);	16362	const dst_reg = try self.register_manager.allocReg(inst, dst_rc);
15114	try self.genSetReg(dst_reg, scalar_ty, src_mcv);	16363	try self.genSetReg(dst_reg, scalar_ty, src_mcv, .{});
15115	break :result .{ .register = dst_reg };	16364	break :result .{ .register = dst_reg };
15116	},	16365	},
15117	2...4 => {	16366	2...4 => {
...	@@ -15194,7 +16443,7 @@ fn airSplat(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -15194,7 +16443,7 @@ fn airSplat(self: *Self, inst: Air.Inst.Index) !void {
15194	const src_mcv = try self.resolveInst(ty_op.operand);	16443	const src_mcv = try self.resolveInst(ty_op.operand);
15195	if (self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) break :result src_mcv;	16444	if (self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) break :result src_mcv;
15196	const dst_reg = try self.register_manager.allocReg(inst, dst_rc);	16445	const dst_reg = try self.register_manager.allocReg(inst, dst_rc);
15197	try self.genSetReg(dst_reg, scalar_ty, src_mcv);	16446	try self.genSetReg(dst_reg, scalar_ty, src_mcv, .{});
15198	break :result .{ .register = dst_reg };	16447	break :result .{ .register = dst_reg };
15199	},	16448	},
15200	2 => {	16449	2 => {
...	@@ -15263,7 +16512,7 @@ fn airSplat(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -15263,7 +16512,7 @@ fn airSplat(self: *Self, inst: Air.Inst.Index) !void {
15263	const src_mcv = try self.resolveInst(ty_op.operand);	16512	const src_mcv = try self.resolveInst(ty_op.operand);
15264	if (self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) break :result src_mcv;	16513	if (self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) break :result src_mcv;
15265	const dst_reg = try self.register_manager.allocReg(inst, dst_rc);	16514	const dst_reg = try self.register_manager.allocReg(inst, dst_rc);
15266	try self.genSetReg(dst_reg, scalar_ty, src_mcv);	16515	try self.genSetReg(dst_reg, scalar_ty, src_mcv, .{});
15267	break :result .{ .register = dst_reg };	16516	break :result .{ .register = dst_reg };
15268	},	16517	},
15269	2 => if (self.hasFeature(.avx)) {	16518	2 => if (self.hasFeature(.avx)) {
...	@@ -15387,6 +16636,7 @@ fn airAggregateInit(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -15387,6 +16636,7 @@ fn airAggregateInit(self: *Self, inst: Air.Inst.Index) !void {
15387	.{ .lea_frame = .{ .index = frame_index } },	16636	.{ .lea_frame = .{ .index = frame_index } },
15388	.{ .immediate = 0 },	16637	.{ .immediate = 0 },
15389	.{ .immediate = result_ty.abiSize(mod) },	16638	.{ .immediate = result_ty.abiSize(mod) },
		16639	.{},
15390	);	16640	);
15391	for (elements, 0..) \|elem, elem_i_usize\| {	16641	for (elements, 0..) \|elem, elem_i_usize\| {
15392	const elem_i: u32 = @intCast(elem_i_usize);	16642	const elem_i: u32 = @intCast(elem_i_usize);
...	@@ -15431,6 +16681,7 @@ fn airAggregateInit(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -15431,6 +16681,7 @@ fn airAggregateInit(self: *Self, inst: Air.Inst.Index) !void {
15431	.{ ._l, .sh },	16681	.{ ._l, .sh },
15432	elem_ty,	16682	elem_ty,
15433	.{ .register = elem_reg },	16683	.{ .register = elem_reg },
		16684	Type.u8,
15434	.{ .immediate = elem_bit_off },	16685	.{ .immediate = elem_bit_off },
15435	);	16686	);
15436	try self.genBinOpMir(	16687	try self.genBinOpMir(
...	@@ -15448,6 +16699,7 @@ fn airAggregateInit(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -15448,6 +16699,7 @@ fn airAggregateInit(self: *Self, inst: Air.Inst.Index) !void {
15448	.{ ._r, .sh },	16699	.{ ._r, .sh },
15449	elem_ty,	16700	elem_ty,
15450	.{ .register = reg },	16701	.{ .register = reg },
		16702	Type.u8,
15451	.{ .immediate = elem_abi_bits - elem_bit_off },	16703	.{ .immediate = elem_abi_bits - elem_bit_off },
15452	);	16704	);
15453	try self.genBinOpMir(	16705	try self.genBinOpMir(
...	@@ -15471,7 +16723,7 @@ fn airAggregateInit(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -15471,7 +16723,7 @@ fn airAggregateInit(self: *Self, inst: Air.Inst.Index) !void {
15471	.load_tlv => \|sym_index\| MCValue{ .lea_tlv = sym_index },	16723	.load_tlv => \|sym_index\| MCValue{ .lea_tlv = sym_index },
15472	else => elem_mcv,	16724	else => elem_mcv,
15473	};	16725	};
15474	try self.genSetMem(.{ .frame = frame_index }, elem_off, elem_ty, mat_elem_mcv);	16726	try self.genSetMem(.{ .frame = frame_index }, elem_off, elem_ty, mat_elem_mcv, .{});
15475	}	16727	}
15476	break :result .{ .load_frame = .{ .index = frame_index } };	16728	break :result .{ .load_frame = .{ .index = frame_index } };
15477	},	16729	},
...	@@ -15519,13 +16771,20 @@ fn airAggregateInit(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -15519,13 +16771,20 @@ fn airAggregateInit(self: *Self, inst: Air.Inst.Index) !void {
15519	else => elem_mcv,	16771	else => elem_mcv,
15520	};	16772	};
15521	const elem_off: i32 = @intCast(elem_size * elem_i);	16773	const elem_off: i32 = @intCast(elem_size * elem_i);
15522	try self.genSetMem(.{ .frame = frame_index }, elem_off, elem_ty, mat_elem_mcv);	16774	try self.genSetMem(
		16775	.{ .frame = frame_index },
		16776	elem_off,
		16777	elem_ty,
		16778	mat_elem_mcv,
		16779	.{},
		16780	);
15523	}	16781	}
15524	if (result_ty.sentinel(mod)) \|sentinel\| try self.genSetMem(	16782	if (result_ty.sentinel(mod)) \|sentinel\| try self.genSetMem(
15525	.{ .frame = frame_index },	16783	.{ .frame = frame_index },
15526	@intCast(elem_size * elements.len),	16784	@intCast(elem_size * elements.len),
15527	elem_ty,	16785	elem_ty,
15528	try self.genTypedValue(.{ .ty = elem_ty, .val = sentinel }),	16786	try self.genTypedValue(.{ .ty = elem_ty, .val = sentinel }),
		16787	.{},
15529	);	16788	);
15530	break :result .{ .load_frame = .{ .index = frame_index } };	16789	break :result .{ .load_frame = .{ .index = frame_index } };
15531	}	16790	}
...	@@ -15560,7 +16819,7 @@ fn airUnionInit(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -15560,7 +16819,7 @@ fn airUnionInit(self: *Self, inst: Air.Inst.Index) !void {
15560	self.reuseOperand(inst, extra.init, 0, src_mcv)) break :result src_mcv;	16819	self.reuseOperand(inst, extra.init, 0, src_mcv)) break :result src_mcv;
15561		16820
15562	const dst_mcv = try self.allocRegOrMem(inst, true);	16821	const dst_mcv = try self.allocRegOrMem(inst, true);
15563	try self.genCopy(src_ty, dst_mcv, src_mcv);	16822	try self.genCopy(src_ty, dst_mcv, src_mcv, .{});
15564	break :result dst_mcv;	16823	break :result dst_mcv;
15565	}	16824	}
15566		16825
...	@@ -15577,13 +16836,18 @@ fn airUnionInit(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -15577,13 +16836,18 @@ fn airUnionInit(self: *Self, inst: Air.Inst.Index) !void {
15577	@intCast(layout.payload_size)	16836	@intCast(layout.payload_size)
15578	else	16837	else
15579	0;	16838	0;
15580	try self.genCopy(tag_ty, dst_mcv.address().offset(tag_off).deref(), .{ .immediate = tag_int });	16839	try self.genCopy(
		16840	tag_ty,
		16841	dst_mcv.address().offset(tag_off).deref(),
		16842	.{ .immediate = tag_int },
		16843	.{},
		16844	);
15581		16845
15582	const pl_off: i32 = if (layout.tag_align.compare(.lt, layout.payload_align))	16846	const pl_off: i32 = if (layout.tag_align.compare(.lt, layout.payload_align))
15583	0	16847	0
15584	else	16848	else
15585	@intCast(layout.tag_size);	16849	@intCast(layout.tag_size);
15586	try self.genCopy(src_ty, dst_mcv.address().offset(pl_off).deref(), src_mcv);	16850	try self.genCopy(src_ty, dst_mcv.address().offset(pl_off).deref(), src_mcv, .{});
15587		16851
15588	break :result dst_mcv;	16852	break :result dst_mcv;
15589	};	16853	};
...	@@ -15781,6 +17045,7 @@ fn airVaStart(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -15781,6 +17045,7 @@ fn airVaStart(self: *Self, inst: Air.Inst.Index) !void {
15781	field_off,	17045	field_off,
15782	Type.c_uint,	17046	Type.c_uint,
15783	.{ .immediate = info.gp_count * 8 },	17047	.{ .immediate = info.gp_count * 8 },
		17048	.{},
15784	);	17049	);
15785	field_off += @intCast(Type.c_uint.abiSize(mod));	17050	field_off += @intCast(Type.c_uint.abiSize(mod));
15786	// fp_offset: c_uint,	17051	// fp_offset: c_uint,
...	@@ -15789,6 +17054,7 @@ fn airVaStart(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -15789,6 +17054,7 @@ fn airVaStart(self: *Self, inst: Air.Inst.Index) !void {
15789	field_off,	17054	field_off,
15790	Type.c_uint,	17055	Type.c_uint,
15791	.{ .immediate = abi.SysV.c_abi_int_param_regs.len * 8 + info.fp_count * 16 },	17056	.{ .immediate = abi.SysV.c_abi_int_param_regs.len * 8 + info.fp_count * 16 },
		17057	.{},
15792	);	17058	);
15793	field_off += @intCast(Type.c_uint.abiSize(mod));	17059	field_off += @intCast(Type.c_uint.abiSize(mod));
15794	// overflow_arg_area: *anyopaque,	17060	// overflow_arg_area: *anyopaque,
...	@@ -15797,6 +17063,7 @@ fn airVaStart(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -15797,6 +17063,7 @@ fn airVaStart(self: *Self, inst: Air.Inst.Index) !void {
15797	field_off,	17063	field_off,
15798	ptr_anyopaque_ty,	17064	ptr_anyopaque_ty,
15799	.{ .lea_frame = info.overflow_arg_area },	17065	.{ .lea_frame = info.overflow_arg_area },
		17066	.{},
15800	);	17067	);
15801	field_off += @intCast(ptr_anyopaque_ty.abiSize(mod));	17068	field_off += @intCast(ptr_anyopaque_ty.abiSize(mod));
15802	// reg_save_area: *anyopaque,	17069	// reg_save_area: *anyopaque,
...	@@ -15805,6 +17072,7 @@ fn airVaStart(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -15805,6 +17072,7 @@ fn airVaStart(self: *Self, inst: Air.Inst.Index) !void {
15805	field_off,	17072	field_off,
15806	ptr_anyopaque_ty,	17073	ptr_anyopaque_ty,
15807	.{ .lea_frame = info.reg_save_area },	17074	.{ .lea_frame = info.reg_save_area },
		17075	.{},
15808	);	17076	);
15809	field_off += @intCast(ptr_anyopaque_ty.abiSize(mod));	17077	field_off += @intCast(ptr_anyopaque_ty.abiSize(mod));
15810	break :result .{ .load_frame = .{ .index = dst_fi } };	17078	break :result .{ .load_frame = .{ .index = dst_fi } };
...	@@ -15831,7 +17099,7 @@ fn airVaArg(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -15831,7 +17099,7 @@ fn airVaArg(self: *Self, inst: Air.Inst.Index) !void {
15831	try self.spillEflagsIfOccupied();	17099	try self.spillEflagsIfOccupied();
15832		17100
15833	const tmp_regs =	17101	const tmp_regs =
15834	try self.register_manager.allocRegs(2, .{ null, null }, abi.RegisterClass.gp);	17102	try self.register_manager.allocRegs(2, .{null} ** 2, abi.RegisterClass.gp);
15835	const offset_reg = tmp_regs[0].to32();	17103	const offset_reg = tmp_regs[0].to32();
15836	const addr_reg = tmp_regs[1].to64();	17104	const addr_reg = tmp_regs[1].to64();
15837	const tmp_locks = self.register_manager.lockRegsAssumeUnused(2, tmp_regs);	17105	const tmp_locks = self.register_manager.lockRegsAssumeUnused(2, tmp_regs);
...	@@ -15859,13 +17127,13 @@ fn airVaArg(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -15859,13 +17127,13 @@ fn airVaArg(self: *Self, inst: Air.Inst.Index) !void {
15859	.integer => {	17127	.integer => {
15860	assert(classes.len == 1);	17128	assert(classes.len == 1);
15861		17129
15862	try self.genSetReg(offset_reg, Type.c_uint, gp_offset);	17130	try self.genSetReg(offset_reg, Type.c_uint, gp_offset, .{});
15863	try self.asmRegisterImmediate(.{ ._, .cmp }, offset_reg, Immediate.u(	17131	try self.asmRegisterImmediate(.{ ._, .cmp }, offset_reg, Immediate.u(
15864	abi.SysV.c_abi_int_param_regs.len * 8,	17132	abi.SysV.c_abi_int_param_regs.len * 8,
15865	));	17133	));
15866	const mem_reloc = try self.asmJccReloc(.ae, undefined);	17134	const mem_reloc = try self.asmJccReloc(.ae, undefined);
15867		17135
15868	try self.genSetReg(addr_reg, ptr_anyopaque_ty, reg_save_area);	17136	try self.genSetReg(addr_reg, ptr_anyopaque_ty, reg_save_area, .{});
15869	if (!unused) try self.asmRegisterMemory(.{ ._, .lea }, addr_reg, .{	17137	if (!unused) try self.asmRegisterMemory(.{ ._, .lea }, addr_reg, .{
15870	.base = .{ .reg = addr_reg },	17138	.base = .{ .reg = addr_reg },
15871	.mod = .{ .rm = .{	17139	.mod = .{ .rm = .{
...	@@ -15880,11 +17148,11 @@ fn airVaArg(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -15880,11 +17148,11 @@ fn airVaArg(self: *Self, inst: Air.Inst.Index) !void {
15880	.disp = 8,	17148	.disp = 8,
15881	} },	17149	} },
15882	});	17150	});
15883	try self.genCopy(Type.c_uint, gp_offset, .{ .register = offset_reg });	17151	try self.genCopy(Type.c_uint, gp_offset, .{ .register = offset_reg }, .{});
15884	const done_reloc = try self.asmJmpReloc(undefined);	17152	const done_reloc = try self.asmJmpReloc(undefined);
15885		17153
15886	try self.performReloc(mem_reloc);	17154	self.performReloc(mem_reloc);
15887	try self.genSetReg(addr_reg, ptr_anyopaque_ty, overflow_arg_area);	17155	try self.genSetReg(addr_reg, ptr_anyopaque_ty, overflow_arg_area, .{});
15888	try self.asmRegisterMemory(.{ ._, .lea }, offset_reg.to64(), .{	17156	try self.asmRegisterMemory(.{ ._, .lea }, offset_reg.to64(), .{
15889	.base = .{ .reg = addr_reg },	17157	.base = .{ .reg = addr_reg },
15890	.mod = .{ .rm = .{	17158	.mod = .{ .rm = .{
...	@@ -15896,23 +17164,24 @@ fn airVaArg(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -15896,23 +17164,24 @@ fn airVaArg(self: *Self, inst: Air.Inst.Index) !void {
15896	ptr_anyopaque_ty,	17164	ptr_anyopaque_ty,
15897	overflow_arg_area,	17165	overflow_arg_area,
15898	.{ .register = offset_reg.to64() },	17166	.{ .register = offset_reg.to64() },
		17167	.{},
15899	);	17168	);
15900		17169
15901	try self.performReloc(done_reloc);	17170	self.performReloc(done_reloc);
15902	if (!unused) try self.genCopy(promote_ty, promote_mcv, .{	17171	if (!unused) try self.genCopy(promote_ty, promote_mcv, .{
15903	.indirect = .{ .reg = addr_reg },	17172	.indirect = .{ .reg = addr_reg },
15904	});	17173	}, .{});
15905	},	17174	},
15906	.sse => {	17175	.sse => {
15907	assert(classes.len == 1);	17176	assert(classes.len == 1);
15908		17177
15909	try self.genSetReg(offset_reg, Type.c_uint, fp_offset);	17178	try self.genSetReg(offset_reg, Type.c_uint, fp_offset, .{});
15910	try self.asmRegisterImmediate(.{ ._, .cmp }, offset_reg, Immediate.u(	17179	try self.asmRegisterImmediate(.{ ._, .cmp }, offset_reg, Immediate.u(
15911	abi.SysV.c_abi_int_param_regs.len * 8 + abi.SysV.c_abi_sse_param_regs.len * 16,	17180	abi.SysV.c_abi_int_param_regs.len * 8 + abi.SysV.c_abi_sse_param_regs.len * 16,
15912	));	17181	));
15913	const mem_reloc = try self.asmJccReloc(.ae, undefined);	17182	const mem_reloc = try self.asmJccReloc(.ae, undefined);
15914		17183
15915	try self.genSetReg(addr_reg, ptr_anyopaque_ty, reg_save_area);	17184	try self.genSetReg(addr_reg, ptr_anyopaque_ty, reg_save_area, .{});
15916	if (!unused) try self.asmRegisterMemory(.{ ._, .lea }, addr_reg, .{	17185	if (!unused) try self.asmRegisterMemory(.{ ._, .lea }, addr_reg, .{
15917	.base = .{ .reg = addr_reg },	17186	.base = .{ .reg = addr_reg },
15918	.mod = .{ .rm = .{	17187	.mod = .{ .rm = .{
...	@@ -15927,11 +17196,11 @@ fn airVaArg(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -15927,11 +17196,11 @@ fn airVaArg(self: *Self, inst: Air.Inst.Index) !void {
15927	.disp = 16,	17196	.disp = 16,
15928	} },	17197	} },
15929	});	17198	});
15930	try self.genCopy(Type.c_uint, fp_offset, .{ .register = offset_reg });	17199	try self.genCopy(Type.c_uint, fp_offset, .{ .register = offset_reg }, .{});
15931	const done_reloc = try self.asmJmpReloc(undefined);	17200	const done_reloc = try self.asmJmpReloc(undefined);
15932		17201
15933	try self.performReloc(mem_reloc);	17202	self.performReloc(mem_reloc);
15934	try self.genSetReg(addr_reg, ptr_anyopaque_ty, overflow_arg_area);	17203	try self.genSetReg(addr_reg, ptr_anyopaque_ty, overflow_arg_area, .{});
15935	try self.asmRegisterMemory(.{ ._, .lea }, offset_reg.to64(), .{	17204	try self.asmRegisterMemory(.{ ._, .lea }, offset_reg.to64(), .{
15936	.base = .{ .reg = addr_reg },	17205	.base = .{ .reg = addr_reg },
15937	.mod = .{ .rm = .{	17206	.mod = .{ .rm = .{
...	@@ -15943,12 +17212,13 @@ fn airVaArg(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -15943,12 +17212,13 @@ fn airVaArg(self: *Self, inst: Air.Inst.Index) !void {
15943	ptr_anyopaque_ty,	17212	ptr_anyopaque_ty,
15944	overflow_arg_area,	17213	overflow_arg_area,
15945	.{ .register = offset_reg.to64() },	17214	.{ .register = offset_reg.to64() },
		17215	.{},
15946	);	17216	);
15947		17217
15948	try self.performReloc(done_reloc);	17218	self.performReloc(done_reloc);
15949	if (!unused) try self.genCopy(promote_ty, promote_mcv, .{	17219	if (!unused) try self.genCopy(promote_ty, promote_mcv, .{
15950	.indirect = .{ .reg = addr_reg },	17220	.indirect = .{ .reg = addr_reg },
15951	});	17221	}, .{});
15952	},	17222	},
15953	.memory => {	17223	.memory => {
15954	assert(classes.len == 1);	17224	assert(classes.len == 1);
...	@@ -15964,7 +17234,7 @@ fn airVaArg(self: *Self, inst: Air.Inst.Index) !void {	...	@@ -15964,7 +17234,7 @@ fn airVaArg(self: *Self, inst: Air.Inst.Index) !void {
15964		17234
15965	if (!promote_ty.isRuntimeFloat()) {	17235	if (!promote_ty.isRuntimeFloat()) {
15966	const dst_mcv = try self.allocRegOrMem(inst, true);	17236	const dst_mcv = try self.allocRegOrMem(inst, true);
15967	try self.genCopy(ty, dst_mcv, promote_mcv);	17237	try self.genCopy(ty, dst_mcv, promote_mcv, .{});
15968	break :result dst_mcv;	17238	break :result dst_mcv;
15969	}	17239	}
15970		17240
...	@@ -16055,6 +17325,7 @@ fn resolveInst(self: *Self, ref: Air.Inst.Ref) InnerError!MCValue {	...	@@ -16055,6 +17325,7 @@ fn resolveInst(self: *Self, ref: Air.Inst.Ref) InnerError!MCValue {
16055	0,	17325	0,
16056	Type.usize,	17326	Type.usize,
16057	.{ .lea_symbol = .{ .sym = tlv_sym } },	17327	.{ .lea_symbol = .{ .sym = tlv_sym } },
		17328	.{},
16058	);	17329	);
16059	break :init .{ .load_frame = .{ .index = frame_index } };	17330	break :init .{ .load_frame = .{ .index = frame_index } };
16060	},	17331	},
...	@@ -16249,7 +17520,7 @@ fn resolveCallingConventionValues(	...	@@ -16249,7 +17520,7 @@ fn resolveCallingConventionValues(
16249	};	17520	};
16250	ret_tracking_i += 1;	17521	ret_tracking_i += 1;
16251	},	17522	},
16252	.none => unreachable,	17523	.none, .integer_per_element => unreachable,
16253	};	17524	};
16254	result.return_value = switch (ret_tracking_i) {	17525	result.return_value = switch (ret_tracking_i) {
16255	else => unreachable,	17526	else => unreachable,
...	@@ -16324,6 +17595,32 @@ fn resolveCallingConventionValues(	...	@@ -16324,6 +17595,32 @@ fn resolveCallingConventionValues(
16324	else => unreachable,	17595	else => unreachable,
16325	},	17596	},
16326	.none => unreachable,	17597	.none => unreachable,
		17598	.integer_per_element => {
		17599	const param_int_regs_len: u32 =
		17600	@intCast(abi.getCAbiIntParamRegs(resolved_cc).len);
		17601	const remaining_param_int_regs: u3 =
		17602	@intCast(param_int_regs_len - param_int_reg_i);
		17603	param_int_reg_i = param_int_regs_len;
		17604
		17605	const frame_elem_align = 8;
		17606	const frame_elems_len = ty.vectorLen(mod) - remaining_param_int_regs;
		17607	const frame_elem_size = mem.alignForward(
		17608	u64,
		17609	ty.childType(mod).abiSize(mod),
		17610	frame_elem_align,
		17611	);
		17612	const frame_size: u31 = @intCast(frame_elems_len * frame_elem_size);
		17613
		17614	result.stack_byte_count =
		17615	mem.alignForward(u31, result.stack_byte_count, frame_elem_align);
		17616	arg_mcv[arg_mcv_i] = .{ .elementwise_regs_then_frame = .{
		17617	.regs = remaining_param_int_regs,
		17618	.frame_off = @intCast(result.stack_byte_count),
		17619	.frame_index = stack_frame_base,
		17620	} };
		17621	arg_mcv_i += 1;
		17622	result.stack_byte_count += frame_size;
		17623	},
16327	} else {	17624	} else {
16328	arg.* = switch (arg_mcv_i) {	17625	arg.* = switch (arg_mcv_i) {
16329	else => unreachable,	17626	else => unreachable,
...	@@ -16506,12 +17803,14 @@ fn truncateRegister(self: *Self, ty: Type, reg: Register) !void {	...	@@ -16506,12 +17803,14 @@ fn truncateRegister(self: *Self, ty: Type, reg: Register) !void {
16506	.{ ._l, .sa },	17803	.{ ._l, .sa },
16507	Type.isize,	17804	Type.isize,
16508	.{ .register = reg },	17805	.{ .register = reg },
		17806	Type.u8,
16509	.{ .immediate = shift },	17807	.{ .immediate = shift },
16510	);	17808	);
16511	try self.genShiftBinOpMir(	17809	try self.genShiftBinOpMir(
16512	.{ ._r, .sa },	17810	.{ ._r, .sa },
16513	Type.isize,	17811	Type.isize,
16514	.{ .register = reg },	17812	.{ .register = reg },
		17813	Type.u8,
16515	.{ .immediate = shift },	17814	.{ .immediate = shift },
16516	);	17815	);
16517	},	17816	},

src/arch/x86_64/Encoding.zig+1-2

...	@@ -232,8 +232,7 @@ pub const Mnemonic = enum {	...	@@ -232,8 +232,7 @@ pub const Mnemonic = enum {
232	cmps, cmpsb, cmpsd, cmpsq, cmpsw,	232	cmps, cmpsb, cmpsd, cmpsq, cmpsw,
233	cmpxchg, cmpxchg8b, cmpxchg16b,	233	cmpxchg, cmpxchg8b, cmpxchg16b,
234	cpuid, cqo, cwd, cwde,	234	cpuid, cqo, cwd, cwde,
235	div,	235	dec, div, idiv, imul, inc, int3,
236	idiv, imul, int3,
237	ja, jae, jb, jbe, jc, jrcxz, je, jg, jge, jl, jle, jna, jnae, jnb, jnbe,	236	ja, jae, jb, jbe, jc, jrcxz, je, jg, jge, jl, jle, jna, jnae, jnb, jnbe,
238	jnc, jne, jng, jnge, jnl, jnle, jno, jnp, jns, jnz, jo, jp, jpe, jpo, js, jz,	237	jnc, jne, jng, jnge, jnl, jnle, jno, jnp, jns, jnz, jo, jp, jpe, jpo, js, jz,
239	jmp,	238	jmp,

src/arch/x86_64/Mir.zig+5-1

...	@@ -325,6 +325,8 @@ pub const Inst = struct {	...	@@ -325,6 +325,8 @@ pub const Inst = struct {
325	cwd,	325	cwd,
326	/// Convert word to doubleword	326	/// Convert word to doubleword
327	cwde,	327	cwde,
		328	/// Decrement by 1
		329	dec,
328	/// Unsigned division	330	/// Unsigned division
329	/// Signed division	331	/// Signed division
330	/// Divide packed single-precision floating-point values	332	/// Divide packed single-precision floating-point values
...	@@ -332,7 +334,9 @@ pub const Inst = struct {	...	@@ -332,7 +334,9 @@ pub const Inst = struct {
332	/// Divide packed double-precision floating-point values	334	/// Divide packed double-precision floating-point values
333	/// Divide scalar double-precision floating-point values	335	/// Divide scalar double-precision floating-point values
334	div,	336	div,
335	///	337	/// Increment by 1
		338	inc,
		339	/// Call to interrupt procedure
336	int3,	340	int3,
337	/// Conditional jump	341	/// Conditional jump
338	j,	342	j,

src/arch/x86_64/abi.zig+26

...	@@ -10,6 +10,7 @@ pub const Class = enum {	...	@@ -10,6 +10,7 @@ pub const Class = enum {
10	win_i128,	10	win_i128,
11	float,	11	float,
12	float_combine,	12	float_combine,
		13	integer_per_element,
13	};	14	};
14		15
15	pub fn classifyWindows(ty: Type, mod: *Module) Class {	16	pub fn classifyWindows(ty: Type, mod: *Module) Class {
...	@@ -161,6 +162,31 @@ pub fn classifySystemV(ty: Type, mod: *Module, ctx: Context) [8]Class {	...	@@ -161,6 +162,31 @@ pub fn classifySystemV(ty: Type, mod: *Module, ctx: Context) [8]Class {
161	.Vector => {	162	.Vector => {
162	const elem_ty = ty.childType(mod);	163	const elem_ty = ty.childType(mod);
163	const bits = elem_ty.bitSize(mod) * ty.arrayLen(mod);	164	const bits = elem_ty.bitSize(mod) * ty.arrayLen(mod);
		165	if (elem_ty.toIntern() == .bool_type) {
		166	if (bits <= 32) return .{
		167	.integer, .none, .none, .none,
		168	.none, .none, .none, .none,
		169	};
		170	if (bits <= 64) return .{
		171	.sse, .none, .none, .none,
		172	.none, .none, .none, .none,
		173	};
		174	if (ctx == .arg) {
		175	if (bits <= 128) return .{
		176	.integer_per_element, .none, .none, .none,
		177	.none, .none, .none, .none,
		178	};
		179	if (bits <= 256 and std.Target.x86.featureSetHas(target.cpu.features, .avx)) return .{
		180	.integer_per_element, .none, .none, .none,
		181	.none, .none, .none, .none,
		182	};
		183	if (bits <= 512 and std.Target.x86.featureSetHas(target.cpu.features, .avx512f)) return .{
		184	.integer_per_element, .none, .none, .none,
		185	.none, .none, .none, .none,
		186	};
		187	}
		188	return memory_class;
		189	}
164	if (bits <= 64) return .{	190	if (bits <= 64) return .{
165	.sse, .none, .none, .none,	191	.sse, .none, .none, .none,
166	.none, .none, .none, .none,	192	.none, .none, .none, .none,

src/arch/x86_64/encodings.zig+12

...	@@ -269,6 +269,12 @@ pub const table = [_]Entry{	...	@@ -269,6 +269,12 @@ pub const table = [_]Entry{
269		269
270	.{ .cpuid, .zo, &.{}, &.{ 0x0f, 0xa2 }, 0, .none, .none },	270	.{ .cpuid, .zo, &.{}, &.{ 0x0f, 0xa2 }, 0, .none, .none },
271		271
		272	.{ .dec, .m, &.{ .rm8 }, &.{ 0xfe }, 1, .none, .none },
		273	.{ .dec, .m, &.{ .rm8 }, &.{ 0xfe }, 1, .rex, .none },
		274	.{ .dec, .m, &.{ .rm16 }, &.{ 0xff }, 1, .short, .none },
		275	.{ .dec, .m, &.{ .rm32 }, &.{ 0xff }, 1, .none, .none },
		276	.{ .dec, .m, &.{ .rm64 }, &.{ 0xff }, 1, .long, .none },
		277
272	.{ .div, .m, &.{ .rm8 }, &.{ 0xf6 }, 6, .none, .none },	278	.{ .div, .m, &.{ .rm8 }, &.{ 0xf6 }, 6, .none, .none },
273	.{ .div, .m, &.{ .rm8 }, &.{ 0xf6 }, 6, .rex, .none },	279	.{ .div, .m, &.{ .rm8 }, &.{ 0xf6 }, 6, .rex, .none },
274	.{ .div, .m, &.{ .rm16 }, &.{ 0xf7 }, 6, .short, .none },	280	.{ .div, .m, &.{ .rm16 }, &.{ 0xf7 }, 6, .short, .none },
...	@@ -296,6 +302,12 @@ pub const table = [_]Entry{	...	@@ -296,6 +302,12 @@ pub const table = [_]Entry{
296	.{ .imul, .rmi, &.{ .r32, .rm32, .imm32 }, &.{ 0x69 }, 0, .none, .none },	302	.{ .imul, .rmi, &.{ .r32, .rm32, .imm32 }, &.{ 0x69 }, 0, .none, .none },
297	.{ .imul, .rmi, &.{ .r64, .rm64, .imm32 }, &.{ 0x69 }, 0, .long, .none },	303	.{ .imul, .rmi, &.{ .r64, .rm64, .imm32 }, &.{ 0x69 }, 0, .long, .none },
298		304
		305	.{ .inc, .m, &.{ .rm8 }, &.{ 0xfe }, 0, .none, .none },
		306	.{ .inc, .m, &.{ .rm8 }, &.{ 0xfe }, 0, .rex, .none },
		307	.{ .inc, .m, &.{ .rm16 }, &.{ 0xff }, 0, .short, .none },
		308	.{ .inc, .m, &.{ .rm32 }, &.{ 0xff }, 0, .none, .none },
		309	.{ .inc, .m, &.{ .rm64 }, &.{ 0xff }, 0, .long, .none },
		310
299	.{ .int3, .zo, &.{}, &.{ 0xcc }, 0, .none, .none },	311	.{ .int3, .zo, &.{}, &.{ 0xcc }, 0, .none, .none },
300		312
301	.{ .ja, .d, &.{ .rel32 }, &.{ 0x0f, 0x87 }, 0, .none, .none },	313	.{ .ja, .d, &.{ .rel32 }, &.{ 0x0f, 0x87 }, 0, .none, .none },

src/codegen/llvm.zig+6

 @@ -11139,6 +11139,9 @@ fn lowerSystemVFnRetTy(o: *Object, fn_info: InternPool.Key.FuncType) Allocator.E
             .memory => unreachable, // handled above
             .win_i128 => unreachable, // windows only
             .none => break,
+            .integer_per_element => {
+                @panic("TODO");
+            },
         }
     }
     const first_non_integer = std.mem.indexOfNone(x86_64_abi.Class, &classes, &.{.integer});
 @@ -11417,6 +11420,9 @@ const ParamTypeIterator = struct {
                 .memory => unreachable, // handled above
                 .win_i128 => unreachable, // windows only
                 .none => break,
+                .integer_per_element => {
+                    @panic("TODO");
+                },
             }
         }
         const first_non_integer = std.mem.indexOfNone(x86_64_abi.Class, &classes, &.{.integer});

test/behavior/math.zig+34

...	@@ -1059,6 +1059,40 @@ test "@mulWithOverflow bitsize > 32" {	...	@@ -1059,6 +1059,40 @@ test "@mulWithOverflow bitsize > 32" {
1059	}	1059	}
1060	}	1060	}
1061		1061
		1062	test "@mulWithOverflow u256" {
		1063	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
		1064	if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest;
		1065
		1066	{
		1067	const const_lhs: u256 = 8035709466408580321693645878924206181189;
		1068	const const_rhs: u256 = 343954217539185679456797259115612849079;
		1069	const const_result = @mulWithOverflow(const_lhs, const_rhs);
		1070	comptime assert(const_result[0] == 100698109432518020450541558444080472799095368135495022414802684874680804056403);
		1071	comptime assert(const_result[1] == 1);
		1072
		1073	var var_lhs = const_lhs;
		1074	var var_rhs = const_rhs;
		1075	_ = .{ &var_lhs, &var_rhs };
		1076	const var_result = @mulWithOverflow(var_lhs, var_rhs);
		1077	try std.testing.expect(var_result[0] == const_result[0]);
		1078	try std.testing.expect(var_result[1] == const_result[1]);
		1079	}
		1080	{
		1081	const const_lhs: u256 = 100477140835310762407466294984162740292250605075409128262608;
		1082	const const_rhs: u256 = 406310585934439581231;
		1083	const const_result = @mulWithOverflow(const_lhs, const_rhs);
		1084	comptime assert(const_result[0] == 66110554277021146912650321519727251744526528332039438002889524600764482652976);
		1085	comptime assert(const_result[1] == 1);
		1086
		1087	var var_lhs = const_lhs;
		1088	var var_rhs = const_rhs;
		1089	_ = .{ &var_lhs, &var_rhs };
		1090	const var_result = @mulWithOverflow(var_lhs, var_rhs);
		1091	try std.testing.expect(var_result[0] == const_result[0]);
		1092	try std.testing.expect(var_result[1] == const_result[1]);
		1093	}
		1094	}
		1095
1062	test "@subWithOverflow" {	1096	test "@subWithOverflow" {
1063	if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO	1097	if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
1064	if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO	1098	if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO

test/behavior/packed-struct.zig-4

 @@ -1130,10 +1130,6 @@ test "pointer loaded correctly from packed struct" {
     if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
     if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest;
     if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
-    if (builtin.zig_backend == .stage2_x86_64) {
-        // Careful enabling this test, fails randomly.
-        return error.SkipZigTest;
-    }
     var ram = try RAM.new();
     var cpu = try CPU.new(&ram);

test/behavior/undefined.zig-1

...	@@ -99,7 +99,6 @@ test "reslice of undefined global var slice" {	...	@@ -99,7 +99,6 @@ test "reslice of undefined global var slice" {
99	}	99	}
100		100
101	test "returned undef is 0xaa bytes when runtime safety is enabled" {	101	test "returned undef is 0xaa bytes when runtime safety is enabled" {
102	if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
103	if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO	102	if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
104	if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO	103	if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
105	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO	104	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO

test/behavior/vector.zig-1

...	@@ -485,7 +485,6 @@ test "initialize vector which is a struct field" {	...	@@ -485,7 +485,6 @@ test "initialize vector which is a struct field" {
485		485
486	test "vector comparison operators" {	486	test "vector comparison operators" {
487	if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO	487	if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
488	if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
489	if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO	488	if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
490	if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO	489	if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
491	if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO	490	if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO

test/c_abi/cfuncs.c+4251

...	@@ -236,6 +236,2156 @@ struct SplitStructMixed zig_ret_split_struct_mixed();	...	@@ -236,6 +236,2156 @@ struct SplitStructMixed zig_ret_split_struct_mixed();
236		236
237	struct BigStruct zig_big_struct_both(struct BigStruct);	237	struct BigStruct zig_big_struct_both(struct BigStruct);
238		238
		239	#if defined(ZIG_BACKEND_STAGE2_X86_64) \|\| defined(ZIG_PPC32)
		240
		241	typedef bool Vector2Bool __attribute__((ext_vector_type(2)));
		242	typedef bool Vector4Bool __attribute__((ext_vector_type(4)));
		243	typedef bool Vector8Bool __attribute__((ext_vector_type(8)));
		244	typedef bool Vector16Bool __attribute__((ext_vector_type(16)));
		245	typedef bool Vector32Bool __attribute__((ext_vector_type(32)));
		246	typedef bool Vector64Bool __attribute__((ext_vector_type(64)));
		247	typedef bool Vector128Bool __attribute__((ext_vector_type(128)));
		248	typedef bool Vector256Bool __attribute__((ext_vector_type(256)));
		249	typedef bool Vector512Bool __attribute__((ext_vector_type(512)));
		250
		251	void c_vector_2_bool(Vector2Bool vec) {
		252	assert_or_panic(vec[0] == true);
		253	assert_or_panic(vec[1] == true);
		254	}
		255
		256	void c_vector_4_bool(Vector4Bool vec) {
		257	assert_or_panic(vec[0] == true);
		258	assert_or_panic(vec[1] == true);
		259	assert_or_panic(vec[2] == false);
		260	assert_or_panic(vec[3] == true);
		261	}
		262
		263	void c_vector_8_bool(Vector8Bool vec) {
		264	assert_or_panic(vec[0] == true);
		265	assert_or_panic(vec[1] == false);
		266	assert_or_panic(vec[2] == true);
		267	assert_or_panic(vec[3] == true);
		268	assert_or_panic(vec[4] == true);
		269	assert_or_panic(vec[5] == true);
		270	assert_or_panic(vec[6] == false);
		271	assert_or_panic(vec[7] == true);
		272	}
		273
		274	void c_vector_16_bool(Vector16Bool vec) {
		275	assert_or_panic(vec[0] == true);
		276	assert_or_panic(vec[1] == false);
		277	assert_or_panic(vec[2] == false);
		278	assert_or_panic(vec[3] == false);
		279	assert_or_panic(vec[4] == true);
		280	assert_or_panic(vec[5] == false);
		281	assert_or_panic(vec[6] == true);
		282	assert_or_panic(vec[7] == true);
		283	assert_or_panic(vec[8] == true);
		284	assert_or_panic(vec[9] == true);
		285	assert_or_panic(vec[10] == true);
		286	assert_or_panic(vec[11] == true);
		287	assert_or_panic(vec[12] == false);
		288	assert_or_panic(vec[13] == false);
		289	assert_or_panic(vec[14] == false);
		290	assert_or_panic(vec[15] == false);
		291	}
		292
		293	void c_vector_32_bool(Vector32Bool vec) {
		294	assert_or_panic(vec[0] == true);
		295	assert_or_panic(vec[1] == false);
		296	assert_or_panic(vec[2] == true);
		297	assert_or_panic(vec[3] == true);
		298	assert_or_panic(vec[4] == false);
		299	assert_or_panic(vec[5] == false);
		300	assert_or_panic(vec[6] == true);
		301	assert_or_panic(vec[7] == false);
		302	assert_or_panic(vec[8] == true);
		303	assert_or_panic(vec[9] == false);
		304	assert_or_panic(vec[10] == true);
		305	assert_or_panic(vec[11] == true);
		306	assert_or_panic(vec[12] == true);
		307	assert_or_panic(vec[13] == false);
		308	assert_or_panic(vec[14] == false);
		309	assert_or_panic(vec[15] == true);
		310	assert_or_panic(vec[16] == false);
		311	assert_or_panic(vec[17] == true);
		312	assert_or_panic(vec[18] == false);
		313	assert_or_panic(vec[19] == true);
		314	assert_or_panic(vec[20] == true);
		315	assert_or_panic(vec[21] == true);
		316	assert_or_panic(vec[22] == true);
		317	assert_or_panic(vec[23] == true);
		318	assert_or_panic(vec[24] == false);
		319	assert_or_panic(vec[25] == true);
		320	assert_or_panic(vec[26] == true);
		321	assert_or_panic(vec[27] == true);
		322	assert_or_panic(vec[28] == false);
		323	assert_or_panic(vec[29] == true);
		324	assert_or_panic(vec[30] == true);
		325	assert_or_panic(vec[31] == false);
		326	}
		327
		328	void c_vector_64_bool(Vector64Bool vec) {
		329	assert_or_panic(vec[0] == true);
		330	assert_or_panic(vec[1] == true);
		331	assert_or_panic(vec[2] == true);
		332	assert_or_panic(vec[3] == false);
		333	assert_or_panic(vec[4] == true);
		334	assert_or_panic(vec[5] == false);
		335	assert_or_panic(vec[6] == false);
		336	assert_or_panic(vec[7] == false);
		337	assert_or_panic(vec[8] == true);
		338	assert_or_panic(vec[9] == false);
		339	assert_or_panic(vec[10] == false);
		340	assert_or_panic(vec[11] == false);
		341	assert_or_panic(vec[12] == false);
		342	assert_or_panic(vec[13] == true);
		343	assert_or_panic(vec[14] == true);
		344	assert_or_panic(vec[15] == true);
		345	assert_or_panic(vec[16] == true);
		346	assert_or_panic(vec[17] == false);
		347	assert_or_panic(vec[18] == false);
		348	assert_or_panic(vec[19] == true);
		349	assert_or_panic(vec[20] == false);
		350	assert_or_panic(vec[21] == true);
		351	assert_or_panic(vec[22] == false);
		352	assert_or_panic(vec[23] == true);
		353	assert_or_panic(vec[24] == true);
		354	assert_or_panic(vec[25] == true);
		355	assert_or_panic(vec[26] == true);
		356	assert_or_panic(vec[27] == true);
		357	assert_or_panic(vec[28] == true);
		358	assert_or_panic(vec[29] == true);
		359	assert_or_panic(vec[30] == false);
		360	assert_or_panic(vec[31] == false);
		361	assert_or_panic(vec[32] == true);
		362	assert_or_panic(vec[33] == true);
		363	assert_or_panic(vec[34] == false);
		364	assert_or_panic(vec[35] == true);
		365	assert_or_panic(vec[36] == false);
		366	assert_or_panic(vec[37] == false);
		367	assert_or_panic(vec[38] == true);
		368	assert_or_panic(vec[39] == true);
		369	assert_or_panic(vec[40] == true);
		370	assert_or_panic(vec[41] == false);
		371	assert_or_panic(vec[42] == false);
		372	assert_or_panic(vec[43] == true);
		373	assert_or_panic(vec[44] == true);
		374	assert_or_panic(vec[45] == false);
		375	assert_or_panic(vec[46] == true);
		376	assert_or_panic(vec[47] == false);
		377	assert_or_panic(vec[48] == true);
		378	assert_or_panic(vec[49] == false);
		379	assert_or_panic(vec[50] == false);
		380	assert_or_panic(vec[51] == true);
		381	assert_or_panic(vec[52] == false);
		382	assert_or_panic(vec[53] == true);
		383	assert_or_panic(vec[54] == true);
		384	assert_or_panic(vec[55] == true);
		385	assert_or_panic(vec[56] == true);
		386	assert_or_panic(vec[57] == true);
		387	assert_or_panic(vec[58] == false);
		388	assert_or_panic(vec[59] == false);
		389	assert_or_panic(vec[60] == true);
		390	assert_or_panic(vec[61] == false);
		391	assert_or_panic(vec[62] == true);
		392	assert_or_panic(vec[63] == false);
		393	}
		394
		395	void c_vector_128_bool(Vector128Bool vec) {
		396	assert_or_panic(vec[0] == false);
		397	assert_or_panic(vec[1] == false);
		398	assert_or_panic(vec[2] == false);
		399	assert_or_panic(vec[3] == false);
		400	assert_or_panic(vec[4] == false);
		401	assert_or_panic(vec[5] == true);
		402	assert_or_panic(vec[6] == true);
		403	assert_or_panic(vec[7] == false);
		404	assert_or_panic(vec[8] == true);
		405	assert_or_panic(vec[9] == true);
		406	assert_or_panic(vec[10] == false);
		407	assert_or_panic(vec[11] == true);
		408	assert_or_panic(vec[12] == true);
		409	assert_or_panic(vec[13] == false);
		410	assert_or_panic(vec[14] == true);
		411	assert_or_panic(vec[15] == true);
		412	assert_or_panic(vec[16] == true);
		413	assert_or_panic(vec[17] == false);
		414	assert_or_panic(vec[18] == false);
		415	assert_or_panic(vec[19] == false);
		416	assert_or_panic(vec[20] == false);
		417	assert_or_panic(vec[21] == true);
		418	assert_or_panic(vec[22] == true);
		419	assert_or_panic(vec[23] == false);
		420	assert_or_panic(vec[24] == false);
		421	assert_or_panic(vec[25] == false);
		422	assert_or_panic(vec[26] == true);
		423	assert_or_panic(vec[27] == true);
		424	assert_or_panic(vec[28] == false);
		425	assert_or_panic(vec[29] == true);
		426	assert_or_panic(vec[30] == false);
		427	assert_or_panic(vec[31] == false);
		428	assert_or_panic(vec[32] == true);
		429	assert_or_panic(vec[33] == false);
		430	assert_or_panic(vec[34] == false);
		431	assert_or_panic(vec[35] == true);
		432	assert_or_panic(vec[36] == true);
		433	assert_or_panic(vec[37] == true);
		434	assert_or_panic(vec[38] == true);
		435	assert_or_panic(vec[39] == true);
		436	assert_or_panic(vec[40] == false);
		437	assert_or_panic(vec[41] == true);
		438	assert_or_panic(vec[42] == true);
		439	assert_or_panic(vec[43] == true);
		440	assert_or_panic(vec[44] == false);
		441	assert_or_panic(vec[45] == false);
		442	assert_or_panic(vec[46] == false);
		443	assert_or_panic(vec[47] == false);
		444	assert_or_panic(vec[48] == true);
		445	assert_or_panic(vec[49] == true);
		446	assert_or_panic(vec[50] == false);
		447	assert_or_panic(vec[51] == true);
		448	assert_or_panic(vec[52] == true);
		449	assert_or_panic(vec[53] == true);
		450	assert_or_panic(vec[54] == true);
		451	assert_or_panic(vec[55] == true);
		452	assert_or_panic(vec[56] == false);
		453	assert_or_panic(vec[57] == true);
		454	assert_or_panic(vec[58] == true);
		455	assert_or_panic(vec[59] == false);
		456	assert_or_panic(vec[60] == true);
		457	assert_or_panic(vec[61] == false);
		458	assert_or_panic(vec[62] == false);
		459	assert_or_panic(vec[63] == true);
		460	assert_or_panic(vec[64] == true);
		461	assert_or_panic(vec[65] == false);
		462	assert_or_panic(vec[66] == true);
		463	assert_or_panic(vec[67] == true);
		464	assert_or_panic(vec[68] == false);
		465	assert_or_panic(vec[69] == true);
		466	assert_or_panic(vec[70] == false);
		467	assert_or_panic(vec[71] == false);
		468	assert_or_panic(vec[72] == true);
		469	assert_or_panic(vec[73] == true);
		470	assert_or_panic(vec[74] == false);
		471	assert_or_panic(vec[75] == true);
		472	assert_or_panic(vec[76] == true);
		473	assert_or_panic(vec[77] == true);
		474	assert_or_panic(vec[78] == false);
		475	assert_or_panic(vec[79] == true);
		476	assert_or_panic(vec[80] == false);
		477	assert_or_panic(vec[81] == false);
		478	assert_or_panic(vec[82] == false);
		479	assert_or_panic(vec[83] == false);
		480	assert_or_panic(vec[84] == true);
		481	assert_or_panic(vec[85] == false);
		482	assert_or_panic(vec[86] == false);
		483	assert_or_panic(vec[87] == false);
		484	assert_or_panic(vec[88] == true);
		485	assert_or_panic(vec[89] == true);
		486	assert_or_panic(vec[90] == false);
		487	assert_or_panic(vec[91] == false);
		488	assert_or_panic(vec[92] == true);
		489	assert_or_panic(vec[93] == true);
		490	assert_or_panic(vec[94] == true);
		491	assert_or_panic(vec[95] == true);
		492	assert_or_panic(vec[96] == false);
		493	assert_or_panic(vec[97] == false);
		494	assert_or_panic(vec[98] == false);
		495	assert_or_panic(vec[99] == false);
		496	assert_or_panic(vec[100] == false);
		497	assert_or_panic(vec[101] == true);
		498	assert_or_panic(vec[102] == false);
		499	assert_or_panic(vec[103] == false);
		500	assert_or_panic(vec[104] == false);
		501	assert_or_panic(vec[105] == false);
		502	assert_or_panic(vec[106] == true);
		503	assert_or_panic(vec[107] == true);
		504	assert_or_panic(vec[108] == true);
		505	assert_or_panic(vec[109] == true);
		506	assert_or_panic(vec[110] == true);
		507	assert_or_panic(vec[111] == false);
		508	assert_or_panic(vec[112] == false);
		509	assert_or_panic(vec[113] == true);
		510	assert_or_panic(vec[114] == false);
		511	assert_or_panic(vec[115] == true);
		512	assert_or_panic(vec[116] == false);
		513	assert_or_panic(vec[117] == false);
		514	assert_or_panic(vec[118] == true);
		515	assert_or_panic(vec[119] == false);
		516	assert_or_panic(vec[120] == true);
		517	assert_or_panic(vec[121] == false);
		518	assert_or_panic(vec[122] == true);
		519	assert_or_panic(vec[123] == true);
		520	assert_or_panic(vec[124] == true);
		521	assert_or_panic(vec[125] == true);
		522	assert_or_panic(vec[126] == true);
		523	assert_or_panic(vec[127] == true);
		524	}
		525
		526	void c_vector_256_bool(Vector256Bool vec) {
		527	assert_or_panic(vec[0] == false);
		528	assert_or_panic(vec[1] == true);
		529	assert_or_panic(vec[2] == true);
		530	assert_or_panic(vec[3] == false);
		531	assert_or_panic(vec[4] == false);
		532	assert_or_panic(vec[5] == true);
		533	assert_or_panic(vec[6] == true);
		534	assert_or_panic(vec[7] == true);
		535	assert_or_panic(vec[8] == false);
		536	assert_or_panic(vec[9] == true);
		537	assert_or_panic(vec[10] == true);
		538	assert_or_panic(vec[11] == true);
		539	assert_or_panic(vec[12] == false);
		540	assert_or_panic(vec[13] == true);
		541	assert_or_panic(vec[14] == false);
		542	assert_or_panic(vec[15] == true);
		543	assert_or_panic(vec[16] == false);
		544	assert_or_panic(vec[17] == false);
		545	assert_or_panic(vec[18] == true);
		546	assert_or_panic(vec[19] == true);
		547	assert_or_panic(vec[20] == false);
		548	assert_or_panic(vec[21] == true);
		549	assert_or_panic(vec[22] == false);
		550	assert_or_panic(vec[23] == false);
		551	assert_or_panic(vec[24] == false);
		552	assert_or_panic(vec[25] == true);
		553	assert_or_panic(vec[26] == true);
		554	assert_or_panic(vec[27] == false);
		555	assert_or_panic(vec[28] == false);
		556	assert_or_panic(vec[29] == true);
		557	assert_or_panic(vec[30] == true);
		558	assert_or_panic(vec[31] == false);
		559	assert_or_panic(vec[32] == true);
		560	assert_or_panic(vec[33] == false);
		561	assert_or_panic(vec[34] == false);
		562	assert_or_panic(vec[35] == true);
		563	assert_or_panic(vec[36] == false);
		564	assert_or_panic(vec[37] == true);
		565	assert_or_panic(vec[38] == false);
		566	assert_or_panic(vec[39] == true);
		567	assert_or_panic(vec[40] == true);
		568	assert_or_panic(vec[41] == true);
		569	assert_or_panic(vec[42] == true);
		570	assert_or_panic(vec[43] == false);
		571	assert_or_panic(vec[44] == false);
		572	assert_or_panic(vec[45] == true);
		573	assert_or_panic(vec[46] == false);
		574	assert_or_panic(vec[47] == false);
		575	assert_or_panic(vec[48] == false);
		576	assert_or_panic(vec[49] == false);
		577	assert_or_panic(vec[50] == false);
		578	assert_or_panic(vec[51] == false);
		579	assert_or_panic(vec[52] == true);
		580	assert_or_panic(vec[53] == true);
		581	assert_or_panic(vec[54] == true);
		582	assert_or_panic(vec[55] == true);
		583	assert_or_panic(vec[56] == true);
		584	assert_or_panic(vec[57] == true);
		585	assert_or_panic(vec[58] == false);
		586	assert_or_panic(vec[59] == true);
		587	assert_or_panic(vec[60] == true);
		588	assert_or_panic(vec[61] == false);
		589	assert_or_panic(vec[62] == false);
		590	assert_or_panic(vec[63] == true);
		591	assert_or_panic(vec[64] == false);
		592	assert_or_panic(vec[65] == false);
		593	assert_or_panic(vec[66] == false);
		594	assert_or_panic(vec[67] == false);
		595	assert_or_panic(vec[68] == false);
		596	assert_or_panic(vec[69] == false);
		597	assert_or_panic(vec[70] == true);
		598	assert_or_panic(vec[71] == true);
		599	assert_or_panic(vec[72] == true);
		600	assert_or_panic(vec[73] == false);
		601	assert_or_panic(vec[74] == false);
		602	assert_or_panic(vec[75] == false);
		603	assert_or_panic(vec[76] == true);
		604	assert_or_panic(vec[77] == false);
		605	assert_or_panic(vec[78] == true);
		606	assert_or_panic(vec[79] == true);
		607	assert_or_panic(vec[80] == false);
		608	assert_or_panic(vec[81] == false);
		609	assert_or_panic(vec[82] == true);
		610	assert_or_panic(vec[83] == true);
		611	assert_or_panic(vec[84] == false);
		612	assert_or_panic(vec[85] == true);
		613	assert_or_panic(vec[86] == true);
		614	assert_or_panic(vec[87] == true);
		615	assert_or_panic(vec[88] == true);
		616	assert_or_panic(vec[89] == true);
		617	assert_or_panic(vec[90] == true);
		618	assert_or_panic(vec[91] == true);
		619	assert_or_panic(vec[92] == false);
		620	assert_or_panic(vec[93] == true);
		621	assert_or_panic(vec[94] == true);
		622	assert_or_panic(vec[95] == false);
		623	assert_or_panic(vec[96] == false);
		624	assert_or_panic(vec[97] == true);
		625	assert_or_panic(vec[98] == true);
		626	assert_or_panic(vec[99] == false);
		627	assert_or_panic(vec[100] == true);
		628	assert_or_panic(vec[101] == false);
		629	assert_or_panic(vec[102] == false);
		630	assert_or_panic(vec[103] == true);
		631	assert_or_panic(vec[104] == false);
		632	assert_or_panic(vec[105] == true);
		633	assert_or_panic(vec[106] == true);
		634	assert_or_panic(vec[107] == true);
		635	assert_or_panic(vec[108] == true);
		636	assert_or_panic(vec[109] == true);
		637	assert_or_panic(vec[110] == false);
		638	assert_or_panic(vec[111] == false);
		639	assert_or_panic(vec[112] == false);
		640	assert_or_panic(vec[113] == false);
		641	assert_or_panic(vec[114] == true);
		642	assert_or_panic(vec[115] == true);
		643	assert_or_panic(vec[116] == false);
		644	assert_or_panic(vec[117] == true);
		645	assert_or_panic(vec[118] == false);
		646	assert_or_panic(vec[119] == false);
		647	assert_or_panic(vec[120] == true);
		648	assert_or_panic(vec[121] == false);
		649	assert_or_panic(vec[122] == false);
		650	assert_or_panic(vec[123] == true);
		651	assert_or_panic(vec[124] == false);
		652	assert_or_panic(vec[125] == true);
		653	assert_or_panic(vec[126] == true);
		654	assert_or_panic(vec[127] == true);
		655	assert_or_panic(vec[128] == true);
		656	assert_or_panic(vec[129] == false);
		657	assert_or_panic(vec[130] == true);
		658	assert_or_panic(vec[131] == true);
		659	assert_or_panic(vec[132] == false);
		660	assert_or_panic(vec[133] == false);
		661	assert_or_panic(vec[134] == true);
		662	assert_or_panic(vec[135] == false);
		663	assert_or_panic(vec[136] == false);
		664	assert_or_panic(vec[137] == true);
		665	assert_or_panic(vec[138] == false);
		666	assert_or_panic(vec[139] == true);
		667	assert_or_panic(vec[140] == false);
		668	assert_or_panic(vec[141] == true);
		669	assert_or_panic(vec[142] == true);
		670	assert_or_panic(vec[143] == true);
		671	assert_or_panic(vec[144] == true);
		672	assert_or_panic(vec[145] == false);
		673	assert_or_panic(vec[146] == true);
		674	assert_or_panic(vec[147] == false);
		675	assert_or_panic(vec[148] == false);
		676	assert_or_panic(vec[149] == false);
		677	assert_or_panic(vec[150] == true);
		678	assert_or_panic(vec[151] == true);
		679	assert_or_panic(vec[152] == true);
		680	assert_or_panic(vec[153] == true);
		681	assert_or_panic(vec[154] == true);
		682	assert_or_panic(vec[155] == false);
		683	assert_or_panic(vec[156] == true);
		684	assert_or_panic(vec[157] == false);
		685	assert_or_panic(vec[158] == false);
		686	assert_or_panic(vec[159] == false);
		687	assert_or_panic(vec[160] == true);
		688	assert_or_panic(vec[161] == true);
		689	assert_or_panic(vec[162] == false);
		690	assert_or_panic(vec[163] == true);
		691	assert_or_panic(vec[164] == true);
		692	assert_or_panic(vec[165] == false);
		693	assert_or_panic(vec[166] == false);
		694	assert_or_panic(vec[167] == false);
		695	assert_or_panic(vec[168] == false);
		696	assert_or_panic(vec[169] == true);
		697	assert_or_panic(vec[170] == false);
		698	assert_or_panic(vec[171] == true);
		699	assert_or_panic(vec[172] == false);
		700	assert_or_panic(vec[173] == false);
		701	assert_or_panic(vec[174] == false);
		702	assert_or_panic(vec[175] == false);
		703	assert_or_panic(vec[176] == true);
		704	assert_or_panic(vec[177] == true);
		705	assert_or_panic(vec[178] == true);
		706	assert_or_panic(vec[179] == false);
		707	assert_or_panic(vec[180] == true);
		708	assert_or_panic(vec[181] == false);
		709	assert_or_panic(vec[182] == true);
		710	assert_or_panic(vec[183] == true);
		711	assert_or_panic(vec[184] == false);
		712	assert_or_panic(vec[185] == false);
		713	assert_or_panic(vec[186] == true);
		714	assert_or_panic(vec[187] == false);
		715	assert_or_panic(vec[188] == false);
		716	assert_or_panic(vec[189] == false);
		717	assert_or_panic(vec[190] == false);
		718	assert_or_panic(vec[191] == true);
		719	assert_or_panic(vec[192] == true);
		720	assert_or_panic(vec[193] == true);
		721	assert_or_panic(vec[194] == true);
		722	assert_or_panic(vec[195] == true);
		723	assert_or_panic(vec[196] == true);
		724	assert_or_panic(vec[197] == true);
		725	assert_or_panic(vec[198] == false);
		726	assert_or_panic(vec[199] == true);
		727	assert_or_panic(vec[200] == false);
		728	assert_or_panic(vec[201] == false);
		729	assert_or_panic(vec[202] == true);
		730	assert_or_panic(vec[203] == false);
		731	assert_or_panic(vec[204] == true);
		732	assert_or_panic(vec[205] == true);
		733	assert_or_panic(vec[206] == true);
		734	assert_or_panic(vec[207] == false);
		735	assert_or_panic(vec[208] == false);
		736	assert_or_panic(vec[209] == true);
		737	assert_or_panic(vec[210] == true);
		738	assert_or_panic(vec[211] == true);
		739	assert_or_panic(vec[212] == false);
		740	assert_or_panic(vec[213] == true);
		741	assert_or_panic(vec[214] == true);
		742	assert_or_panic(vec[215] == true);
		743	assert_or_panic(vec[216] == true);
		744	assert_or_panic(vec[217] == true);
		745	assert_or_panic(vec[218] == false);
		746	assert_or_panic(vec[219] == false);
		747	assert_or_panic(vec[220] == false);
		748	assert_or_panic(vec[221] == false);
		749	assert_or_panic(vec[222] == false);
		750	assert_or_panic(vec[223] == true);
		751	assert_or_panic(vec[224] == true);
		752	assert_or_panic(vec[225] == false);
		753	assert_or_panic(vec[226] == true);
		754	assert_or_panic(vec[227] == false);
		755	assert_or_panic(vec[228] == false);
		756	assert_or_panic(vec[229] == true);
		757	assert_or_panic(vec[230] == false);
		758	assert_or_panic(vec[231] == true);
		759	assert_or_panic(vec[232] == false);
		760	assert_or_panic(vec[233] == false);
		761	assert_or_panic(vec[234] == false);
		762	assert_or_panic(vec[235] == true);
		763	assert_or_panic(vec[236] == false);
		764	assert_or_panic(vec[237] == false);
		765	assert_or_panic(vec[238] == false);
		766	assert_or_panic(vec[239] == true);
		767	assert_or_panic(vec[240] == true);
		768	assert_or_panic(vec[241] == true);
		769	assert_or_panic(vec[242] == true);
		770	assert_or_panic(vec[243] == true);
		771	assert_or_panic(vec[244] == true);
		772	assert_or_panic(vec[245] == false);
		773	assert_or_panic(vec[246] == false);
		774	assert_or_panic(vec[247] == true);
		775	assert_or_panic(vec[248] == false);
		776	assert_or_panic(vec[249] == true);
		777	assert_or_panic(vec[250] == true);
		778	assert_or_panic(vec[251] == false);
		779	assert_or_panic(vec[252] == true);
		780	assert_or_panic(vec[253] == true);
		781	assert_or_panic(vec[254] == true);
		782	assert_or_panic(vec[255] == false);
		783	}
		784
		785	void c_vector_512_bool(Vector512Bool vec) {
		786	assert_or_panic(vec[0] == true);
		787	assert_or_panic(vec[1] == true);
		788	assert_or_panic(vec[2] == true);
		789	assert_or_panic(vec[3] == true);
		790	assert_or_panic(vec[4] == true);
		791	assert_or_panic(vec[5] == false);
		792	assert_or_panic(vec[6] == false);
		793	assert_or_panic(vec[7] == true);
		794	assert_or_panic(vec[8] == true);
		795	assert_or_panic(vec[9] == true);
		796	assert_or_panic(vec[10] == true);
		797	assert_or_panic(vec[11] == false);
		798	assert_or_panic(vec[12] == true);
		799	assert_or_panic(vec[13] == true);
		800	assert_or_panic(vec[14] == false);
		801	assert_or_panic(vec[15] == false);
		802	assert_or_panic(vec[16] == false);
		803	assert_or_panic(vec[17] == true);
		804	assert_or_panic(vec[18] == true);
		805	assert_or_panic(vec[19] == true);
		806	assert_or_panic(vec[20] == true);
		807	assert_or_panic(vec[21] == true);
		808	assert_or_panic(vec[22] == false);
		809	assert_or_panic(vec[23] == false);
		810	assert_or_panic(vec[24] == true);
		811	assert_or_panic(vec[25] == true);
		812	assert_or_panic(vec[26] == false);
		813	assert_or_panic(vec[27] == false);
		814	assert_or_panic(vec[28] == false);
		815	assert_or_panic(vec[29] == false);
		816	assert_or_panic(vec[30] == false);
		817	assert_or_panic(vec[31] == true);
		818	assert_or_panic(vec[32] == true);
		819	assert_or_panic(vec[33] == false);
		820	assert_or_panic(vec[34] == true);
		821	assert_or_panic(vec[35] == true);
		822	assert_or_panic(vec[36] == true);
		823	assert_or_panic(vec[37] == true);
		824	assert_or_panic(vec[38] == true);
		825	assert_or_panic(vec[39] == true);
		826	assert_or_panic(vec[40] == false);
		827	assert_or_panic(vec[41] == true);
		828	assert_or_panic(vec[42] == true);
		829	assert_or_panic(vec[43] == false);
		830	assert_or_panic(vec[44] == false);
		831	assert_or_panic(vec[45] == false);
		832	assert_or_panic(vec[46] == true);
		833	assert_or_panic(vec[47] == true);
		834	assert_or_panic(vec[48] == false);
		835	assert_or_panic(vec[49] == true);
		836	assert_or_panic(vec[50] == false);
		837	assert_or_panic(vec[51] == true);
		838	assert_or_panic(vec[52] == true);
		839	assert_or_panic(vec[53] == false);
		840	assert_or_panic(vec[54] == true);
		841	assert_or_panic(vec[55] == false);
		842	assert_or_panic(vec[56] == false);
		843	assert_or_panic(vec[57] == true);
		844	assert_or_panic(vec[58] == true);
		845	assert_or_panic(vec[59] == false);
		846	assert_or_panic(vec[60] == true);
		847	assert_or_panic(vec[61] == true);
		848	assert_or_panic(vec[62] == false);
		849	assert_or_panic(vec[63] == true);
		850	assert_or_panic(vec[64] == false);
		851	assert_or_panic(vec[65] == true);
		852	assert_or_panic(vec[66] == true);
		853	assert_or_panic(vec[67] == true);
		854	assert_or_panic(vec[68] == true);
		855	assert_or_panic(vec[69] == true);
		856	assert_or_panic(vec[70] == true);
		857	assert_or_panic(vec[71] == true);
		858	assert_or_panic(vec[72] == true);
		859	assert_or_panic(vec[73] == true);
		860	assert_or_panic(vec[74] == false);
		861	assert_or_panic(vec[75] == true);
		862	assert_or_panic(vec[76] == false);
		863	assert_or_panic(vec[77] == true);
		864	assert_or_panic(vec[78] == false);
		865	assert_or_panic(vec[79] == false);
		866	assert_or_panic(vec[80] == false);
		867	assert_or_panic(vec[81] == true);
		868	assert_or_panic(vec[82] == false);
		869	assert_or_panic(vec[83] == true);
		870	assert_or_panic(vec[84] == true);
		871	assert_or_panic(vec[85] == false);
		872	assert_or_panic(vec[86] == true);
		873	assert_or_panic(vec[87] == true);
		874	assert_or_panic(vec[88] == true);
		875	assert_or_panic(vec[89] == false);
		876	assert_or_panic(vec[90] == true);
		877	assert_or_panic(vec[91] == true);
		878	assert_or_panic(vec[92] == false);
		879	assert_or_panic(vec[93] == true);
		880	assert_or_panic(vec[94] == false);
		881	assert_or_panic(vec[95] == true);
		882	assert_or_panic(vec[96] == true);
		883	assert_or_panic(vec[97] == false);
		884	assert_or_panic(vec[98] == false);
		885	assert_or_panic(vec[99] == false);
		886	assert_or_panic(vec[100] == true);
		887	assert_or_panic(vec[101] == true);
		888	assert_or_panic(vec[102] == false);
		889	assert_or_panic(vec[103] == true);
		890	assert_or_panic(vec[104] == false);
		891	assert_or_panic(vec[105] == false);
		892	assert_or_panic(vec[106] == true);
		893	assert_or_panic(vec[107] == false);
		894	assert_or_panic(vec[108] == false);
		895	assert_or_panic(vec[109] == true);
		896	assert_or_panic(vec[110] == false);
		897	assert_or_panic(vec[111] == false);
		898	assert_or_panic(vec[112] == false);
		899	assert_or_panic(vec[113] == false);
		900	assert_or_panic(vec[114] == false);
		901	assert_or_panic(vec[115] == true);
		902	assert_or_panic(vec[116] == true);
		903	assert_or_panic(vec[117] == false);
		904	assert_or_panic(vec[118] == false);
		905	assert_or_panic(vec[119] == false);
		906	assert_or_panic(vec[120] == false);
		907	assert_or_panic(vec[121] == true);
		908	assert_or_panic(vec[122] == false);
		909	assert_or_panic(vec[123] == false);
		910	assert_or_panic(vec[124] == true);
		911	assert_or_panic(vec[125] == true);
		912	assert_or_panic(vec[126] == false);
		913	assert_or_panic(vec[127] == true);
		914	assert_or_panic(vec[128] == false);
		915	assert_or_panic(vec[129] == true);
		916	assert_or_panic(vec[130] == true);
		917	assert_or_panic(vec[131] == false);
		918	assert_or_panic(vec[132] == true);
		919	assert_or_panic(vec[133] == false);
		920	assert_or_panic(vec[134] == false);
		921	assert_or_panic(vec[135] == false);
		922	assert_or_panic(vec[136] == false);
		923	assert_or_panic(vec[137] == true);
		924	assert_or_panic(vec[138] == true);
		925	assert_or_panic(vec[139] == false);
		926	assert_or_panic(vec[140] == false);
		927	assert_or_panic(vec[141] == false);
		928	assert_or_panic(vec[142] == true);
		929	assert_or_panic(vec[143] == true);
		930	assert_or_panic(vec[144] == false);
		931	assert_or_panic(vec[145] == false);
		932	assert_or_panic(vec[146] == true);
		933	assert_or_panic(vec[147] == true);
		934	assert_or_panic(vec[148] == true);
		935	assert_or_panic(vec[149] == true);
		936	assert_or_panic(vec[150] == true);
		937	assert_or_panic(vec[151] == true);
		938	assert_or_panic(vec[152] == true);
		939	assert_or_panic(vec[153] == false);
		940	assert_or_panic(vec[154] == true);
		941	assert_or_panic(vec[155] == false);
		942	assert_or_panic(vec[156] == false);
		943	assert_or_panic(vec[157] == true);
		944	assert_or_panic(vec[158] == false);
		945	assert_or_panic(vec[159] == true);
		946	assert_or_panic(vec[160] == false);
		947	assert_or_panic(vec[161] == true);
		948	assert_or_panic(vec[162] == true);
		949	assert_or_panic(vec[163] == true);
		950	assert_or_panic(vec[164] == true);
		951	assert_or_panic(vec[165] == true);
		952	assert_or_panic(vec[166] == true);
		953	assert_or_panic(vec[167] == true);
		954	assert_or_panic(vec[168] == true);
		955	assert_or_panic(vec[169] == false);
		956	assert_or_panic(vec[170] == true);
		957	assert_or_panic(vec[171] == true);
		958	assert_or_panic(vec[172] == false);
		959	assert_or_panic(vec[173] == true);
		960	assert_or_panic(vec[174] == true);
		961	assert_or_panic(vec[175] == false);
		962	assert_or_panic(vec[176] == false);
		963	assert_or_panic(vec[177] == false);
		964	assert_or_panic(vec[178] == true);
		965	assert_or_panic(vec[179] == false);
		966	assert_or_panic(vec[180] == false);
		967	assert_or_panic(vec[181] == true);
		968	assert_or_panic(vec[182] == true);
		969	assert_or_panic(vec[183] == true);
		970	assert_or_panic(vec[184] == true);
		971	assert_or_panic(vec[185] == true);
		972	assert_or_panic(vec[186] == true);
		973	assert_or_panic(vec[187] == true);
		974	assert_or_panic(vec[188] == true);
		975	assert_or_panic(vec[189] == true);
		976	assert_or_panic(vec[190] == false);
		977	assert_or_panic(vec[191] == true);
		978	assert_or_panic(vec[192] == true);
		979	assert_or_panic(vec[193] == false);
		980	assert_or_panic(vec[194] == false);
		981	assert_or_panic(vec[195] == true);
		982	assert_or_panic(vec[196] == true);
		983	assert_or_panic(vec[197] == false);
		984	assert_or_panic(vec[198] == true);
		985	assert_or_panic(vec[199] == true);
		986	assert_or_panic(vec[200] == false);
		987	assert_or_panic(vec[201] == true);
		988	assert_or_panic(vec[202] == true);
		989	assert_or_panic(vec[203] == false);
		990	assert_or_panic(vec[204] == true);
		991	assert_or_panic(vec[205] == true);
		992	assert_or_panic(vec[206] == true);
		993	assert_or_panic(vec[207] == true);
		994	assert_or_panic(vec[208] == false);
		995	assert_or_panic(vec[209] == true);
		996	assert_or_panic(vec[210] == false);
		997	assert_or_panic(vec[211] == true);
		998	assert_or_panic(vec[212] == true);
		999	assert_or_panic(vec[213] == false);
		1000	assert_or_panic(vec[214] == true);
		1001	assert_or_panic(vec[215] == false);
		1002	assert_or_panic(vec[216] == true);
		1003	assert_or_panic(vec[217] == false);
		1004	assert_or_panic(vec[218] == true);
		1005	assert_or_panic(vec[219] == false);
		1006	assert_or_panic(vec[220] == false);
		1007	assert_or_panic(vec[221] == true);
		1008	assert_or_panic(vec[222] == false);
		1009	assert_or_panic(vec[223] == false);
		1010	assert_or_panic(vec[224] == false);
		1011	assert_or_panic(vec[225] == true);
		1012	assert_or_panic(vec[226] == true);
		1013	assert_or_panic(vec[227] == false);
		1014	assert_or_panic(vec[228] == false);
		1015	assert_or_panic(vec[229] == false);
		1016	assert_or_panic(vec[230] == true);
		1017	assert_or_panic(vec[231] == false);
		1018	assert_or_panic(vec[232] == true);
		1019	assert_or_panic(vec[233] == false);
		1020	assert_or_panic(vec[234] == false);
		1021	assert_or_panic(vec[235] == false);
		1022	assert_or_panic(vec[236] == true);
		1023	assert_or_panic(vec[237] == true);
		1024	assert_or_panic(vec[238] == false);
		1025	assert_or_panic(vec[239] == false);
		1026	assert_or_panic(vec[240] == false);
		1027	assert_or_panic(vec[241] == false);
		1028	assert_or_panic(vec[242] == false);
		1029	assert_or_panic(vec[243] == true);
		1030	assert_or_panic(vec[244] == true);
		1031	assert_or_panic(vec[245] == false);
		1032	assert_or_panic(vec[246] == true);
		1033	assert_or_panic(vec[247] == false);
		1034	assert_or_panic(vec[248] == false);
		1035	assert_or_panic(vec[249] == true);
		1036	assert_or_panic(vec[250] == false);
		1037	assert_or_panic(vec[251] == false);
		1038	assert_or_panic(vec[252] == false);
		1039	assert_or_panic(vec[253] == true);
		1040	assert_or_panic(vec[254] == false);
		1041	assert_or_panic(vec[255] == false);
		1042	assert_or_panic(vec[256] == false);
		1043	assert_or_panic(vec[257] == false);
		1044	assert_or_panic(vec[258] == true);
		1045	assert_or_panic(vec[259] == true);
		1046	assert_or_panic(vec[260] == true);
		1047	assert_or_panic(vec[261] == true);
		1048	assert_or_panic(vec[262] == false);
		1049	assert_or_panic(vec[263] == true);
		1050	assert_or_panic(vec[264] == false);
		1051	assert_or_panic(vec[265] == false);
		1052	assert_or_panic(vec[266] == false);
		1053	assert_or_panic(vec[267] == true);
		1054	assert_or_panic(vec[268] == false);
		1055	assert_or_panic(vec[269] == false);
		1056	assert_or_panic(vec[270] == true);
		1057	assert_or_panic(vec[271] == true);
		1058	assert_or_panic(vec[272] == false);
		1059	assert_or_panic(vec[273] == false);
		1060	assert_or_panic(vec[274] == false);
		1061	assert_or_panic(vec[275] == false);
		1062	assert_or_panic(vec[276] == false);
		1063	assert_or_panic(vec[277] == true);
		1064	assert_or_panic(vec[278] == false);
		1065	assert_or_panic(vec[279] == true);
		1066	assert_or_panic(vec[280] == true);
		1067	assert_or_panic(vec[281] == true);
		1068	assert_or_panic(vec[282] == true);
		1069	assert_or_panic(vec[283] == true);
		1070	assert_or_panic(vec[284] == false);
		1071	assert_or_panic(vec[285] == false);
		1072	assert_or_panic(vec[286] == false);
		1073	assert_or_panic(vec[287] == false);
		1074	assert_or_panic(vec[288] == false);
		1075	assert_or_panic(vec[289] == false);
		1076	assert_or_panic(vec[290] == false);
		1077	assert_or_panic(vec[291] == false);
		1078	assert_or_panic(vec[292] == false);
		1079	assert_or_panic(vec[293] == true);
		1080	assert_or_panic(vec[294] == true);
		1081	assert_or_panic(vec[295] == true);
		1082	assert_or_panic(vec[296] == true);
		1083	assert_or_panic(vec[297] == true);
		1084	assert_or_panic(vec[298] == true);
		1085	assert_or_panic(vec[299] == false);
		1086	assert_or_panic(vec[300] == true);
		1087	assert_or_panic(vec[301] == false);
		1088	assert_or_panic(vec[302] == true);
		1089	assert_or_panic(vec[303] == true);
		1090	assert_or_panic(vec[304] == true);
		1091	assert_or_panic(vec[305] == false);
		1092	assert_or_panic(vec[306] == false);
		1093	assert_or_panic(vec[307] == true);
		1094	assert_or_panic(vec[308] == true);
		1095	assert_or_panic(vec[309] == true);
		1096	assert_or_panic(vec[310] == false);
		1097	assert_or_panic(vec[311] == true);
		1098	assert_or_panic(vec[312] == true);
		1099	assert_or_panic(vec[313] == true);
		1100	assert_or_panic(vec[314] == false);
		1101	assert_or_panic(vec[315] == true);
		1102	assert_or_panic(vec[316] == true);
		1103	assert_or_panic(vec[317] == true);
		1104	assert_or_panic(vec[318] == false);
		1105	assert_or_panic(vec[319] == true);
		1106	assert_or_panic(vec[320] == true);
		1107	assert_or_panic(vec[321] == false);
		1108	assert_or_panic(vec[322] == false);
		1109	assert_or_panic(vec[323] == true);
		1110	assert_or_panic(vec[324] == false);
		1111	assert_or_panic(vec[325] == false);
		1112	assert_or_panic(vec[326] == false);
		1113	assert_or_panic(vec[327] == false);
		1114	assert_or_panic(vec[328] == true);
		1115	assert_or_panic(vec[329] == false);
		1116	assert_or_panic(vec[330] == true);
		1117	assert_or_panic(vec[331] == true);
		1118	assert_or_panic(vec[332] == true);
		1119	assert_or_panic(vec[333] == true);
		1120	assert_or_panic(vec[334] == false);
		1121	assert_or_panic(vec[335] == false);
		1122	assert_or_panic(vec[336] == true);
		1123	assert_or_panic(vec[337] == false);
		1124	assert_or_panic(vec[338] == true);
		1125	assert_or_panic(vec[339] == false);
		1126	assert_or_panic(vec[340] == false);
		1127	assert_or_panic(vec[341] == false);
		1128	assert_or_panic(vec[342] == true);
		1129	assert_or_panic(vec[343] == false);
		1130	assert_or_panic(vec[344] == true);
		1131	assert_or_panic(vec[345] == false);
		1132	assert_or_panic(vec[346] == false);
		1133	assert_or_panic(vec[347] == true);
		1134	assert_or_panic(vec[348] == true);
		1135	assert_or_panic(vec[349] == true);
		1136	assert_or_panic(vec[350] == true);
		1137	assert_or_panic(vec[351] == false);
		1138	assert_or_panic(vec[352] == false);
		1139	assert_or_panic(vec[353] == false);
		1140	assert_or_panic(vec[354] == true);
		1141	assert_or_panic(vec[355] == true);
		1142	assert_or_panic(vec[356] == false);
		1143	assert_or_panic(vec[357] == true);
		1144	assert_or_panic(vec[358] == false);
		1145	assert_or_panic(vec[359] == false);
		1146	assert_or_panic(vec[360] == true);
		1147	assert_or_panic(vec[361] == false);
		1148	assert_or_panic(vec[362] == true);
		1149	assert_or_panic(vec[363] == false);
		1150	assert_or_panic(vec[364] == true);
		1151	assert_or_panic(vec[365] == true);
		1152	assert_or_panic(vec[366] == false);
		1153	assert_or_panic(vec[367] == false);
		1154	assert_or_panic(vec[368] == true);
		1155	assert_or_panic(vec[369] == true);
		1156	assert_or_panic(vec[370] == true);
		1157	assert_or_panic(vec[371] == true);
		1158	assert_or_panic(vec[372] == false);
		1159	assert_or_panic(vec[373] == false);
		1160	assert_or_panic(vec[374] == true);
		1161	assert_or_panic(vec[375] == false);
		1162	assert_or_panic(vec[376] == true);
		1163	assert_or_panic(vec[377] == true);
		1164	assert_or_panic(vec[378] == false);
		1165	assert_or_panic(vec[379] == true);
		1166	assert_or_panic(vec[380] == true);
		1167	assert_or_panic(vec[381] == false);
		1168	assert_or_panic(vec[382] == true);
		1169	assert_or_panic(vec[383] == true);
		1170	assert_or_panic(vec[384] == true);
		1171	assert_or_panic(vec[385] == false);
		1172	assert_or_panic(vec[386] == true);
		1173	assert_or_panic(vec[387] == true);
		1174	assert_or_panic(vec[388] == true);
		1175	assert_or_panic(vec[389] == false);
		1176	assert_or_panic(vec[390] == false);
		1177	assert_or_panic(vec[391] == true);
		1178	assert_or_panic(vec[392] == false);
		1179	assert_or_panic(vec[393] == true);
		1180	assert_or_panic(vec[394] == true);
		1181	assert_or_panic(vec[395] == true);
		1182	assert_or_panic(vec[396] == false);
		1183	assert_or_panic(vec[397] == false);
		1184	assert_or_panic(vec[398] == false);
		1185	assert_or_panic(vec[399] == false);
		1186	assert_or_panic(vec[400] == false);
		1187	assert_or_panic(vec[401] == true);
		1188	assert_or_panic(vec[402] == false);
		1189	assert_or_panic(vec[403] == false);
		1190	assert_or_panic(vec[404] == false);
		1191	assert_or_panic(vec[405] == false);
		1192	assert_or_panic(vec[406] == true);
		1193	assert_or_panic(vec[407] == false);
		1194	assert_or_panic(vec[408] == false);
		1195	assert_or_panic(vec[409] == true);
		1196	assert_or_panic(vec[410] == true);
		1197	assert_or_panic(vec[411] == false);
		1198	assert_or_panic(vec[412] == false);
		1199	assert_or_panic(vec[413] == false);
		1200	assert_or_panic(vec[414] == false);
		1201	assert_or_panic(vec[415] == true);
		1202	assert_or_panic(vec[416] == true);
		1203	assert_or_panic(vec[417] == true);
		1204	assert_or_panic(vec[418] == true);
		1205	assert_or_panic(vec[419] == true);
		1206	assert_or_panic(vec[420] == false);
		1207	assert_or_panic(vec[421] == false);
		1208	assert_or_panic(vec[422] == false);
		1209	assert_or_panic(vec[423] == true);
		1210	assert_or_panic(vec[424] == false);
		1211	assert_or_panic(vec[425] == false);
		1212	assert_or_panic(vec[426] == false);
		1213	assert_or_panic(vec[427] == false);
		1214	assert_or_panic(vec[428] == true);
		1215	assert_or_panic(vec[429] == false);
		1216	assert_or_panic(vec[430] == true);
		1217	assert_or_panic(vec[431] == false);
		1218	assert_or_panic(vec[432] == true);
		1219	assert_or_panic(vec[433] == true);
		1220	assert_or_panic(vec[434] == true);
		1221	assert_or_panic(vec[435] == true);
		1222	assert_or_panic(vec[436] == false);
		1223	assert_or_panic(vec[437] == false);
		1224	assert_or_panic(vec[438] == false);
		1225	assert_or_panic(vec[439] == false);
		1226	assert_or_panic(vec[440] == false);
		1227	assert_or_panic(vec[441] == true);
		1228	assert_or_panic(vec[442] == true);
		1229	assert_or_panic(vec[443] == true);
		1230	assert_or_panic(vec[444] == true);
		1231	assert_or_panic(vec[445] == true);
		1232	assert_or_panic(vec[446] == true);
		1233	assert_or_panic(vec[447] == true);
		1234	assert_or_panic(vec[448] == true);
		1235	assert_or_panic(vec[449] == true);
		1236	assert_or_panic(vec[450] == false);
		1237	assert_or_panic(vec[451] == false);
		1238	assert_or_panic(vec[452] == true);
		1239	assert_or_panic(vec[453] == false);
		1240	assert_or_panic(vec[454] == true);
		1241	assert_or_panic(vec[455] == false);
		1242	assert_or_panic(vec[456] == false);
		1243	assert_or_panic(vec[457] == true);
		1244	assert_or_panic(vec[458] == false);
		1245	assert_or_panic(vec[459] == false);
		1246	assert_or_panic(vec[460] == true);
		1247	assert_or_panic(vec[461] == true);
		1248	assert_or_panic(vec[462] == true);
		1249	assert_or_panic(vec[463] == true);
		1250	assert_or_panic(vec[464] == true);
		1251	assert_or_panic(vec[465] == true);
		1252	assert_or_panic(vec[466] == false);
		1253	assert_or_panic(vec[467] == true);
		1254	assert_or_panic(vec[468] == false);
		1255	assert_or_panic(vec[469] == false);
		1256	assert_or_panic(vec[470] == false);
		1257	assert_or_panic(vec[471] == true);
		1258	assert_or_panic(vec[472] == true);
		1259	assert_or_panic(vec[473] == false);
		1260	assert_or_panic(vec[474] == true);
		1261	assert_or_panic(vec[475] == true);
		1262	assert_or_panic(vec[476] == false);
		1263	assert_or_panic(vec[477] == false);
		1264	assert_or_panic(vec[478] == true);
		1265	assert_or_panic(vec[479] == true);
		1266	assert_or_panic(vec[480] == false);
		1267	assert_or_panic(vec[481] == false);
		1268	assert_or_panic(vec[482] == true);
		1269	assert_or_panic(vec[483] == true);
		1270	assert_or_panic(vec[484] == false);
		1271	assert_or_panic(vec[485] == true);
		1272	assert_or_panic(vec[486] == false);
		1273	assert_or_panic(vec[487] == true);
		1274	assert_or_panic(vec[488] == true);
		1275	assert_or_panic(vec[489] == true);
		1276	assert_or_panic(vec[490] == true);
		1277	assert_or_panic(vec[491] == true);
		1278	assert_or_panic(vec[492] == true);
		1279	assert_or_panic(vec[493] == true);
		1280	assert_or_panic(vec[494] == true);
		1281	assert_or_panic(vec[495] == true);
		1282	assert_or_panic(vec[496] == false);
		1283	assert_or_panic(vec[497] == true);
		1284	assert_or_panic(vec[498] == true);
		1285	assert_or_panic(vec[499] == true);
		1286	assert_or_panic(vec[500] == false);
		1287	assert_or_panic(vec[501] == false);
		1288	assert_or_panic(vec[502] == true);
		1289	assert_or_panic(vec[503] == false);
		1290	assert_or_panic(vec[504] == false);
		1291	assert_or_panic(vec[505] == false);
		1292	assert_or_panic(vec[506] == true);
		1293	assert_or_panic(vec[507] == true);
		1294	assert_or_panic(vec[508] == false);
		1295	assert_or_panic(vec[509] == true);
		1296	assert_or_panic(vec[510] == false);
		1297	assert_or_panic(vec[511] == true);
		1298	}
		1299
		1300	Vector2Bool c_ret_vector_2_bool(void) {
		1301	return (Vector2Bool){
		1302	true,
		1303	false,
		1304	};
		1305	}
		1306
		1307	Vector4Bool c_ret_vector_4_bool(void) {
		1308	return (Vector4Bool){
		1309	true,
		1310	false,
		1311	true,
		1312	false,
		1313	};
		1314	}
		1315
		1316	Vector8Bool c_ret_vector_8_bool(void) {
		1317	return (Vector8Bool){
		1318	false,
		1319	true,
		1320	false,
		1321	false,
		1322	true,
		1323	false,
		1324	false,
		1325	true,
		1326	};
		1327	}
		1328
		1329	Vector16Bool c_ret_vector_16_bool(void) {
		1330	return (Vector16Bool){
		1331	true,
		1332	true,
		1333	false,
		1334	false,
		1335	false,
		1336	false,
		1337	true,
		1338	false,
		1339	true,
		1340	false,
		1341	false,
		1342	true,
		1343	true,
		1344	false,
		1345	true,
		1346	true,
		1347	};
		1348	}
		1349
		1350	Vector32Bool c_ret_vector_32_bool(void) {
		1351	return (Vector32Bool){
		1352	true,
		1353	false,
		1354	true,
		1355	true,
		1356	true,
		1357	false,
		1358	true,
		1359	false,
		1360	true,
		1361	true,
		1362	true,
		1363	false,
		1364	true,
		1365	true,
		1366	false,
		1367	false,
		1368	true,
		1369	false,
		1370	false,
		1371	false,
		1372	false,
		1373	true,
		1374	true,
		1375	true,
		1376	false,
		1377	true,
		1378	false,
		1379	false,
		1380	true,
		1381	false,
		1382	false,
		1383	false,
		1384	};
		1385	}
		1386
		1387	Vector64Bool c_ret_vector_64_bool(void) {
		1388	return (Vector64Bool){
		1389	false,
		1390	true,
		1391	false,
		1392	true,
		1393	true,
		1394	true,
		1395	false,
		1396	true,
		1397	true,
		1398	true,
		1399	true,
		1400	true,
		1401	true,
		1402	false,
		1403	true,
		1404	true,
		1405	true,
		1406	false,
		1407	false,
		1408	false,
		1409	true,
		1410	true,
		1411	false,
		1412	true,
		1413	false,
		1414	true,
		1415	false,
		1416	true,
		1417	false,
		1418	true,
		1419	false,
		1420	true,
		1421	false,
		1422	false,
		1423	true,
		1424	true,
		1425	false,
		1426	false,
		1427	false,
		1428	true,
		1429	true,
		1430	true,
		1431	true,
		1432	false,
		1433	false,
		1434	false,
		1435	true,
		1436	true,
		1437	false,
		1438	false,
		1439	true,
		1440	false,
		1441	false,
		1442	false,
		1443	false,
		1444	true,
		1445	false,
		1446	false,
		1447	false,
		1448	true,
		1449	true,
		1450	true,
		1451	true,
		1452	true,
		1453	};
		1454	}
		1455
		1456	Vector128Bool c_ret_vector_128_bool(void) {
		1457	return (Vector128Bool){
		1458	false,
		1459	true,
		1460	true,
		1461	false,
		1462	true,
		1463	false,
		1464	false,
		1465	true,
		1466	true,
		1467	false,
		1468	true,
		1469	false,
		1470	false,
		1471	false,
		1472	true,
		1473	false,
		1474	true,
		1475	false,
		1476	false,
		1477	true,
		1478	false,
		1479	true,
		1480	false,
		1481	false,
		1482	false,
		1483	true,
		1484	true,
		1485	true,
		1486	false,
		1487	false,
		1488	false,
		1489	false,
		1490	true,
		1491	true,
		1492	true,
		1493	false,
		1494	true,
		1495	true,
		1496	false,
		1497	false,
		1498	false,
		1499	false,
		1500	true,
		1501	true,
		1502	true,
		1503	false,
		1504	false,
		1505	false,
		1506	false,
		1507	true,
		1508	false,
		1509	false,
		1510	true,
		1511	false,
		1512	false,
		1513	false,
		1514	false,
		1515	false,
		1516	true,
		1517	true,
		1518	true,
		1519	false,
		1520	true,
		1521	true,
		1522	false,
		1523	false,
		1524	false,
		1525	false,
		1526	false,
		1527	false,
		1528	false,
		1529	false,
		1530	true,
		1531	true,
		1532	true,
		1533	true,
		1534	true,
		1535	false,
		1536	false,
		1537	false,
		1538	false,
		1539	false,
		1540	false,
		1541	true,
		1542	false,
		1543	true,
		1544	false,
		1545	true,
		1546	false,
		1547	true,
		1548	false,
		1549	true,
		1550	true,
		1551	true,
		1552	true,
		1553	false,
		1554	false,
		1555	true,
		1556	false,
		1557	false,
		1558	true,
		1559	true,
		1560	true,
		1561	true,
		1562	false,
		1563	true,
		1564	true,
		1565	true,
		1566	false,
		1567	false,
		1568	true,
		1569	false,
		1570	false,
		1571	true,
		1572	true,
		1573	false,
		1574	true,
		1575	false,
		1576	true,
		1577	true,
		1578	true,
		1579	true,
		1580	true,
		1581	false,
		1582	false,
		1583	true,
		1584	false,
		1585	true,
		1586	};
		1587	}
		1588
		1589	Vector256Bool c_ret_vector_256_bool(void) {
		1590	return (Vector256Bool){
		1591	true,
		1592	false,
		1593	true,
		1594	true,
		1595	false,
		1596	false,
		1597	false,
		1598	false,
		1599	false,
		1600	true,
		1601	false,
		1602	true,
		1603	false,
		1604	true,
		1605	false,
		1606	false,
		1607	true,
		1608	true,
		1609	true,
		1610	false,
		1611	false,
		1612	false,
		1613	true,
		1614	false,
		1615	true,
		1616	false,
		1617	false,
		1618	true,
		1619	true,
		1620	true,
		1621	false,
		1622	false,
		1623	true,
		1624	true,
		1625	true,
		1626	false,
		1627	true,
		1628	true,
		1629	true,
		1630	false,
		1631	true,
		1632	false,
		1633	true,
		1634	true,
		1635	false,
		1636	true,
		1637	false,
		1638	true,
		1639	true,
		1640	false,
		1641	false,
		1642	true,
		1643	true,
		1644	false,
		1645	false,
		1646	true,
		1647	false,
		1648	true,
		1649	true,
		1650	true,
		1651	false,
		1652	true,
		1653	true,
		1654	false,
		1655	true,
		1656	true,
		1657	false,
		1658	true,
		1659	false,
		1660	true,
		1661	true,
		1662	true,
		1663	false,
		1664	true,
		1665	true,
		1666	false,
		1667	true,
		1668	true,
		1669	true,
		1670	true,
		1671	false,
		1672	true,
		1673	false,
		1674	true,
		1675	true,
		1676	true,
		1677	false,
		1678	true,
		1679	false,
		1680	true,
		1681	false,
		1682	false,
		1683	true,
		1684	false,
		1685	false,
		1686	false,
		1687	true,
		1688	true,
		1689	false,
		1690	false,
		1691	false,
		1692	true,
		1693	true,
		1694	true,
		1695	false,
		1696	false,
		1697	false,
		1698	true,
		1699	false,
		1700	true,
		1701	true,
		1702	true,
		1703	true,
		1704	true,
		1705	true,
		1706	true,
		1707	true,
		1708	false,
		1709	true,
		1710	false,
		1711	true,
		1712	false,
		1713	false,
		1714	true,
		1715	true,
		1716	false,
		1717	true,
		1718	false,
		1719	false,
		1720	false,
		1721	false,
		1722	true,
		1723	false,
		1724	false,
		1725	true,
		1726	false,
		1727	false,
		1728	false,
		1729	false,
		1730	false,
		1731	false,
		1732	true,
		1733	false,
		1734	true,
		1735	false,
		1736	true,
		1737	true,
		1738	true,
		1739	false,
		1740	true,
		1741	true,
		1742	false,
		1743	true,
		1744	true,
		1745	false,
		1746	true,
		1747	true,
		1748	true,
		1749	true,
		1750	true,
		1751	true,
		1752	true,
		1753	false,
		1754	false,
		1755	false,
		1756	true,
		1757	false,
		1758	false,
		1759	true,
		1760	false,
		1761	true,
		1762	true,
		1763	true,
		1764	false,
		1765	false,
		1766	true,
		1767	true,
		1768	true,
		1769	true,
		1770	false,
		1771	true,
		1772	true,
		1773	false,
		1774	true,
		1775	false,
		1776	false,
		1777	false,
		1778	true,
		1779	true,
		1780	true,
		1781	true,
		1782	true,
		1783	true,
		1784	true,
		1785	true,
		1786	false,
		1787	false,
		1788	true,
		1789	false,
		1790	false,
		1791	false,
		1792	true,
		1793	true,
		1794	true,
		1795	true,
		1796	true,
		1797	true,
		1798	false,
		1799	false,
		1800	false,
		1801	true,
		1802	true,
		1803	true,
		1804	false,
		1805	true,
		1806	false,
		1807	true,
		1808	false,
		1809	true,
		1810	false,
		1811	true,
		1812	true,
		1813	true,
		1814	false,
		1815	true,
		1816	false,
		1817	true,
		1818	false,
		1819	true,
		1820	false,
		1821	true,
		1822	false,
		1823	false,
		1824	true,
		1825	false,
		1826	true,
		1827	true,
		1828	false,
		1829	false,
		1830	true,
		1831	false,
		1832	false,
		1833	false,
		1834	true,
		1835	true,
		1836	false,
		1837	false,
		1838	false,
		1839	false,
		1840	false,
		1841	true,
		1842	false,
		1843	true,
		1844	false,
		1845	false,
		1846	false,
		1847	};
		1848	}
		1849
		1850	Vector512Bool c_ret_vector_512_bool(void) {
		1851	return (Vector512Bool){
		1852	false,
		1853	true,
		1854	false,
		1855	false,
		1856	false,
		1857	true,
		1858	false,
		1859	false,
		1860	false,
		1861	true,
		1862	false,
		1863	false,
		1864	false,
		1865	true,
		1866	false,
		1867	true,
		1868	false,
		1869	false,
		1870	false,
		1871	false,
		1872	false,
		1873	false,
		1874	true,
		1875	true,
		1876	false,
		1877	false,
		1878	false,
		1879	false,
		1880	true,
		1881	true,
		1882	false,
		1883	true,
		1884	false,
		1885	true,
		1886	true,
		1887	true,
		1888	false,
		1889	false,
		1890	true,
		1891	true,
		1892	false,
		1893	false,
		1894	false,
		1895	false,
		1896	false,
		1897	true,
		1898	false,
		1899	true,
		1900	true,
		1901	false,
		1902	true,
		1903	true,
		1904	true,
		1905	true,
		1906	false,
		1907	false,
		1908	false,
		1909	true,
		1910	true,
		1911	false,
		1912	false,
		1913	false,
		1914	false,
		1915	true,
		1916	true,
		1917	true,
		1918	true,
		1919	true,
		1920	false,
		1921	false,
		1922	false,
		1923	false,
		1924	false,
		1925	true,
		1926	false,
		1927	true,
		1928	false,
		1929	false,
		1930	true,
		1931	true,
		1932	false,
		1933	false,
		1934	false,
		1935	true,
		1936	false,
		1937	true,
		1938	true,
		1939	true,
		1940	false,
		1941	true,
		1942	false,
		1943	false,
		1944	true,
		1945	true,
		1946	false,
		1947	true,
		1948	true,
		1949	false,
		1950	true,
		1951	false,
		1952	true,
		1953	true,
		1954	false,
		1955	true,
		1956	true,
		1957	false,
		1958	false,
		1959	false,
		1960	true,
		1961	false,
		1962	false,
		1963	false,
		1964	true,
		1965	true,
		1966	true,
		1967	false,
		1968	true,
		1969	false,
		1970	true,
		1971	false,
		1972	true,
		1973	true,
		1974	false,
		1975	true,
		1976	false,
		1977	true,
		1978	true,
		1979	true,
		1980	false,
		1981	true,
		1982	false,
		1983	false,
		1984	false,
		1985	false,
		1986	false,
		1987	false,
		1988	true,
		1989	false,
		1990	true,
		1991	false,
		1992	true,
		1993	true,
		1994	false,
		1995	true,
		1996	false,
		1997	false,
		1998	true,
		1999	false,
		2000	false,
		2001	true,
		2002	false,
		2003	true,
		2004	false,
		2005	true,
		2006	false,
		2007	false,
		2008	true,
		2009	false,
		2010	true,
		2011	true,
		2012	true,
		2013	false,
		2014	false,
		2015	true,
		2016	false,
		2017	false,
		2018	false,
		2019	true,
		2020	true,
		2021	true,
		2022	false,
		2023	true,
		2024	false,
		2025	false,
		2026	false,
		2027	false,
		2028	false,
		2029	true,
		2030	true,
		2031	false,
		2032	false,
		2033	true,
		2034	false,
		2035	false,
		2036	false,
		2037	false,
		2038	false,
		2039	true,
		2040	true,
		2041	false,
		2042	false,
		2043	false,
		2044	false,
		2045	false,
		2046	false,
		2047	true,
		2048	true,
		2049	false,
		2050	true,
		2051	true,
		2052	true,
		2053	true,
		2054	true,
		2055	true,
		2056	false,
		2057	false,
		2058	false,
		2059	false,
		2060	true,
		2061	false,
		2062	true,
		2063	true,
		2064	true,
		2065	true,
		2066	false,
		2067	false,
		2068	false,
		2069	true,
		2070	true,
		2071	false,
		2072	true,
		2073	true,
		2074	false,
		2075	false,
		2076	false,
		2077	true,
		2078	true,
		2079	true,
		2080	true,
		2081	false,
		2082	true,
		2083	false,
		2084	true,
		2085	true,
		2086	true,
		2087	true,
		2088	false,
		2089	true,
		2090	false,
		2091	true,
		2092	false,
		2093	true,
		2094	false,
		2095	false,
		2096	false,
		2097	true,
		2098	true,
		2099	false,
		2100	true,
		2101	false,
		2102	false,
		2103	false,
		2104	true,
		2105	true,
		2106	true,
		2107	true,
		2108	true,
		2109	false,
		2110	true,
		2111	true,
		2112	true,
		2113	true,
		2114	false,
		2115	true,
		2116	false,
		2117	false,
		2118	true,
		2119	false,
		2120	true,
		2121	false,
		2122	false,
		2123	true,
		2124	true,
		2125	false,
		2126	true,
		2127	false,
		2128	false,
		2129	true,
		2130	false,
		2131	false,
		2132	true,
		2133	true,
		2134	true,
		2135	false,
		2136	false,
		2137	true,
		2138	true,
		2139	true,
		2140	false,
		2141	false,
		2142	false,
		2143	false,
		2144	false,
		2145	false,
		2146	true,
		2147	false,
		2148	true,
		2149	false,
		2150	true,
		2151	true,
		2152	false,
		2153	false,
		2154	false,
		2155	false,
		2156	true,
		2157	true,
		2158	true,
		2159	true,
		2160	true,
		2161	false,
		2162	true,
		2163	true,
		2164	true,
		2165	true,
		2166	true,
		2167	false,
		2168	true,
		2169	true,
		2170	true,
		2171	false,
		2172	true,
		2173	false,
		2174	true,
		2175	true,
		2176	true,
		2177	false,
		2178	false,
		2179	true,
		2180	true,
		2181	true,
		2182	false,
		2183	false,
		2184	true,
		2185	true,
		2186	false,
		2187	true,
		2188	true,
		2189	true,
		2190	true,
		2191	true,
		2192	true,
		2193	false,
		2194	true,
		2195	false,
		2196	true,
		2197	false,
		2198	false,
		2199	false,
		2200	false,
		2201	true,
		2202	true,
		2203	true,
		2204	true,
		2205	false,
		2206	true,
		2207	false,
		2208	true,
		2209	true,
		2210	false,
		2211	true,
		2212	false,
		2213	false,
		2214	true,
		2215	false,
		2216	false,
		2217	false,
		2218	false,
		2219	false,
		2220	false,
		2221	false,
		2222	true,
		2223	false,
		2224	true,
		2225	true,
		2226	false,
		2227	false,
		2228	true,
		2229	false,
		2230	false,
		2231	true,
		2232	false,
		2233	false,
		2234	true,
		2235	false,
		2236	false,
		2237	false,
		2238	false,
		2239	true,
		2240	true,
		2241	true,
		2242	true,
		2243	true,
		2244	true,
		2245	true,
		2246	false,
		2247	true,
		2248	true,
		2249	false,
		2250	false,
		2251	false,
		2252	true,
		2253	false,
		2254	true,
		2255	true,
		2256	false,
		2257	true,
		2258	true,
		2259	true,
		2260	true,
		2261	false,
		2262	false,
		2263	false,
		2264	true,
		2265	true,
		2266	false,
		2267	true,
		2268	false,
		2269	true,
		2270	false,
		2271	false,
		2272	false,
		2273	false,
		2274	true,
		2275	true,
		2276	true,
		2277	false,
		2278	true,
		2279	false,
		2280	false,
		2281	false,
		2282	true,
		2283	true,
		2284	false,
		2285	true,
		2286	false,
		2287	false,
		2288	true,
		2289	true,
		2290	true,
		2291	true,
		2292	true,
		2293	true,
		2294	false,
		2295	false,
		2296	false,
		2297	true,
		2298	true,
		2299	true,
		2300	false,
		2301	false,
		2302	false,
		2303	false,
		2304	false,
		2305	false,
		2306	false,
		2307	false,
		2308	false,
		2309	false,
		2310	false,
		2311	true,
		2312	false,
		2313	false,
		2314	false,
		2315	true,
		2316	false,
		2317	false,
		2318	false,
		2319	false,
		2320	true,
		2321	true,
		2322	true,
		2323	true,
		2324	true,
		2325	false,
		2326	false,
		2327	true,
		2328	true,
		2329	true,
		2330	false,
		2331	true,
		2332	true,
		2333	true,
		2334	false,
		2335	true,
		2336	false,
		2337	true,
		2338	false,
		2339	true,
		2340	false,
		2341	true,
		2342	true,
		2343	true,
		2344	true,
		2345	false,
		2346	true,
		2347	true,
		2348	false,
		2349	true,
		2350	false,
		2351	false,
		2352	false,
		2353	false,
		2354	false,
		2355	false,
		2356	false,
		2357	false,
		2358	false,
		2359	true,
		2360	true,
		2361	false,
		2362	true,
		2363	false,
		2364	};
		2365	}
		2366
		2367	void zig_vector_2_bool(Vector2Bool vec);
		2368	void zig_vector_4_bool(Vector4Bool vec);
		2369	void zig_vector_8_bool(Vector8Bool vec);
		2370	void zig_vector_16_bool(Vector16Bool vec);
		2371	void zig_vector_32_bool(Vector32Bool vec);
		2372	void zig_vector_64_bool(Vector64Bool vec);
		2373	void zig_vector_128_bool(Vector128Bool vec);
		2374	void zig_vector_256_bool(Vector256Bool vec);
		2375	void zig_vector_512_bool(Vector512Bool vec);
		2376
		2377	Vector2Bool zig_ret_vector_2_bool(void);
		2378	Vector4Bool zig_ret_vector_4_bool(void);
		2379	Vector8Bool zig_ret_vector_8_bool(void);
		2380	Vector16Bool zig_ret_vector_16_bool(void);
		2381	Vector32Bool zig_ret_vector_32_bool(void);
		2382	Vector64Bool zig_ret_vector_64_bool(void);
		2383	Vector128Bool zig_ret_vector_128_bool(void);
		2384	Vector256Bool zig_ret_vector_256_bool(void);
		2385	Vector512Bool zig_ret_vector_512_bool(void);
		2386
		2387	#endif
		2388
239	typedef struct Vector3 {	2389	typedef struct Vector3 {
240	float x;	2390	float x;
241	float y;	2391	float y;
...	@@ -450,6 +2600,2107 @@ void run_c_tests(void) {	...	@@ -450,6 +2600,2107 @@ void run_c_tests(void) {
450	assert_or_panic(zig_ret_i32() == -1);	2600	assert_or_panic(zig_ret_i32() == -1);
451	assert_or_panic(zig_ret_i64() == -1);	2601	assert_or_panic(zig_ret_i64() == -1);
452	}	2602	}
		2603
		2604	#if defined(ZIG_BACKEND_STAGE2_X86_64) \|\| defined(ZIG_PPC32)
		2605	{
		2606	zig_vector_2_bool((Vector2Bool){
		2607	false,
		2608	true,
		2609	});
		2610
		2611	Vector2Bool vec = zig_ret_vector_2_bool();
		2612	assert_or_panic(vec[0] == false);
		2613	assert_or_panic(vec[1] == false);
		2614	}
		2615	{
		2616	zig_vector_4_bool((Vector4Bool){
		2617	false,
		2618	false,
		2619	false,
		2620	false,
		2621	});
		2622
		2623	Vector4Bool vec = zig_ret_vector_4_bool();
		2624	assert_or_panic(vec[0] == false);
		2625	assert_or_panic(vec[1] == true);
		2626	assert_or_panic(vec[2] == true);
		2627	assert_or_panic(vec[3] == true);
		2628	}
		2629	{
		2630	zig_vector_8_bool((Vector8Bool){
		2631	true,
		2632	true,
		2633	false,
		2634	true,
		2635	false,
		2636	true,
		2637	true,
		2638	false,
		2639	});
		2640
		2641	Vector8Bool vec = zig_ret_vector_8_bool();
		2642	assert_or_panic(vec[0] == false);
		2643	assert_or_panic(vec[1] == false);
		2644	assert_or_panic(vec[2] == false);
		2645	assert_or_panic(vec[3] == false);
		2646	assert_or_panic(vec[4] == true);
		2647	assert_or_panic(vec[5] == false);
		2648	assert_or_panic(vec[6] == false);
		2649	assert_or_panic(vec[7] == false);
		2650	}
		2651	{
		2652	zig_vector_16_bool((Vector16Bool){
		2653	true,
		2654	false,
		2655	true,
		2656	true,
		2657	true,
		2658	false,
		2659	false,
		2660	false,
		2661	true,
		2662	true,
		2663	true,
		2664	true,
		2665	false,
		2666	false,
		2667	false,
		2668	true,
		2669	});
		2670
		2671	Vector16Bool vec = zig_ret_vector_16_bool();
		2672	assert_or_panic(vec[0] == false);
		2673	assert_or_panic(vec[1] == true);
		2674	assert_or_panic(vec[2] == false);
		2675	assert_or_panic(vec[3] == false);
		2676	assert_or_panic(vec[4] == false);
		2677	assert_or_panic(vec[5] == true);
		2678	assert_or_panic(vec[6] == false);
		2679	assert_or_panic(vec[7] == false);
		2680	assert_or_panic(vec[8] == true);
		2681	assert_or_panic(vec[9] == false);
		2682	assert_or_panic(vec[10] == false);
		2683	assert_or_panic(vec[11] == false);
		2684	assert_or_panic(vec[12] == false);
		2685	assert_or_panic(vec[13] == true);
		2686	assert_or_panic(vec[14] == false);
		2687	assert_or_panic(vec[15] == false);
		2688	}
		2689	{
		2690	zig_vector_32_bool((Vector32Bool){
		2691	false,
		2692	false,
		2693	false,
		2694	true,
		2695	true,
		2696	false,
		2697	false,
		2698	true,
		2699	false,
		2700	true,
		2701	true,
		2702	true,
		2703	false,
		2704	false,
		2705	true,
		2706	true,
		2707	true,
		2708	true,
		2709	true,
		2710	false,
		2711	true,
		2712	true,
		2713	true,
		2714	false,
		2715	false,
		2716	true,
		2717	true,
		2718	false,
		2719	true,
		2720	true,
		2721	false,
		2722	true,
		2723	});
		2724
		2725	Vector32Bool vec = zig_ret_vector_32_bool();
		2726	assert_or_panic(vec[0] == false);
		2727	assert_or_panic(vec[1] == true);
		2728	assert_or_panic(vec[2] == false);
		2729	assert_or_panic(vec[3] == false);
		2730	assert_or_panic(vec[4] == true);
		2731	assert_or_panic(vec[5] == false);
		2732	assert_or_panic(vec[6] == true);
		2733	assert_or_panic(vec[7] == true);
		2734	assert_or_panic(vec[8] == true);
		2735	assert_or_panic(vec[9] == true);
		2736	assert_or_panic(vec[10] == true);
		2737	assert_or_panic(vec[11] == true);
		2738	assert_or_panic(vec[12] == false);
		2739	assert_or_panic(vec[13] == false);
		2740	assert_or_panic(vec[14] == false);
		2741	assert_or_panic(vec[15] == false);
		2742	assert_or_panic(vec[16] == false);
		2743	assert_or_panic(vec[17] == false);
		2744	assert_or_panic(vec[18] == true);
		2745	assert_or_panic(vec[19] == true);
		2746	assert_or_panic(vec[20] == true);
		2747	assert_or_panic(vec[21] == false);
		2748	assert_or_panic(vec[22] == true);
		2749	assert_or_panic(vec[23] == false);
		2750	assert_or_panic(vec[24] == true);
		2751	assert_or_panic(vec[25] == false);
		2752	assert_or_panic(vec[26] == false);
		2753	assert_or_panic(vec[27] == true);
		2754	assert_or_panic(vec[28] == false);
		2755	assert_or_panic(vec[29] == false);
		2756	assert_or_panic(vec[30] == true);
		2757	assert_or_panic(vec[31] == true);
		2758	}
		2759	{
		2760	zig_vector_64_bool((Vector64Bool){
		2761	true,
		2762	true,
		2763	false,
		2764	true,
		2765	false,
		2766	true,
		2767	false,
		2768	false,
		2769	true,
		2770	true,
		2771	true,
		2772	true,
		2773	true,
		2774	true,
		2775	true,
		2776	false,
		2777	false,
		2778	true,
		2779	true,
		2780	false,
		2781	true,
		2782	true,
		2783	true,
		2784	true,
		2785	false,
		2786	false,
		2787	true,
		2788	false,
		2789	false,
		2790	true,
		2791	false,
		2792	true,
		2793	false,
		2794	true,
		2795	true,
		2796	false,
		2797	true,
		2798	true,
		2799	false,
		2800	false,
		2801	true,
		2802	true,
		2803	true,
		2804	true,
		2805	true,
		2806	false,
		2807	true,
		2808	false,
		2809	false,
		2810	false,
		2811	false,
		2812	false,
		2813	true,
		2814	false,
		2815	false,
		2816	true,
		2817	true,
		2818	false,
		2819	false,
		2820	false,
		2821	true,
		2822	true,
		2823	true,
		2824	true,
		2825	});
		2826
		2827	Vector64Bool vec = zig_ret_vector_64_bool();
		2828	assert_or_panic(vec[0] == true);
		2829	assert_or_panic(vec[1] == false);
		2830	assert_or_panic(vec[2] == true);
		2831	assert_or_panic(vec[3] == false);
		2832	assert_or_panic(vec[4] == false);
		2833	assert_or_panic(vec[5] == true);
		2834	assert_or_panic(vec[6] == false);
		2835	assert_or_panic(vec[7] == true);
		2836	assert_or_panic(vec[8] == true);
		2837	assert_or_panic(vec[9] == false);
		2838	assert_or_panic(vec[10] == true);
		2839	assert_or_panic(vec[11] == false);
		2840	assert_or_panic(vec[12] == true);
		2841	assert_or_panic(vec[13] == false);
		2842	assert_or_panic(vec[14] == false);
		2843	assert_or_panic(vec[15] == true);
		2844	assert_or_panic(vec[16] == false);
		2845	assert_or_panic(vec[17] == false);
		2846	assert_or_panic(vec[18] == true);
		2847	assert_or_panic(vec[19] == true);
		2848	assert_or_panic(vec[20] == false);
		2849	assert_or_panic(vec[21] == false);
		2850	assert_or_panic(vec[22] == true);
		2851	assert_or_panic(vec[23] == false);
		2852	assert_or_panic(vec[24] == false);
		2853	assert_or_panic(vec[25] == true);
		2854	assert_or_panic(vec[26] == true);
		2855	assert_or_panic(vec[27] == true);
		2856	assert_or_panic(vec[28] == true);
		2857	assert_or_panic(vec[29] == true);
		2858	assert_or_panic(vec[30] == false);
		2859	assert_or_panic(vec[31] == false);
		2860	assert_or_panic(vec[32] == true);
		2861	assert_or_panic(vec[33] == true);
		2862	assert_or_panic(vec[34] == true);
		2863	assert_or_panic(vec[35] == true);
		2864	assert_or_panic(vec[36] == false);
		2865	assert_or_panic(vec[37] == true);
		2866	assert_or_panic(vec[38] == false);
		2867	assert_or_panic(vec[39] == true);
		2868	assert_or_panic(vec[40] == true);
		2869	assert_or_panic(vec[41] == true);
		2870	assert_or_panic(vec[42] == true);
		2871	assert_or_panic(vec[43] == true);
		2872	assert_or_panic(vec[44] == false);
		2873	assert_or_panic(vec[45] == false);
		2874	assert_or_panic(vec[46] == false);
		2875	assert_or_panic(vec[47] == true);
		2876	assert_or_panic(vec[48] == true);
		2877	assert_or_panic(vec[49] == true);
		2878	assert_or_panic(vec[50] == false);
		2879	assert_or_panic(vec[51] == true);
		2880	assert_or_panic(vec[52] == true);
		2881	assert_or_panic(vec[53] == true);
		2882	assert_or_panic(vec[54] == false);
		2883	assert_or_panic(vec[55] == false);
		2884	assert_or_panic(vec[56] == false);
		2885	assert_or_panic(vec[57] == true);
		2886	assert_or_panic(vec[58] == false);
		2887	assert_or_panic(vec[59] == false);
		2888	assert_or_panic(vec[60] == true);
		2889	assert_or_panic(vec[61] == false);
		2890	assert_or_panic(vec[62] == true);
		2891	assert_or_panic(vec[63] == false);
		2892	}
		2893	{
		2894	zig_vector_128_bool((Vector128Bool){
		2895	true,
		2896	true,
		2897	false,
		2898	true,
		2899	true,
		2900	false,
		2901	false,
		2902	true,
		2903	true,
		2904	true,
		2905	true,
		2906	true,
		2907	false,
		2908	false,
		2909	false,
		2910	true,
		2911	false,
		2912	true,
		2913	false,
		2914	false,
		2915	true,
		2916	false,
		2917	true,
		2918	false,
		2919	false,
		2920	false,
		2921	true,
		2922	false,
		2923	true,
		2924	true,
		2925	false,
		2926	true,
		2927	false,
		2928	true,
		2929	true,
		2930	false,
		2931	false,
		2932	false,
		2933	false,
		2934	true,
		2935	true,
		2936	false,
		2937	true,
		2938	false,
		2939	false,
		2940	true,
		2941	false,
		2942	false,
		2943	true,
		2944	true,
		2945	false,
		2946	false,
		2947	true,
		2948	false,
		2949	false,
		2950	true,
		2951	true,
		2952	true,
		2953	true,
		2954	true,
		2955	true,
		2956	true,
		2957	true,
		2958	false,
		2959	false,
		2960	true,
		2961	false,
		2962	true,
		2963	true,
		2964	true,
		2965	true,
		2966	false,
		2967	false,
		2968	false,
		2969	true,
		2970	true,
		2971	false,
		2972	true,
		2973	true,
		2974	true,
		2975	true,
		2976	false,
		2977	true,
		2978	true,
		2979	true,
		2980	true,
		2981	true,
		2982	true,
		2983	false,
		2984	true,
		2985	true,
		2986	true,
		2987	true,
		2988	true,
		2989	true,
		2990	false,
		2991	false,
		2992	false,
		2993	true,
		2994	true,
		2995	true,
		2996	true,
		2997	true,
		2998	true,
		2999	true,
		3000	false,
		3001	false,
		3002	false,
		3003	false,
		3004	false,
		3005	true,
		3006	true,
		3007	true,
		3008	false,
		3009	false,
		3010	false,
		3011	false,
		3012	false,
		3013	true,
		3014	false,
		3015	false,
		3016	false,
		3017	false,
		3018	true,
		3019	true,
		3020	false,
		3021	true,
		3022	false,
		3023	});
		3024
		3025	Vector128Bool vec = zig_ret_vector_128_bool();
		3026	assert_or_panic(vec[0] == true);
		3027	assert_or_panic(vec[1] == true);
		3028	assert_or_panic(vec[2] == false);
		3029	assert_or_panic(vec[3] == false);
		3030	assert_or_panic(vec[4] == false);
		3031	assert_or_panic(vec[5] == true);
		3032	assert_or_panic(vec[6] == true);
		3033	assert_or_panic(vec[7] == false);
		3034	assert_or_panic(vec[8] == false);
		3035	assert_or_panic(vec[9] == true);
		3036	assert_or_panic(vec[10] == false);
		3037	assert_or_panic(vec[11] == false);
		3038	assert_or_panic(vec[12] == false);
		3039	assert_or_panic(vec[13] == true);
		3040	assert_or_panic(vec[14] == false);
		3041	assert_or_panic(vec[15] == true);
		3042	assert_or_panic(vec[16] == true);
		3043	assert_or_panic(vec[17] == false);
		3044	assert_or_panic(vec[18] == false);
		3045	assert_or_panic(vec[19] == true);
		3046	assert_or_panic(vec[20] == true);
		3047	assert_or_panic(vec[21] == true);
		3048	assert_or_panic(vec[22] == true);
		3049	assert_or_panic(vec[23] == true);
		3050	assert_or_panic(vec[24] == false);
		3051	assert_or_panic(vec[25] == false);
		3052	assert_or_panic(vec[26] == true);
		3053	assert_or_panic(vec[27] == true);
		3054	assert_or_panic(vec[28] == true);
		3055	assert_or_panic(vec[29] == false);
		3056	assert_or_panic(vec[30] == false);
		3057	assert_or_panic(vec[31] == true);
		3058	assert_or_panic(vec[32] == true);
		3059	assert_or_panic(vec[33] == false);
		3060	assert_or_panic(vec[34] == true);
		3061	assert_or_panic(vec[35] == true);
		3062	assert_or_panic(vec[36] == true);
		3063	assert_or_panic(vec[37] == false);
		3064	assert_or_panic(vec[38] == true);
		3065	assert_or_panic(vec[39] == true);
		3066	assert_or_panic(vec[40] == true);
		3067	assert_or_panic(vec[41] == false);
		3068	assert_or_panic(vec[42] == true);
		3069	assert_or_panic(vec[43] == true);
		3070	assert_or_panic(vec[44] == false);
		3071	assert_or_panic(vec[45] == false);
		3072	assert_or_panic(vec[46] == false);
		3073	assert_or_panic(vec[47] == true);
		3074	assert_or_panic(vec[48] == false);
		3075	assert_or_panic(vec[49] == false);
		3076	assert_or_panic(vec[50] == false);
		3077	assert_or_panic(vec[51] == false);
		3078	assert_or_panic(vec[52] == true);
		3079	assert_or_panic(vec[53] == false);
		3080	assert_or_panic(vec[54] == true);
		3081	assert_or_panic(vec[55] == false);
		3082	assert_or_panic(vec[56] == true);
		3083	assert_or_panic(vec[57] == false);
		3084	assert_or_panic(vec[58] == false);
		3085	assert_or_panic(vec[59] == true);
		3086	assert_or_panic(vec[60] == true);
		3087	assert_or_panic(vec[61] == true);
		3088	assert_or_panic(vec[62] == true);
		3089	assert_or_panic(vec[63] == true);
		3090	assert_or_panic(vec[64] == false);
		3091	assert_or_panic(vec[65] == false);
		3092	assert_or_panic(vec[66] == false);
		3093	assert_or_panic(vec[67] == true);
		3094	assert_or_panic(vec[68] == true);
		3095	assert_or_panic(vec[69] == false);
		3096	assert_or_panic(vec[70] == true);
		3097	assert_or_panic(vec[71] == true);
		3098	assert_or_panic(vec[72] == false);
		3099	assert_or_panic(vec[73] == true);
		3100	assert_or_panic(vec[74] == true);
		3101	assert_or_panic(vec[75] == false);
		3102	assert_or_panic(vec[76] == false);
		3103	assert_or_panic(vec[77] == true);
		3104	assert_or_panic(vec[78] == false);
		3105	assert_or_panic(vec[79] == true);
		3106	assert_or_panic(vec[80] == false);
		3107	assert_or_panic(vec[81] == false);
		3108	assert_or_panic(vec[82] == true);
		3109	assert_or_panic(vec[83] == true);
		3110	assert_or_panic(vec[84] == false);
		3111	assert_or_panic(vec[85] == true);
		3112	assert_or_panic(vec[86] == false);
		3113	assert_or_panic(vec[87] == false);
		3114	assert_or_panic(vec[88] == true);
		3115	assert_or_panic(vec[89] == true);
		3116	assert_or_panic(vec[90] == true);
		3117	assert_or_panic(vec[91] == true);
		3118	assert_or_panic(vec[92] == true);
		3119	assert_or_panic(vec[93] == false);
		3120	assert_or_panic(vec[94] == false);
		3121	assert_or_panic(vec[95] == true);
		3122	assert_or_panic(vec[96] == false);
		3123	assert_or_panic(vec[97] == false);
		3124	assert_or_panic(vec[98] == true);
		3125	assert_or_panic(vec[99] == true);
		3126	assert_or_panic(vec[100] == true);
		3127	assert_or_panic(vec[101] == true);
		3128	assert_or_panic(vec[102] == true);
		3129	assert_or_panic(vec[103] == true);
		3130	assert_or_panic(vec[104] == true);
		3131	assert_or_panic(vec[105] == false);
		3132	assert_or_panic(vec[106] == false);
		3133	assert_or_panic(vec[107] == true);
		3134	assert_or_panic(vec[108] == false);
		3135	assert_or_panic(vec[109] == false);
		3136	assert_or_panic(vec[110] == true);
		3137	assert_or_panic(vec[111] == false);
		3138	assert_or_panic(vec[112] == false);
		3139	assert_or_panic(vec[113] == true);
		3140	assert_or_panic(vec[114] == false);
		3141	assert_or_panic(vec[115] == false);
		3142	assert_or_panic(vec[116] == false);
		3143	assert_or_panic(vec[117] == false);
		3144	assert_or_panic(vec[118] == false);
		3145	assert_or_panic(vec[119] == false);
		3146	assert_or_panic(vec[120] == true);
		3147	assert_or_panic(vec[121] == true);
		3148	assert_or_panic(vec[122] == true);
		3149	assert_or_panic(vec[123] == false);
		3150	assert_or_panic(vec[124] == true);
		3151	assert_or_panic(vec[125] == false);
		3152	assert_or_panic(vec[126] == false);
		3153	assert_or_panic(vec[127] == true);
		3154	}
		3155	{
		3156	zig_vector_256_bool((Vector256Bool){
		3157	false,
		3158	false,
		3159	false,
		3160	false,
		3161	true,
		3162	true,
		3163	false,
		3164	false,
		3165	false,
		3166	true,
		3167	true,
		3168	false,
		3169	true,
		3170	false,
		3171	false,
		3172	false,
		3173	false,
		3174	true,
		3175	true,
		3176	true,
		3177	false,
		3178	true,
		3179	true,
		3180	false,
		3181	true,
		3182	false,
		3183	false,
		3184	true,
		3185	true,
		3186	true,
		3187	false,
		3188	true,
		3189	false,
		3190	true,
		3191	false,
		3192	false,
		3193	false,
		3194	true,
		3195	false,
		3196	false,
		3197	true,
		3198	true,
		3199	false,
		3200	true,
		3201	true,
		3202	false,
		3203	true,
		3204	false,
		3205	true,
		3206	false,
		3207	true,
		3208	false,
		3209	true,
		3210	true,
		3211	true,
		3212	false,
		3213	false,
		3214	true,
		3215	true,
		3216	false,
		3217	false,
		3218	true,
		3219	true,
		3220	false,
		3221	false,
		3222	false,
		3223	true,
		3224	true,
		3225	false,
		3226	true,
		3227	false,
		3228	true,
		3229	false,
		3230	true,
		3231	false,
		3232	false,
		3233	true,
		3234	false,
		3235	false,
		3236	false,
		3237	false,
		3238	false,
		3239	true,
		3240	false,
		3241	false,
		3242	false,
		3243	true,
		3244	true,
		3245	true,
		3246	false,
		3247	true,
		3248	false,
		3249	true,
		3250	false,
		3251	true,
		3252	true,
		3253	true,
		3254	true,
		3255	false,
		3256	true,
		3257	false,
		3258	true,
		3259	true,
		3260	false,
		3261	false,
		3262	true,
		3263	false,
		3264	true,
		3265	false,
		3266	false,
		3267	false,
		3268	false,
		3269	false,
		3270	false,
		3271	false,
		3272	false,
		3273	false,
		3274	false,
		3275	false,
		3276	false,
		3277	false,
		3278	false,
		3279	true,
		3280	true,
		3281	false,
		3282	false,
		3283	false,
		3284	true,
		3285	true,
		3286	true,
		3287	true,
		3288	false,
		3289	false,
		3290	false,
		3291	true,
		3292	true,
		3293	false,
		3294	false,
		3295	true,
		3296	true,
		3297	true,
		3298	true,
		3299	true,
		3300	false,
		3301	true,
		3302	true,
		3303	true,
		3304	false,
		3305	false,
		3306	false,
		3307	false,
		3308	false,
		3309	false,
		3310	false,
		3311	true,
		3312	false,
		3313	false,
		3314	false,
		3315	true,
		3316	true,
		3317	false,
		3318	true,
		3319	false,
		3320	false,
		3321	false,
		3322	true,
		3323	false,
		3324	true,
		3325	false,
		3326	false,
		3327	false,
		3328	false,
		3329	true,
		3330	true,
		3331	true,
		3332	true,
		3333	true,
		3334	true,
		3335	false,
		3336	true,
		3337	true,
		3338	false,
		3339	true,
		3340	false,
		3341	true,
		3342	false,
		3343	true,
		3344	false,
		3345	true,
		3346	false,
		3347	false,
		3348	false,
		3349	false,
		3350	true,
		3351	true,
		3352	true,
		3353	false,
		3354	false,
		3355	true,
		3356	false,
		3357	false,
		3358	true,
		3359	true,
		3360	false,
		3361	true,
		3362	false,
		3363	true,
		3364	false,
		3365	false,
		3366	false,
		3367	true,
		3368	true,
		3369	false,
		3370	false,
		3371	false,
		3372	true,
		3373	false,
		3374	true,
		3375	true,
		3376	true,
		3377	false,
		3378	true,
		3379	false,
		3380	true,
		3381	false,
		3382	false,
		3383	false,
		3384	true,
		3385	true,
		3386	false,
		3387	false,
		3388	false,
		3389	false,
		3390	false,
		3391	true,
		3392	false,
		3393	false,
		3394	false,
		3395	true,
		3396	false,
		3397	true,
		3398	true,
		3399	true,
		3400	false,
		3401	false,
		3402	true,
		3403	false,
		3404	false,
		3405	false,
		3406	true,
		3407	false,
		3408	false,
		3409	true,
		3410	true,
		3411	true,
		3412	true,
		3413	});
		3414
		3415	Vector256Bool vec = zig_ret_vector_256_bool();
		3416	assert_or_panic(vec[0] == true);
		3417	assert_or_panic(vec[1] == true);
		3418	assert_or_panic(vec[2] == true);
		3419	assert_or_panic(vec[3] == false);
		3420	assert_or_panic(vec[4] == true);
		3421	assert_or_panic(vec[5] == false);
		3422	assert_or_panic(vec[6] == false);
		3423	assert_or_panic(vec[7] == true);
		3424	assert_or_panic(vec[8] == false);
		3425	assert_or_panic(vec[9] == false);
		3426	assert_or_panic(vec[10] == false);
		3427	assert_or_panic(vec[11] == false);
		3428	assert_or_panic(vec[12] == false);
		3429	assert_or_panic(vec[13] == false);
		3430	assert_or_panic(vec[14] == false);
		3431	assert_or_panic(vec[15] == false);
		3432	assert_or_panic(vec[16] == true);
		3433	assert_or_panic(vec[17] == false);
		3434	assert_or_panic(vec[18] == true);
		3435	assert_or_panic(vec[19] == false);
		3436	assert_or_panic(vec[20] == false);
		3437	assert_or_panic(vec[21] == true);
		3438	assert_or_panic(vec[22] == true);
		3439	assert_or_panic(vec[23] == false);
		3440	assert_or_panic(vec[24] == false);
		3441	assert_or_panic(vec[25] == true);
		3442	assert_or_panic(vec[26] == true);
		3443	assert_or_panic(vec[27] == false);
		3444	assert_or_panic(vec[28] == true);
		3445	assert_or_panic(vec[29] == true);
		3446	assert_or_panic(vec[30] == true);
		3447	assert_or_panic(vec[31] == false);
		3448	assert_or_panic(vec[32] == true);
		3449	assert_or_panic(vec[33] == false);
		3450	assert_or_panic(vec[34] == true);
		3451	assert_or_panic(vec[35] == false);
		3452	assert_or_panic(vec[36] == true);
		3453	assert_or_panic(vec[37] == false);
		3454	assert_or_panic(vec[38] == true);
		3455	assert_or_panic(vec[39] == false);
		3456	assert_or_panic(vec[40] == false);
		3457	assert_or_panic(vec[41] == false);
		3458	assert_or_panic(vec[42] == true);
		3459	assert_or_panic(vec[43] == true);
		3460	assert_or_panic(vec[44] == true);
		3461	assert_or_panic(vec[45] == false);
		3462	assert_or_panic(vec[46] == false);
		3463	assert_or_panic(vec[47] == false);
		3464	assert_or_panic(vec[48] == true);
		3465	assert_or_panic(vec[49] == false);
		3466	assert_or_panic(vec[50] == true);
		3467	assert_or_panic(vec[51] == false);
		3468	assert_or_panic(vec[52] == true);
		3469	assert_or_panic(vec[53] == false);
		3470	assert_or_panic(vec[54] == true);
		3471	assert_or_panic(vec[55] == true);
		3472	assert_or_panic(vec[56] == false);
		3473	assert_or_panic(vec[57] == false);
		3474	assert_or_panic(vec[58] == false);
		3475	assert_or_panic(vec[59] == true);
		3476	assert_or_panic(vec[60] == true);
		3477	assert_or_panic(vec[61] == true);
		3478	assert_or_panic(vec[62] == false);
		3479	assert_or_panic(vec[63] == true);
		3480	assert_or_panic(vec[64] == false);
		3481	assert_or_panic(vec[65] == true);
		3482	assert_or_panic(vec[66] == false);
		3483	assert_or_panic(vec[67] == true);
		3484	assert_or_panic(vec[68] == true);
		3485	assert_or_panic(vec[69] == false);
		3486	assert_or_panic(vec[70] == true);
		3487	assert_or_panic(vec[71] == false);
		3488	assert_or_panic(vec[72] == true);
		3489	assert_or_panic(vec[73] == true);
		3490	assert_or_panic(vec[74] == false);
		3491	assert_or_panic(vec[75] == false);
		3492	assert_or_panic(vec[76] == false);
		3493	assert_or_panic(vec[77] == false);
		3494	assert_or_panic(vec[78] == false);
		3495	assert_or_panic(vec[79] == false);
		3496	assert_or_panic(vec[80] == false);
		3497	assert_or_panic(vec[81] == false);
		3498	assert_or_panic(vec[82] == false);
		3499	assert_or_panic(vec[83] == true);
		3500	assert_or_panic(vec[84] == false);
		3501	assert_or_panic(vec[85] == false);
		3502	assert_or_panic(vec[86] == false);
		3503	assert_or_panic(vec[87] == true);
		3504	assert_or_panic(vec[88] == false);
		3505	assert_or_panic(vec[89] == true);
		3506	assert_or_panic(vec[90] == true);
		3507	assert_or_panic(vec[91] == false);
		3508	assert_or_panic(vec[92] == false);
		3509	assert_or_panic(vec[93] == true);
		3510	assert_or_panic(vec[94] == true);
		3511	assert_or_panic(vec[95] == false);
		3512	assert_or_panic(vec[96] == false);
		3513	assert_or_panic(vec[97] == true);
		3514	assert_or_panic(vec[98] == false);
		3515	assert_or_panic(vec[99] == false);
		3516	assert_or_panic(vec[100] == false);
		3517	assert_or_panic(vec[101] == false);
		3518	assert_or_panic(vec[102] == false);
		3519	assert_or_panic(vec[103] == false);
		3520	assert_or_panic(vec[104] == false);
		3521	assert_or_panic(vec[105] == true);
		3522	assert_or_panic(vec[106] == true);
		3523	assert_or_panic(vec[107] == false);
		3524	assert_or_panic(vec[108] == true);
		3525	assert_or_panic(vec[109] == false);
		3526	assert_or_panic(vec[110] == true);
		3527	assert_or_panic(vec[111] == true);
		3528	assert_or_panic(vec[112] == false);
		3529	assert_or_panic(vec[113] == false);
		3530	assert_or_panic(vec[114] == false);
		3531	assert_or_panic(vec[115] == false);
		3532	assert_or_panic(vec[116] == false);
		3533	assert_or_panic(vec[117] == false);
		3534	assert_or_panic(vec[118] == false);
		3535	assert_or_panic(vec[119] == true);
		3536	assert_or_panic(vec[120] == true);
		3537	assert_or_panic(vec[121] == true);
		3538	assert_or_panic(vec[122] == false);
		3539	assert_or_panic(vec[123] == true);
		3540	assert_or_panic(vec[124] == true);
		3541	assert_or_panic(vec[125] == false);
		3542	assert_or_panic(vec[126] == false);
		3543	assert_or_panic(vec[127] == true);
		3544	assert_or_panic(vec[128] == true);
		3545	assert_or_panic(vec[129] == true);
		3546	assert_or_panic(vec[130] == true);
		3547	assert_or_panic(vec[131] == true);
		3548	assert_or_panic(vec[132] == false);
		3549	assert_or_panic(vec[133] == true);
		3550	assert_or_panic(vec[134] == true);
		3551	assert_or_panic(vec[135] == false);
		3552	assert_or_panic(vec[136] == false);
		3553	assert_or_panic(vec[137] == true);
		3554	assert_or_panic(vec[138] == true);
		3555	assert_or_panic(vec[139] == false);
		3556	assert_or_panic(vec[140] == true);
		3557	assert_or_panic(vec[141] == false);
		3558	assert_or_panic(vec[142] == true);
		3559	assert_or_panic(vec[143] == false);
		3560	assert_or_panic(vec[144] == true);
		3561	assert_or_panic(vec[145] == true);
		3562	assert_or_panic(vec[146] == true);
		3563	assert_or_panic(vec[147] == true);
		3564	assert_or_panic(vec[148] == false);
		3565	assert_or_panic(vec[149] == false);
		3566	assert_or_panic(vec[150] == false);
		3567	assert_or_panic(vec[151] == true);
		3568	assert_or_panic(vec[152] == false);
		3569	assert_or_panic(vec[153] == true);
		3570	assert_or_panic(vec[154] == false);
		3571	assert_or_panic(vec[155] == true);
		3572	assert_or_panic(vec[156] == true);
		3573	assert_or_panic(vec[157] == false);
		3574	assert_or_panic(vec[158] == true);
		3575	assert_or_panic(vec[159] == true);
		3576	assert_or_panic(vec[160] == true);
		3577	assert_or_panic(vec[161] == true);
		3578	assert_or_panic(vec[162] == true);
		3579	assert_or_panic(vec[163] == false);
		3580	assert_or_panic(vec[164] == false);
		3581	assert_or_panic(vec[165] == true);
		3582	assert_or_panic(vec[166] == false);
		3583	assert_or_panic(vec[167] == true);
		3584	assert_or_panic(vec[168] == true);
		3585	assert_or_panic(vec[169] == true);
		3586	assert_or_panic(vec[170] == true);
		3587	assert_or_panic(vec[171] == false);
		3588	assert_or_panic(vec[172] == true);
		3589	assert_or_panic(vec[173] == true);
		3590	assert_or_panic(vec[174] == true);
		3591	assert_or_panic(vec[175] == true);
		3592	assert_or_panic(vec[176] == true);
		3593	assert_or_panic(vec[177] == true);
		3594	assert_or_panic(vec[178] == true);
		3595	assert_or_panic(vec[179] == false);
		3596	assert_or_panic(vec[180] == true);
		3597	assert_or_panic(vec[181] == false);
		3598	assert_or_panic(vec[182] == false);
		3599	assert_or_panic(vec[183] == false);
		3600	assert_or_panic(vec[184] == true);
		3601	assert_or_panic(vec[185] == false);
		3602	assert_or_panic(vec[186] == true);
		3603	assert_or_panic(vec[187] == true);
		3604	assert_or_panic(vec[188] == false);
		3605	assert_or_panic(vec[189] == true);
		3606	assert_or_panic(vec[190] == false);
		3607	assert_or_panic(vec[191] == true);
		3608	assert_or_panic(vec[192] == false);
		3609	assert_or_panic(vec[193] == true);
		3610	assert_or_panic(vec[194] == false);
		3611	assert_or_panic(vec[195] == false);
		3612	assert_or_panic(vec[196] == true);
		3613	assert_or_panic(vec[197] == true);
		3614	assert_or_panic(vec[198] == true);
		3615	assert_or_panic(vec[199] == true);
		3616	assert_or_panic(vec[200] == true);
		3617	assert_or_panic(vec[201] == true);
		3618	assert_or_panic(vec[202] == true);
		3619	assert_or_panic(vec[203] == false);
		3620	assert_or_panic(vec[204] == true);
		3621	assert_or_panic(vec[205] == false);
		3622	assert_or_panic(vec[206] == false);
		3623	assert_or_panic(vec[207] == true);
		3624	assert_or_panic(vec[208] == true);
		3625	assert_or_panic(vec[209] == false);
		3626	assert_or_panic(vec[210] == false);
		3627	assert_or_panic(vec[211] == false);
		3628	assert_or_panic(vec[212] == true);
		3629	assert_or_panic(vec[213] == true);
		3630	assert_or_panic(vec[214] == true);
		3631	assert_or_panic(vec[215] == false);
		3632	assert_or_panic(vec[216] == false);
		3633	assert_or_panic(vec[217] == true);
		3634	assert_or_panic(vec[218] == true);
		3635	assert_or_panic(vec[219] == true);
		3636	assert_or_panic(vec[220] == true);
		3637	assert_or_panic(vec[221] == false);
		3638	assert_or_panic(vec[222] == true);
		3639	assert_or_panic(vec[223] == false);
		3640	assert_or_panic(vec[224] == true);
		3641	assert_or_panic(vec[225] == true);
		3642	assert_or_panic(vec[226] == true);
		3643	assert_or_panic(vec[227] == false);
		3644	assert_or_panic(vec[228] == false);
		3645	assert_or_panic(vec[229] == false);
		3646	assert_or_panic(vec[230] == false);
		3647	assert_or_panic(vec[231] == false);
		3648	assert_or_panic(vec[232] == true);
		3649	assert_or_panic(vec[233] == true);
		3650	assert_or_panic(vec[234] == false);
		3651	assert_or_panic(vec[235] == false);
		3652	assert_or_panic(vec[236] == false);
		3653	assert_or_panic(vec[237] == true);
		3654	assert_or_panic(vec[238] == true);
		3655	assert_or_panic(vec[239] == false);
		3656	assert_or_panic(vec[240] == true);
		3657	assert_or_panic(vec[241] == true);
		3658	assert_or_panic(vec[242] == true);
		3659	assert_or_panic(vec[243] == false);
		3660	assert_or_panic(vec[244] == true);
		3661	assert_or_panic(vec[245] == true);
		3662	assert_or_panic(vec[246] == false);
		3663	assert_or_panic(vec[247] == true);
		3664	assert_or_panic(vec[248] == false);
		3665	assert_or_panic(vec[249] == false);
		3666	assert_or_panic(vec[250] == true);
		3667	assert_or_panic(vec[251] == true);
		3668	assert_or_panic(vec[252] == false);
		3669	assert_or_panic(vec[253] == true);
		3670	assert_or_panic(vec[254] == false);
		3671	assert_or_panic(vec[255] == true);
		3672	}
		3673	{
		3674	zig_vector_512_bool((Vector512Bool){
		3675	false,
		3676	true,
		3677	true,
		3678	false,
		3679	true,
		3680	false,
		3681	true,
		3682	false,
		3683	false,
		3684	false,
		3685	false,
		3686	false,
		3687	true,
		3688	false,
		3689	true,
		3690	false,
		3691	false,
		3692	false,
		3693	true,
		3694	true,
		3695	true,
		3696	true,
		3697	false,
		3698	false,
		3699	false,
		3700	true,
		3701	true,
		3702	false,
		3703	true,
		3704	true,
		3705	false,
		3706	false,
		3707	true,
		3708	true,
		3709	false,
		3710	false,
		3711	false,
		3712	false,
		3713	false,
		3714	false,
		3715	false,
		3716	true,
		3717	true,
		3718	true,
		3719	false,
		3720	true,
		3721	true,
		3722	true,
		3723	true,
		3724	true,
		3725	false,
		3726	true,
		3727	true,
		3728	true,
		3729	false,
		3730	true,
		3731	false,
		3732	false,
		3733	true,
		3734	false,
		3735	true,
		3736	true,
		3737	false,
		3738	false,
		3739	false,
		3740	true,
		3741	true,
		3742	true,
		3743	true,
		3744	false,
		3745	false,
		3746	true,
		3747	true,
		3748	false,
		3749	true,
		3750	true,
		3751	false,
		3752	false,
		3753	true,
		3754	false,
		3755	false,
		3756	false,
		3757	true,
		3758	true,
		3759	true,
		3760	false,
		3761	false,
		3762	true,
		3763	false,
		3764	true,
		3765	false,
		3766	false,
		3767	true,
		3768	false,
		3769	false,
		3770	true,
		3771	true,
		3772	false,
		3773	false,
		3774	false,
		3775	false,
		3776	true,
		3777	false,
		3778	false,
		3779	false,
		3780	false,
		3781	false,
		3782	false,
		3783	true,
		3784	true,
		3785	true,
		3786	true,
		3787	true,
		3788	false,
		3789	false,
		3790	false,
		3791	false,
		3792	true,
		3793	true,
		3794	false,
		3795	true,
		3796	true,
		3797	false,
		3798	false,
		3799	true,
		3800	false,
		3801	false,
		3802	false,
		3803	false,
		3804	true,
		3805	true,
		3806	true,
		3807	true,
		3808	false,
		3809	false,
		3810	false,
		3811	false,
		3812	true,
		3813	false,
		3814	false,
		3815	false,
		3816	false,
		3817	true,
		3818	true,
		3819	false,
		3820	true,
		3821	false,
		3822	true,
		3823	false,
		3824	false,
		3825	true,
		3826	true,
		3827	false,
		3828	true,
		3829	true,
		3830	false,
		3831	false,
		3832	false,
		3833	true,
		3834	false,
		3835	false,
		3836	false,
		3837	false,
		3838	true,
		3839	true,
		3840	false,
		3841	false,
		3842	true,
		3843	false,
		3844	true,
		3845	true,
		3846	false,
		3847	false,
		3848	false,
		3849	false,
		3850	false,
		3851	false,
		3852	true,
		3853	false,
		3854	false,
		3855	false,
		3856	false,
		3857	false,
		3858	false,
		3859	true,
		3860	false,
		3861	false,
		3862	false,
		3863	false,
		3864	true,
		3865	false,
		3866	false,
		3867	false,
		3868	false,
		3869	false,
		3870	false,
		3871	true,
		3872	true,
		3873	true,
		3874	false,
		3875	true,
		3876	true,
		3877	false,
		3878	false,
		3879	false,
		3880	false,
		3881	false,
		3882	true,
		3883	true,
		3884	false,
		3885	false,
		3886	false,
		3887	true,
		3888	false,
		3889	false,
		3890	true,
		3891	true,
		3892	true,
		3893	false,
		3894	false,
		3895	true,
		3896	false,
		3897	true,
		3898	true,
		3899	true,
		3900	true,
		3901	false,
		3902	true,
		3903	false,
		3904	false,
		3905	false,
		3906	true,
		3907	false,
		3908	false,
		3909	false,
		3910	false,
		3911	false,
		3912	false,
		3913	false,
		3914	true,
		3915	false,
		3916	false,
		3917	false,
		3918	true,
		3919	true,
		3920	true,
		3921	true,
		3922	false,
		3923	true,
		3924	true,
		3925	false,
		3926	false,
		3927	false,
		3928	true,
		3929	false,
		3930	false,
		3931	true,
		3932	true,
		3933	false,
		3934	true,
		3935	false,
		3936	true,
		3937	true,
		3938	false,
		3939	false,
		3940	false,
		3941	false,
		3942	true,
		3943	false,
		3944	true,
		3945	true,
		3946	false,
		3947	false,
		3948	true,
		3949	true,
		3950	true,
		3951	false,
		3952	true,
		3953	false,
		3954	false,
		3955	true,
		3956	true,
		3957	false,
		3958	true,
		3959	false,
		3960	true,
		3961	true,
		3962	true,
		3963	true,
		3964	true,
		3965	true,
		3966	true,
		3967	true,
		3968	true,
		3969	true,
		3970	false,
		3971	true,
		3972	false,
		3973	true,
		3974	false,
		3975	true,
		3976	true,
		3977	false,
		3978	true,
		3979	false,
		3980	true,
		3981	false,
		3982	true,
		3983	true,
		3984	false,
		3985	true,
		3986	true,
		3987	true,
		3988	false,
		3989	false,
		3990	false,
		3991	false,
		3992	true,
		3993	true,
		3994	true,
		3995	true,
		3996	true,
		3997	true,
		3998	true,
		3999	true,
		4000	true,
		4001	false,
		4002	true,
		4003	false,
		4004	false,
		4005	true,
		4006	false,
		4007	false,
		4008	false,
		4009	false,
		4010	false,
		4011	false,
		4012	false,
		4013	false,
		4014	false,
		4015	false,
		4016	false,
		4017	true,
		4018	true,
		4019	false,
		4020	false,
		4021	false,
		4022	false,
		4023	false,
		4024	true,
		4025	true,
		4026	true,
		4027	true,
		4028	false,
		4029	false,
		4030	false,
		4031	false,
		4032	true,
		4033	true,
		4034	false,
		4035	false,
		4036	false,
		4037	true,
		4038	true,
		4039	false,
		4040	false,
		4041	false,
		4042	false,
		4043	false,
		4044	true,
		4045	true,
		4046	false,
		4047	true,
		4048	true,
		4049	false,
		4050	true,
		4051	true,
		4052	false,
		4053	true,
		4054	true,
		4055	false,
		4056	true,
		4057	true,
		4058	false,
		4059	true,
		4060	false,
		4061	true,
		4062	true,
		4063	true,
		4064	true,
		4065	false,
		4066	false,
		4067	false,
		4068	true,
		4069	true,
		4070	true,
		4071	true,
		4072	false,
		4073	true,
		4074	true,
		4075	true,
		4076	false,
		4077	false,
		4078	true,
		4079	false,
		4080	false,
		4081	false,
		4082	true,
		4083	true,
		4084	true,
		4085	false,
		4086	true,
		4087	false,
		4088	false,
		4089	false,
		4090	true,
		4091	false,
		4092	false,
		4093	true,
		4094	true,
		4095	true,
		4096	true,
		4097	false,
		4098	true,
		4099	true,
		4100	false,
		4101	false,
		4102	false,
		4103	true,
		4104	false,
		4105	true,
		4106	true,
		4107	false,
		4108	false,
		4109	false,
		4110	false,
		4111	true,
		4112	false,
		4113	true,
		4114	false,
		4115	false,
		4116	false,
		4117	false,
		4118	true,
		4119	false,
		4120	false,
		4121	true,
		4122	true,
		4123	true,
		4124	false,
		4125	true,
		4126	true,
		4127	false,
		4128	true,
		4129	false,
		4130	true,
		4131	false,
		4132	false,
		4133	false,
		4134	true,
		4135	false,
		4136	false,
		4137	false,
		4138	true,
		4139	true,
		4140	true,
		4141	true,
		4142	true,
		4143	false,
		4144	false,
		4145	false,
		4146	false,
		4147	false,
		4148	false,
		4149	true,
		4150	true,
		4151	true,
		4152	true,
		4153	true,
		4154	false,
		4155	true,
		4156	true,
		4157	false,
		4158	true,
		4159	false,
		4160	true,
		4161	false,
		4162	true,
		4163	false,
		4164	false,
		4165	false,
		4166	true,
		4167	false,
		4168	false,
		4169	false,
		4170	true,
		4171	true,
		4172	false,
		4173	false,
		4174	true,
		4175	false,
		4176	true,
		4177	false,
		4178	false,
		4179	false,
		4180	true,
		4181	true,
		4182	true,
		4183	true,
		4184	false,
		4185	false,
		4186	true,
		4187	});
		4188
		4189	Vector512Bool vec = zig_ret_vector_512_bool();
		4190	assert_or_panic(vec[0] == true);
		4191	assert_or_panic(vec[1] == true);
		4192	assert_or_panic(vec[2] == true);
		4193	assert_or_panic(vec[3] == true);
		4194	assert_or_panic(vec[4] == false);
		4195	assert_or_panic(vec[5] == true);
		4196	assert_or_panic(vec[6] == false);
		4197	assert_or_panic(vec[7] == true);
		4198	assert_or_panic(vec[8] == true);
		4199	assert_or_panic(vec[9] == true);
		4200	assert_or_panic(vec[10] == false);
		4201	assert_or_panic(vec[11] == true);
		4202	assert_or_panic(vec[12] == false);
		4203	assert_or_panic(vec[13] == false);
		4204	assert_or_panic(vec[14] == false);
		4205	assert_or_panic(vec[15] == true);
		4206	assert_or_panic(vec[16] == true);
		4207	assert_or_panic(vec[17] == false);
		4208	assert_or_panic(vec[18] == false);
		4209	assert_or_panic(vec[19] == false);
		4210	assert_or_panic(vec[20] == true);
		4211	assert_or_panic(vec[21] == true);
		4212	assert_or_panic(vec[22] == false);
		4213	assert_or_panic(vec[23] == false);
		4214	assert_or_panic(vec[24] == false);
		4215	assert_or_panic(vec[25] == false);
		4216	assert_or_panic(vec[26] == true);
		4217	assert_or_panic(vec[27] == false);
		4218	assert_or_panic(vec[28] == false);
		4219	assert_or_panic(vec[29] == false);
		4220	assert_or_panic(vec[30] == true);
		4221	assert_or_panic(vec[31] == true);
		4222	assert_or_panic(vec[32] == true);
		4223	assert_or_panic(vec[33] == true);
		4224	assert_or_panic(vec[34] == false);
		4225	assert_or_panic(vec[35] == false);
		4226	assert_or_panic(vec[36] == false);
		4227	assert_or_panic(vec[37] == true);
		4228	assert_or_panic(vec[38] == true);
		4229	assert_or_panic(vec[39] == true);
		4230	assert_or_panic(vec[40] == false);
		4231	assert_or_panic(vec[41] == false);
		4232	assert_or_panic(vec[42] == true);
		4233	assert_or_panic(vec[43] == false);
		4234	assert_or_panic(vec[44] == false);
		4235	assert_or_panic(vec[45] == true);
		4236	assert_or_panic(vec[46] == false);
		4237	assert_or_panic(vec[47] == false);
		4238	assert_or_panic(vec[48] == true);
		4239	assert_or_panic(vec[49] == true);
		4240	assert_or_panic(vec[50] == true);
		4241	assert_or_panic(vec[51] == true);
		4242	assert_or_panic(vec[52] == false);
		4243	assert_or_panic(vec[53] == false);
		4244	assert_or_panic(vec[54] == false);
		4245	assert_or_panic(vec[55] == true);
		4246	assert_or_panic(vec[56] == false);
		4247	assert_or_panic(vec[57] == true);
		4248	assert_or_panic(vec[58] == false);
		4249	assert_or_panic(vec[59] == true);
		4250	assert_or_panic(vec[60] == true);
		4251	assert_or_panic(vec[61] == false);
		4252	assert_or_panic(vec[62] == false);
		4253	assert_or_panic(vec[63] == true);
		4254	assert_or_panic(vec[64] == true);
		4255	assert_or_panic(vec[65] == false);
		4256	assert_or_panic(vec[66] == true);
		4257	assert_or_panic(vec[67] == false);
		4258	assert_or_panic(vec[68] == false);
		4259	assert_or_panic(vec[69] == false);
		4260	assert_or_panic(vec[70] == true);
		4261	assert_or_panic(vec[71] == true);
		4262	assert_or_panic(vec[72] == true);
		4263	assert_or_panic(vec[73] == true);
		4264	assert_or_panic(vec[74] == true);
		4265	assert_or_panic(vec[75] == false);
		4266	assert_or_panic(vec[76] == true);
		4267	assert_or_panic(vec[77] == false);
		4268	assert_or_panic(vec[78] == true);
		4269	assert_or_panic(vec[79] == true);
		4270	assert_or_panic(vec[80] == true);
		4271	assert_or_panic(vec[81] == true);
		4272	assert_or_panic(vec[82] == true);
		4273	assert_or_panic(vec[83] == false);
		4274	assert_or_panic(vec[84] == true);
		4275	assert_or_panic(vec[85] == true);
		4276	assert_or_panic(vec[86] == false);
		4277	assert_or_panic(vec[87] == true);
		4278	assert_or_panic(vec[88] == false);
		4279	assert_or_panic(vec[89] == false);
		4280	assert_or_panic(vec[90] == true);
		4281	assert_or_panic(vec[91] == false);
		4282	assert_or_panic(vec[92] == true);
		4283	assert_or_panic(vec[93] == false);
		4284	assert_or_panic(vec[94] == false);
		4285	assert_or_panic(vec[95] == false);
		4286	assert_or_panic(vec[96] == true);
		4287	assert_or_panic(vec[97] == true);
		4288	assert_or_panic(vec[98] == false);
		4289	assert_or_panic(vec[99] == true);
		4290	assert_or_panic(vec[100] == true);
		4291	assert_or_panic(vec[101] == false);
		4292	assert_or_panic(vec[102] == true);
		4293	assert_or_panic(vec[103] == false);
		4294	assert_or_panic(vec[104] == true);
		4295	assert_or_panic(vec[105] == false);
		4296	assert_or_panic(vec[106] == true);
		4297	assert_or_panic(vec[107] == false);
		4298	assert_or_panic(vec[108] == false);
		4299	assert_or_panic(vec[109] == true);
		4300	assert_or_panic(vec[110] == false);
		4301	assert_or_panic(vec[111] == false);
		4302	assert_or_panic(vec[112] == true);
		4303	assert_or_panic(vec[113] == false);
		4304	assert_or_panic(vec[114] == true);
		4305	assert_or_panic(vec[115] == false);
		4306	assert_or_panic(vec[116] == true);
		4307	assert_or_panic(vec[117] == false);
		4308	assert_or_panic(vec[118] == false);
		4309	assert_or_panic(vec[119] == true);
		4310	assert_or_panic(vec[120] == true);
		4311	assert_or_panic(vec[121] == true);
		4312	assert_or_panic(vec[122] == false);
		4313	assert_or_panic(vec[123] == true);
		4314	assert_or_panic(vec[124] == false);
		4315	assert_or_panic(vec[125] == false);
		4316	assert_or_panic(vec[126] == true);
		4317	assert_or_panic(vec[127] == true);
		4318	assert_or_panic(vec[128] == false);
		4319	assert_or_panic(vec[129] == true);
		4320	assert_or_panic(vec[130] == true);
		4321	assert_or_panic(vec[131] == false);
		4322	assert_or_panic(vec[132] == true);
		4323	assert_or_panic(vec[133] == true);
		4324	assert_or_panic(vec[134] == false);
		4325	assert_or_panic(vec[135] == true);
		4326	assert_or_panic(vec[136] == true);
		4327	assert_or_panic(vec[137] == false);
		4328	assert_or_panic(vec[138] == false);
		4329	assert_or_panic(vec[139] == false);
		4330	assert_or_panic(vec[140] == true);
		4331	assert_or_panic(vec[141] == false);
		4332	assert_or_panic(vec[142] == true);
		4333	assert_or_panic(vec[143] == false);
		4334	assert_or_panic(vec[144] == false);
		4335	assert_or_panic(vec[145] == false);
		4336	assert_or_panic(vec[146] == true);
		4337	assert_or_panic(vec[147] == false);
		4338	assert_or_panic(vec[148] == true);
		4339	assert_or_panic(vec[149] == false);
		4340	assert_or_panic(vec[150] == false);
		4341	assert_or_panic(vec[151] == true);
		4342	assert_or_panic(vec[152] == false);
		4343	assert_or_panic(vec[153] == true);
		4344	assert_or_panic(vec[154] == true);
		4345	assert_or_panic(vec[155] == false);
		4346	assert_or_panic(vec[156] == true);
		4347	assert_or_panic(vec[157] == true);
		4348	assert_or_panic(vec[158] == false);
		4349	assert_or_panic(vec[159] == true);
		4350	assert_or_panic(vec[160] == true);
		4351	assert_or_panic(vec[161] == false);
		4352	assert_or_panic(vec[162] == false);
		4353	assert_or_panic(vec[163] == false);
		4354	assert_or_panic(vec[164] == true);
		4355	assert_or_panic(vec[165] == false);
		4356	assert_or_panic(vec[166] == true);
		4357	assert_or_panic(vec[167] == true);
		4358	assert_or_panic(vec[168] == true);
		4359	assert_or_panic(vec[169] == true);
		4360	assert_or_panic(vec[170] == false);
		4361	assert_or_panic(vec[171] == true);
		4362	assert_or_panic(vec[172] == false);
		4363	assert_or_panic(vec[173] == false);
		4364	assert_or_panic(vec[174] == true);
		4365	assert_or_panic(vec[175] == true);
		4366	assert_or_panic(vec[176] == true);
		4367	assert_or_panic(vec[177] == false);
		4368	assert_or_panic(vec[178] == false);
		4369	assert_or_panic(vec[179] == false);
		4370	assert_or_panic(vec[180] == true);
		4371	assert_or_panic(vec[181] == false);
		4372	assert_or_panic(vec[182] == false);
		4373	assert_or_panic(vec[183] == true);
		4374	assert_or_panic(vec[184] == true);
		4375	assert_or_panic(vec[185] == false);
		4376	assert_or_panic(vec[186] == true);
		4377	assert_or_panic(vec[187] == false);
		4378	assert_or_panic(vec[188] == true);
		4379	assert_or_panic(vec[189] == true);
		4380	assert_or_panic(vec[190] == true);
		4381	assert_or_panic(vec[191] == true);
		4382	assert_or_panic(vec[192] == true);
		4383	assert_or_panic(vec[193] == true);
		4384	assert_or_panic(vec[194] == true);
		4385	assert_or_panic(vec[195] == false);
		4386	assert_or_panic(vec[196] == false);
		4387	assert_or_panic(vec[197] == false);
		4388	assert_or_panic(vec[198] == false);
		4389	assert_or_panic(vec[199] == false);
		4390	assert_or_panic(vec[200] == true);
		4391	assert_or_panic(vec[201] == false);
		4392	assert_or_panic(vec[202] == true);
		4393	assert_or_panic(vec[203] == false);
		4394	assert_or_panic(vec[204] == true);
		4395	assert_or_panic(vec[205] == true);
		4396	assert_or_panic(vec[206] == false);
		4397	assert_or_panic(vec[207] == false);
		4398	assert_or_panic(vec[208] == false);
		4399	assert_or_panic(vec[209] == true);
		4400	assert_or_panic(vec[210] == true);
		4401	assert_or_panic(vec[211] == true);
		4402	assert_or_panic(vec[212] == false);
		4403	assert_or_panic(vec[213] == false);
		4404	assert_or_panic(vec[214] == true);
		4405	assert_or_panic(vec[215] == true);
		4406	assert_or_panic(vec[216] == true);
		4407	assert_or_panic(vec[217] == false);
		4408	assert_or_panic(vec[218] == false);
		4409	assert_or_panic(vec[219] == true);
		4410	assert_or_panic(vec[220] == false);
		4411	assert_or_panic(vec[221] == true);
		4412	assert_or_panic(vec[222] == true);
		4413	assert_or_panic(vec[223] == false);
		4414	assert_or_panic(vec[224] == true);
		4415	assert_or_panic(vec[225] == false);
		4416	assert_or_panic(vec[226] == false);
		4417	assert_or_panic(vec[227] == true);
		4418	assert_or_panic(vec[228] == false);
		4419	assert_or_panic(vec[229] == false);
		4420	assert_or_panic(vec[230] == true);
		4421	assert_or_panic(vec[231] == true);
		4422	assert_or_panic(vec[232] == false);
		4423	assert_or_panic(vec[233] == true);
		4424	assert_or_panic(vec[234] == true);
		4425	assert_or_panic(vec[235] == true);
		4426	assert_or_panic(vec[236] == true);
		4427	assert_or_panic(vec[237] == true);
		4428	assert_or_panic(vec[238] == false);
		4429	assert_or_panic(vec[239] == true);
		4430	assert_or_panic(vec[240] == false);
		4431	assert_or_panic(vec[241] == false);
		4432	assert_or_panic(vec[242] == true);
		4433	assert_or_panic(vec[243] == false);
		4434	assert_or_panic(vec[244] == true);
		4435	assert_or_panic(vec[245] == false);
		4436	assert_or_panic(vec[246] == true);
		4437	assert_or_panic(vec[247] == false);
		4438	assert_or_panic(vec[248] == true);
		4439	assert_or_panic(vec[249] == true);
		4440	assert_or_panic(vec[250] == true);
		4441	assert_or_panic(vec[251] == true);
		4442	assert_or_panic(vec[252] == true);
		4443	assert_or_panic(vec[253] == false);
		4444	assert_or_panic(vec[254] == false);
		4445	assert_or_panic(vec[255] == false);
		4446	assert_or_panic(vec[256] == false);
		4447	assert_or_panic(vec[257] == false);
		4448	assert_or_panic(vec[258] == false);
		4449	assert_or_panic(vec[259] == true);
		4450	assert_or_panic(vec[260] == true);
		4451	assert_or_panic(vec[261] == true);
		4452	assert_or_panic(vec[262] == true);
		4453	assert_or_panic(vec[263] == false);
		4454	assert_or_panic(vec[264] == false);
		4455	assert_or_panic(vec[265] == false);
		4456	assert_or_panic(vec[266] == true);
		4457	assert_or_panic(vec[267] == false);
		4458	assert_or_panic(vec[268] == true);
		4459	assert_or_panic(vec[269] == false);
		4460	assert_or_panic(vec[270] == true);
		4461	assert_or_panic(vec[271] == true);
		4462	assert_or_panic(vec[272] == true);
		4463	assert_or_panic(vec[273] == true);
		4464	assert_or_panic(vec[274] == true);
		4465	assert_or_panic(vec[275] == true);
		4466	assert_or_panic(vec[276] == false);
		4467	assert_or_panic(vec[277] == false);
		4468	assert_or_panic(vec[278] == true);
		4469	assert_or_panic(vec[279] == true);
		4470	assert_or_panic(vec[280] == false);
		4471	assert_or_panic(vec[281] == false);
		4472	assert_or_panic(vec[282] == false);
		4473	assert_or_panic(vec[283] == false);
		4474	assert_or_panic(vec[284] == true);
		4475	assert_or_panic(vec[285] == true);
		4476	assert_or_panic(vec[286] == true);
		4477	assert_or_panic(vec[287] == false);
		4478	assert_or_panic(vec[288] == false);
		4479	assert_or_panic(vec[289] == false);
		4480	assert_or_panic(vec[290] == true);
		4481	assert_or_panic(vec[291] == false);
		4482	assert_or_panic(vec[292] == true);
		4483	assert_or_panic(vec[293] == true);
		4484	assert_or_panic(vec[294] == false);
		4485	assert_or_panic(vec[295] == true);
		4486	assert_or_panic(vec[296] == true);
		4487	assert_or_panic(vec[297] == true);
		4488	assert_or_panic(vec[298] == false);
		4489	assert_or_panic(vec[299] == true);
		4490	assert_or_panic(vec[300] == true);
		4491	assert_or_panic(vec[301] == false);
		4492	assert_or_panic(vec[302] == false);
		4493	assert_or_panic(vec[303] == true);
		4494	assert_or_panic(vec[304] == false);
		4495	assert_or_panic(vec[305] == false);
		4496	assert_or_panic(vec[306] == true);
		4497	assert_or_panic(vec[307] == true);
		4498	assert_or_panic(vec[308] == true);
		4499	assert_or_panic(vec[309] == true);
		4500	assert_or_panic(vec[310] == false);
		4501	assert_or_panic(vec[311] == false);
		4502	assert_or_panic(vec[312] == false);
		4503	assert_or_panic(vec[313] == false);
		4504	assert_or_panic(vec[314] == false);
		4505	assert_or_panic(vec[315] == true);
		4506	assert_or_panic(vec[316] == false);
		4507	assert_or_panic(vec[317] == false);
		4508	assert_or_panic(vec[318] == true);
		4509	assert_or_panic(vec[319] == false);
		4510	assert_or_panic(vec[320] == false);
		4511	assert_or_panic(vec[321] == true);
		4512	assert_or_panic(vec[322] == true);
		4513	assert_or_panic(vec[323] == true);
		4514	assert_or_panic(vec[324] == true);
		4515	assert_or_panic(vec[325] == false);
		4516	assert_or_panic(vec[326] == false);
		4517	assert_or_panic(vec[327] == false);
		4518	assert_or_panic(vec[328] == true);
		4519	assert_or_panic(vec[329] == true);
		4520	assert_or_panic(vec[330] == false);
		4521	assert_or_panic(vec[331] == true);
		4522	assert_or_panic(vec[332] == true);
		4523	assert_or_panic(vec[333] == false);
		4524	assert_or_panic(vec[334] == false);
		4525	assert_or_panic(vec[335] == true);
		4526	assert_or_panic(vec[336] == true);
		4527	assert_or_panic(vec[337] == false);
		4528	assert_or_panic(vec[338] == true);
		4529	assert_or_panic(vec[339] == true);
		4530	assert_or_panic(vec[340] == true);
		4531	assert_or_panic(vec[341] == false);
		4532	assert_or_panic(vec[342] == false);
		4533	assert_or_panic(vec[343] == false);
		4534	assert_or_panic(vec[344] == true);
		4535	assert_or_panic(vec[345] == true);
		4536	assert_or_panic(vec[346] == false);
		4537	assert_or_panic(vec[347] == true);
		4538	assert_or_panic(vec[348] == false);
		4539	assert_or_panic(vec[349] == true);
		4540	assert_or_panic(vec[350] == false);
		4541	assert_or_panic(vec[351] == false);
		4542	assert_or_panic(vec[352] == true);
		4543	assert_or_panic(vec[353] == false);
		4544	assert_or_panic(vec[354] == true);
		4545	assert_or_panic(vec[355] == false);
		4546	assert_or_panic(vec[356] == false);
		4547	assert_or_panic(vec[357] == false);
		4548	assert_or_panic(vec[358] == false);
		4549	assert_or_panic(vec[359] == false);
		4550	assert_or_panic(vec[360] == true);
		4551	assert_or_panic(vec[361] == true);
		4552	assert_or_panic(vec[362] == false);
		4553	assert_or_panic(vec[363] == false);
		4554	assert_or_panic(vec[364] == false);
		4555	assert_or_panic(vec[365] == false);
		4556	assert_or_panic(vec[366] == true);
		4557	assert_or_panic(vec[367] == false);
		4558	assert_or_panic(vec[368] == true);
		4559	assert_or_panic(vec[369] == false);
		4560	assert_or_panic(vec[370] == true);
		4561	assert_or_panic(vec[371] == true);
		4562	assert_or_panic(vec[372] == false);
		4563	assert_or_panic(vec[373] == true);
		4564	assert_or_panic(vec[374] == true);
		4565	assert_or_panic(vec[375] == true);
		4566	assert_or_panic(vec[376] == true);
		4567	assert_or_panic(vec[377] == true);
		4568	assert_or_panic(vec[378] == false);
		4569	assert_or_panic(vec[379] == true);
		4570	assert_or_panic(vec[380] == false);
		4571	assert_or_panic(vec[381] == true);
		4572	assert_or_panic(vec[382] == true);
		4573	assert_or_panic(vec[383] == true);
		4574	assert_or_panic(vec[384] == true);
		4575	assert_or_panic(vec[385] == true);
		4576	assert_or_panic(vec[386] == false);
		4577	assert_or_panic(vec[387] == true);
		4578	assert_or_panic(vec[388] == true);
		4579	assert_or_panic(vec[389] == false);
		4580	assert_or_panic(vec[390] == true);
		4581	assert_or_panic(vec[391] == false);
		4582	assert_or_panic(vec[392] == true);
		4583	assert_or_panic(vec[393] == false);
		4584	assert_or_panic(vec[394] == true);
		4585	assert_or_panic(vec[395] == false);
		4586	assert_or_panic(vec[396] == true);
		4587	assert_or_panic(vec[397] == false);
		4588	assert_or_panic(vec[398] == false);
		4589	assert_or_panic(vec[399] == true);
		4590	assert_or_panic(vec[400] == true);
		4591	assert_or_panic(vec[401] == true);
		4592	assert_or_panic(vec[402] == true);
		4593	assert_or_panic(vec[403] == false);
		4594	assert_or_panic(vec[404] == false);
		4595	assert_or_panic(vec[405] == true);
		4596	assert_or_panic(vec[406] == false);
		4597	assert_or_panic(vec[407] == false);
		4598	assert_or_panic(vec[408] == false);
		4599	assert_or_panic(vec[409] == true);
		4600	assert_or_panic(vec[410] == false);
		4601	assert_or_panic(vec[411] == true);
		4602	assert_or_panic(vec[412] == true);
		4603	assert_or_panic(vec[413] == false);
		4604	assert_or_panic(vec[414] == true);
		4605	assert_or_panic(vec[415] == true);
		4606	assert_or_panic(vec[416] == false);
		4607	assert_or_panic(vec[417] == true);
		4608	assert_or_panic(vec[418] == true);
		4609	assert_or_panic(vec[419] == false);
		4610	assert_or_panic(vec[420] == false);
		4611	assert_or_panic(vec[421] == true);
		4612	assert_or_panic(vec[422] == false);
		4613	assert_or_panic(vec[423] == false);
		4614	assert_or_panic(vec[424] == true);
		4615	assert_or_panic(vec[425] == false);
		4616	assert_or_panic(vec[426] == true);
		4617	assert_or_panic(vec[427] == false);
		4618	assert_or_panic(vec[428] == false);
		4619	assert_or_panic(vec[429] == true);
		4620	assert_or_panic(vec[430] == false);
		4621	assert_or_panic(vec[431] == true);
		4622	assert_or_panic(vec[432] == true);
		4623	assert_or_panic(vec[433] == false);
		4624	assert_or_panic(vec[434] == true);
		4625	assert_or_panic(vec[435] == false);
		4626	assert_or_panic(vec[436] == true);
		4627	assert_or_panic(vec[437] == false);
		4628	assert_or_panic(vec[438] == true);
		4629	assert_or_panic(vec[439] == false);
		4630	assert_or_panic(vec[440] == false);
		4631	assert_or_panic(vec[441] == true);
		4632	assert_or_panic(vec[442] == true);
		4633	assert_or_panic(vec[443] == false);
		4634	assert_or_panic(vec[444] == true);
		4635	assert_or_panic(vec[445] == true);
		4636	assert_or_panic(vec[446] == false);
		4637	assert_or_panic(vec[447] == true);
		4638	assert_or_panic(vec[448] == true);
		4639	assert_or_panic(vec[449] == false);
		4640	assert_or_panic(vec[450] == false);
		4641	assert_or_panic(vec[451] == false);
		4642	assert_or_panic(vec[452] == false);
		4643	assert_or_panic(vec[453] == false);
		4644	assert_or_panic(vec[454] == true);
		4645	assert_or_panic(vec[455] == false);
		4646	assert_or_panic(vec[456] == false);
		4647	assert_or_panic(vec[457] == true);
		4648	assert_or_panic(vec[458] == false);
		4649	assert_or_panic(vec[459] == true);
		4650	assert_or_panic(vec[460] == false);
		4651	assert_or_panic(vec[461] == false);
		4652	assert_or_panic(vec[462] == false);
		4653	assert_or_panic(vec[463] == true);
		4654	assert_or_panic(vec[464] == false);
		4655	assert_or_panic(vec[465] == true);
		4656	assert_or_panic(vec[466] == false);
		4657	assert_or_panic(vec[467] == false);
		4658	assert_or_panic(vec[468] == false);
		4659	assert_or_panic(vec[469] == false);
		4660	assert_or_panic(vec[470] == true);
		4661	assert_or_panic(vec[471] == true);
		4662	assert_or_panic(vec[472] == false);
		4663	assert_or_panic(vec[473] == true);
		4664	assert_or_panic(vec[474] == true);
		4665	assert_or_panic(vec[475] == false);
		4666	assert_or_panic(vec[476] == false);
		4667	assert_or_panic(vec[477] == true);
		4668	assert_or_panic(vec[478] == true);
		4669	assert_or_panic(vec[479] == true);
		4670	assert_or_panic(vec[480] == false);
		4671	assert_or_panic(vec[481] == false);
		4672	assert_or_panic(vec[482] == true);
		4673	assert_or_panic(vec[483] == false);
		4674	assert_or_panic(vec[484] == false);
		4675	assert_or_panic(vec[485] == false);
		4676	assert_or_panic(vec[486] == true);
		4677	assert_or_panic(vec[487] == true);
		4678	assert_or_panic(vec[488] == false);
		4679	assert_or_panic(vec[489] == false);
		4680	assert_or_panic(vec[490] == false);
		4681	assert_or_panic(vec[491] == false);
		4682	assert_or_panic(vec[492] == false);
		4683	assert_or_panic(vec[493] == true);
		4684	assert_or_panic(vec[494] == true);
		4685	assert_or_panic(vec[495] == true);
		4686	assert_or_panic(vec[496] == true);
		4687	assert_or_panic(vec[497] == false);
		4688	assert_or_panic(vec[498] == false);
		4689	assert_or_panic(vec[499] == false);
		4690	assert_or_panic(vec[500] == true);
		4691	assert_or_panic(vec[501] == false);
		4692	assert_or_panic(vec[502] == true);
		4693	assert_or_panic(vec[503] == true);
		4694	assert_or_panic(vec[504] == true);
		4695	assert_or_panic(vec[505] == true);
		4696	assert_or_panic(vec[506] == false);
		4697	assert_or_panic(vec[507] == false);
		4698	assert_or_panic(vec[508] == true);
		4699	assert_or_panic(vec[509] == true);
		4700	assert_or_panic(vec[510] == false);
		4701	assert_or_panic(vec[511] == false);
		4702	}
		4703	#endif
453	}	4704	}
454		4705
455	void c_u8(uint8_t x) {	4706	void c_u8(uint8_t x) {

test/c_abi/main.zig+4258

...	@@ -890,6 +890,4264 @@ test "big simd vector" {	...	@@ -890,6 +890,4264 @@ test "big simd vector" {
890	try expect(x[7] == 16);	890	try expect(x[7] == 16);
891	}	891	}
892		892
		893	const Vector2Bool = @Vector(2, bool);
		894	const Vector4Bool = @Vector(4, bool);
		895	const Vector8Bool = @Vector(8, bool);
		896	const Vector16Bool = @Vector(16, bool);
		897	const Vector32Bool = @Vector(32, bool);
		898	const Vector64Bool = @Vector(64, bool);
		899	const Vector128Bool = @Vector(128, bool);
		900	const Vector256Bool = @Vector(256, bool);
		901	const Vector512Bool = @Vector(512, bool);
		902
		903	extern fn c_vector_2_bool(Vector2Bool) void;
		904	extern fn c_vector_4_bool(Vector4Bool) void;
		905	extern fn c_vector_8_bool(Vector8Bool) void;
		906	extern fn c_vector_16_bool(Vector16Bool) void;
		907	extern fn c_vector_32_bool(Vector32Bool) void;
		908	extern fn c_vector_64_bool(Vector64Bool) void;
		909	extern fn c_vector_128_bool(Vector128Bool) void;
		910	extern fn c_vector_256_bool(Vector256Bool) void;
		911	extern fn c_vector_512_bool(Vector512Bool) void;
		912
		913	extern fn c_ret_vector_2_bool() Vector2Bool;
		914	extern fn c_ret_vector_4_bool() Vector4Bool;
		915	extern fn c_ret_vector_8_bool() Vector8Bool;
		916	extern fn c_ret_vector_16_bool() Vector16Bool;
		917	extern fn c_ret_vector_32_bool() Vector32Bool;
		918	extern fn c_ret_vector_64_bool() Vector64Bool;
		919	extern fn c_ret_vector_128_bool() Vector128Bool;
		920	extern fn c_ret_vector_256_bool() Vector256Bool;
		921	extern fn c_ret_vector_512_bool() Vector512Bool;
		922
		923	test "bool simd vector" {
		924	if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch != .powerpc) return error.SkipZigTest;
		925
		926	{
		927	c_vector_2_bool(.{
		928	true,
		929	true,
		930	});
		931
		932	const vec = c_ret_vector_2_bool();
		933	try expect(vec[0] == true);
		934	try expect(vec[1] == false);
		935	}
		936	{
		937	c_vector_4_bool(.{
		938	true,
		939	true,
		940	false,
		941	true,
		942	});
		943
		944	const vec = c_ret_vector_4_bool();
		945	try expect(vec[0] == true);
		946	try expect(vec[1] == false);
		947	try expect(vec[2] == true);
		948	try expect(vec[3] == false);
		949	}
		950	{
		951	c_vector_8_bool(.{
		952	true,
		953	false,
		954	true,
		955	true,
		956	true,
		957	true,
		958	false,
		959	true,
		960	});
		961
		962	const vec = c_ret_vector_8_bool();
		963	try expect(vec[0] == false);
		964	try expect(vec[1] == true);
		965	try expect(vec[2] == false);
		966	try expect(vec[3] == false);
		967	try expect(vec[4] == true);
		968	try expect(vec[5] == false);
		969	try expect(vec[6] == false);
		970	try expect(vec[7] == true);
		971	}
		972	{
		973	c_vector_16_bool(.{
		974	true,
		975	false,
		976	false,
		977	false,
		978	true,
		979	false,
		980	true,
		981	true,
		982	true,
		983	true,
		984	true,
		985	true,
		986	false,
		987	false,
		988	false,
		989	false,
		990	});
		991
		992	const vec = c_ret_vector_16_bool();
		993	try expect(vec[0] == true);
		994	try expect(vec[1] == true);
		995	try expect(vec[2] == false);
		996	try expect(vec[3] == false);
		997	try expect(vec[4] == false);
		998	try expect(vec[5] == false);
		999	try expect(vec[6] == true);
		1000	try expect(vec[7] == false);
		1001	try expect(vec[8] == true);
		1002	try expect(vec[9] == false);
		1003	try expect(vec[10] == false);
		1004	try expect(vec[11] == true);
		1005	try expect(vec[12] == true);
		1006	try expect(vec[13] == false);
		1007	try expect(vec[14] == true);
		1008	try expect(vec[15] == true);
		1009	}
		1010	{
		1011	c_vector_32_bool(.{
		1012	true,
		1013	false,
		1014	true,
		1015	true,
		1016	false,
		1017	false,
		1018	true,
		1019	false,
		1020	true,
		1021	false,
		1022	true,
		1023	true,
		1024	true,
		1025	false,
		1026	false,
		1027	true,
		1028	false,
		1029	true,
		1030	false,
		1031	true,
		1032	true,
		1033	true,
		1034	true,
		1035	true,
		1036	false,
		1037	true,
		1038	true,
		1039	true,
		1040	false,
		1041	true,
		1042	true,
		1043	false,
		1044	});
		1045
		1046	const vec = c_ret_vector_32_bool();
		1047	try expect(vec[0] == true);
		1048	try expect(vec[1] == false);
		1049	try expect(vec[2] == true);
		1050	try expect(vec[3] == true);
		1051	try expect(vec[4] == true);
		1052	try expect(vec[5] == false);
		1053	try expect(vec[6] == true);
		1054	try expect(vec[7] == false);
		1055	try expect(vec[8] == true);
		1056	try expect(vec[9] == true);
		1057	try expect(vec[10] == true);
		1058	try expect(vec[11] == false);
		1059	try expect(vec[12] == true);
		1060	try expect(vec[13] == true);
		1061	try expect(vec[14] == false);
		1062	try expect(vec[15] == false);
		1063	try expect(vec[16] == true);
		1064	try expect(vec[17] == false);
		1065	try expect(vec[18] == false);
		1066	try expect(vec[19] == false);
		1067	try expect(vec[20] == false);
		1068	try expect(vec[21] == true);
		1069	try expect(vec[22] == true);
		1070	try expect(vec[23] == true);
		1071	try expect(vec[24] == false);
		1072	try expect(vec[25] == true);
		1073	try expect(vec[26] == false);
		1074	try expect(vec[27] == false);
		1075	try expect(vec[28] == true);
		1076	try expect(vec[29] == false);
		1077	try expect(vec[30] == false);
		1078	try expect(vec[31] == false);
		1079	}
		1080	{
		1081	c_vector_64_bool(.{
		1082	true,
		1083	true,
		1084	true,
		1085	false,
		1086	true,
		1087	false,
		1088	false,
		1089	false,
		1090	true,
		1091	false,
		1092	false,
		1093	false,
		1094	false,
		1095	true,
		1096	true,
		1097	true,
		1098	true,
		1099	false,
		1100	false,
		1101	true,
		1102	false,
		1103	true,
		1104	false,
		1105	true,
		1106	true,
		1107	true,
		1108	true,
		1109	true,
		1110	true,
		1111	true,
		1112	false,
		1113	false,
		1114	true,
		1115	true,
		1116	false,
		1117	true,
		1118	false,
		1119	false,
		1120	true,
		1121	true,
		1122	true,
		1123	false,
		1124	false,
		1125	true,
		1126	true,
		1127	false,
		1128	true,
		1129	false,
		1130	true,
		1131	false,
		1132	false,
		1133	true,
		1134	false,
		1135	true,
		1136	true,
		1137	true,
		1138	true,
		1139	true,
		1140	false,
		1141	false,
		1142	true,
		1143	false,
		1144	true,
		1145	false,
		1146	});
		1147
		1148	const vec = c_ret_vector_64_bool();
		1149	try expect(vec[0] == false);
		1150	try expect(vec[1] == true);
		1151	try expect(vec[2] == false);
		1152	try expect(vec[3] == true);
		1153	try expect(vec[4] == true);
		1154	try expect(vec[5] == true);
		1155	try expect(vec[6] == false);
		1156	try expect(vec[7] == true);
		1157	try expect(vec[8] == true);
		1158	try expect(vec[9] == true);
		1159	try expect(vec[10] == true);
		1160	try expect(vec[11] == true);
		1161	try expect(vec[12] == true);
		1162	try expect(vec[13] == false);
		1163	try expect(vec[14] == true);
		1164	try expect(vec[15] == true);
		1165	try expect(vec[16] == true);
		1166	try expect(vec[17] == false);
		1167	try expect(vec[18] == false);
		1168	try expect(vec[19] == false);
		1169	try expect(vec[20] == true);
		1170	try expect(vec[21] == true);
		1171	try expect(vec[22] == false);
		1172	try expect(vec[23] == true);
		1173	try expect(vec[24] == false);
		1174	try expect(vec[25] == true);
		1175	try expect(vec[26] == false);
		1176	try expect(vec[27] == true);
		1177	try expect(vec[28] == false);
		1178	try expect(vec[29] == true);
		1179	try expect(vec[30] == false);
		1180	try expect(vec[31] == true);
		1181	try expect(vec[32] == false);
		1182	try expect(vec[33] == false);
		1183	try expect(vec[34] == true);
		1184	try expect(vec[35] == true);
		1185	try expect(vec[36] == false);
		1186	try expect(vec[37] == false);
		1187	try expect(vec[38] == false);
		1188	try expect(vec[39] == true);
		1189	try expect(vec[40] == true);
		1190	try expect(vec[41] == true);
		1191	try expect(vec[42] == true);
		1192	try expect(vec[43] == false);
		1193	try expect(vec[44] == false);
		1194	try expect(vec[45] == false);
		1195	try expect(vec[46] == true);
		1196	try expect(vec[47] == true);
		1197	try expect(vec[48] == false);
		1198	try expect(vec[49] == false);
		1199	try expect(vec[50] == true);
		1200	try expect(vec[51] == false);
		1201	try expect(vec[52] == false);
		1202	try expect(vec[53] == false);
		1203	try expect(vec[54] == false);
		1204	try expect(vec[55] == true);
		1205	try expect(vec[56] == false);
		1206	try expect(vec[57] == false);
		1207	try expect(vec[58] == false);
		1208	try expect(vec[59] == true);
		1209	try expect(vec[60] == true);
		1210	try expect(vec[61] == true);
		1211	try expect(vec[62] == true);
		1212	try expect(vec[63] == true);
		1213	}
		1214	{
		1215	c_vector_128_bool(.{
		1216	false,
		1217	false,
		1218	false,
		1219	false,
		1220	false,
		1221	true,
		1222	true,
		1223	false,
		1224	true,
		1225	true,
		1226	false,
		1227	true,
		1228	true,
		1229	false,
		1230	true,
		1231	true,
		1232	true,
		1233	false,
		1234	false,
		1235	false,
		1236	false,
		1237	true,
		1238	true,
		1239	false,
		1240	false,
		1241	false,
		1242	true,
		1243	true,
		1244	false,
		1245	true,
		1246	false,
		1247	false,
		1248	true,
		1249	false,
		1250	false,
		1251	true,
		1252	true,
		1253	true,
		1254	true,
		1255	true,
		1256	false,
		1257	true,
		1258	true,
		1259	true,
		1260	false,
		1261	false,
		1262	false,
		1263	false,
		1264	true,
		1265	true,
		1266	false,
		1267	true,
		1268	true,
		1269	true,
		1270	true,
		1271	true,
		1272	false,
		1273	true,
		1274	true,
		1275	false,
		1276	true,
		1277	false,
		1278	false,
		1279	true,
		1280	true,
		1281	false,
		1282	true,
		1283	true,
		1284	false,
		1285	true,
		1286	false,
		1287	false,
		1288	true,
		1289	true,
		1290	false,
		1291	true,
		1292	true,
		1293	true,
		1294	false,
		1295	true,
		1296	false,
		1297	false,
		1298	false,
		1299	false,
		1300	true,
		1301	false,
		1302	false,
		1303	false,
		1304	true,
		1305	true,
		1306	false,
		1307	false,
		1308	true,
		1309	true,
		1310	true,
		1311	true,
		1312	false,
		1313	false,
		1314	false,
		1315	false,
		1316	false,
		1317	true,
		1318	false,
		1319	false,
		1320	false,
		1321	false,
		1322	true,
		1323	true,
		1324	true,
		1325	true,
		1326	true,
		1327	false,
		1328	false,
		1329	true,
		1330	false,
		1331	true,
		1332	false,
		1333	false,
		1334	true,
		1335	false,
		1336	true,
		1337	false,
		1338	true,
		1339	true,
		1340	true,
		1341	true,
		1342	true,
		1343	true,
		1344	});
		1345
		1346	const vec = c_ret_vector_128_bool();
		1347	try expect(vec[0] == false);
		1348	try expect(vec[1] == true);
		1349	try expect(vec[2] == true);
		1350	try expect(vec[3] == false);
		1351	try expect(vec[4] == true);
		1352	try expect(vec[5] == false);
		1353	try expect(vec[6] == false);
		1354	try expect(vec[7] == true);
		1355	try expect(vec[8] == true);
		1356	try expect(vec[9] == false);
		1357	try expect(vec[10] == true);
		1358	try expect(vec[11] == false);
		1359	try expect(vec[12] == false);
		1360	try expect(vec[13] == false);
		1361	try expect(vec[14] == true);
		1362	try expect(vec[15] == false);
		1363	try expect(vec[16] == true);
		1364	try expect(vec[17] == false);
		1365	try expect(vec[18] == false);
		1366	try expect(vec[19] == true);
		1367	try expect(vec[20] == false);
		1368	try expect(vec[21] == true);
		1369	try expect(vec[22] == false);
		1370	try expect(vec[23] == false);
		1371	try expect(vec[24] == false);
		1372	try expect(vec[25] == true);
		1373	try expect(vec[26] == true);
		1374	try expect(vec[27] == true);
		1375	try expect(vec[28] == false);
		1376	try expect(vec[29] == false);
		1377	try expect(vec[30] == false);
		1378	try expect(vec[31] == false);
		1379	try expect(vec[32] == true);
		1380	try expect(vec[33] == true);
		1381	try expect(vec[34] == true);
		1382	try expect(vec[35] == false);
		1383	try expect(vec[36] == true);
		1384	try expect(vec[37] == true);
		1385	try expect(vec[38] == false);
		1386	try expect(vec[39] == false);
		1387	try expect(vec[40] == false);
		1388	try expect(vec[41] == false);
		1389	try expect(vec[42] == true);
		1390	try expect(vec[43] == true);
		1391	try expect(vec[44] == true);
		1392	try expect(vec[45] == false);
		1393	try expect(vec[46] == false);
		1394	try expect(vec[47] == false);
		1395	try expect(vec[48] == false);
		1396	try expect(vec[49] == true);
		1397	try expect(vec[50] == false);
		1398	try expect(vec[51] == false);
		1399	try expect(vec[52] == true);
		1400	try expect(vec[53] == false);
		1401	try expect(vec[54] == false);
		1402	try expect(vec[55] == false);
		1403	try expect(vec[56] == false);
		1404	try expect(vec[57] == false);
		1405	try expect(vec[58] == true);
		1406	try expect(vec[59] == true);
		1407	try expect(vec[60] == true);
		1408	try expect(vec[61] == false);
		1409	try expect(vec[62] == true);
		1410	try expect(vec[63] == true);
		1411	try expect(vec[64] == false);
		1412	try expect(vec[65] == false);
		1413	try expect(vec[66] == false);
		1414	try expect(vec[67] == false);
		1415	try expect(vec[68] == false);
		1416	try expect(vec[69] == false);
		1417	try expect(vec[70] == false);
		1418	try expect(vec[71] == false);
		1419	try expect(vec[72] == true);
		1420	try expect(vec[73] == true);
		1421	try expect(vec[74] == true);
		1422	try expect(vec[75] == true);
		1423	try expect(vec[76] == true);
		1424	try expect(vec[77] == false);
		1425	try expect(vec[78] == false);
		1426	try expect(vec[79] == false);
		1427	try expect(vec[80] == false);
		1428	try expect(vec[81] == false);
		1429	try expect(vec[82] == false);
		1430	try expect(vec[83] == true);
		1431	try expect(vec[84] == false);
		1432	try expect(vec[85] == true);
		1433	try expect(vec[86] == false);
		1434	try expect(vec[87] == true);
		1435	try expect(vec[88] == false);
		1436	try expect(vec[89] == true);
		1437	try expect(vec[90] == false);
		1438	try expect(vec[91] == true);
		1439	try expect(vec[92] == true);
		1440	try expect(vec[93] == true);
		1441	try expect(vec[94] == true);
		1442	try expect(vec[95] == false);
		1443	try expect(vec[96] == false);
		1444	try expect(vec[97] == true);
		1445	try expect(vec[98] == false);
		1446	try expect(vec[99] == false);
		1447	try expect(vec[100] == true);
		1448	try expect(vec[101] == true);
		1449	try expect(vec[102] == true);
		1450	try expect(vec[103] == true);
		1451	try expect(vec[104] == false);
		1452	try expect(vec[105] == true);
		1453	try expect(vec[106] == true);
		1454	try expect(vec[107] == true);
		1455	try expect(vec[108] == false);
		1456	try expect(vec[109] == false);
		1457	try expect(vec[110] == true);
		1458	try expect(vec[111] == false);
		1459	try expect(vec[112] == false);
		1460	try expect(vec[113] == true);
		1461	try expect(vec[114] == true);
		1462	try expect(vec[115] == false);
		1463	try expect(vec[116] == true);
		1464	try expect(vec[117] == false);
		1465	try expect(vec[118] == true);
		1466	try expect(vec[119] == true);
		1467	try expect(vec[120] == true);
		1468	try expect(vec[121] == true);
		1469	try expect(vec[122] == true);
		1470	try expect(vec[123] == false);
		1471	try expect(vec[124] == false);
		1472	try expect(vec[125] == true);
		1473	try expect(vec[126] == false);
		1474	try expect(vec[127] == true);
		1475	}
		1476	{
		1477	c_vector_256_bool(.{
		1478	false,
		1479	true,
		1480	true,
		1481	false,
		1482	false,
		1483	true,
		1484	true,
		1485	true,
		1486	false,
		1487	true,
		1488	true,
		1489	true,
		1490	false,
		1491	true,
		1492	false,
		1493	true,
		1494	false,
		1495	false,
		1496	true,
		1497	true,
		1498	false,
		1499	true,
		1500	false,
		1501	false,
		1502	false,
		1503	true,
		1504	true,
		1505	false,
		1506	false,
		1507	true,
		1508	true,
		1509	false,
		1510	true,
		1511	false,
		1512	false,
		1513	true,
		1514	false,
		1515	true,
		1516	false,
		1517	true,
		1518	true,
		1519	true,
		1520	true,
		1521	false,
		1522	false,
		1523	true,
		1524	false,
		1525	false,
		1526	false,
		1527	false,
		1528	false,
		1529	false,
		1530	true,
		1531	true,
		1532	true,
		1533	true,
		1534	true,
		1535	true,
		1536	false,
		1537	true,
		1538	true,
		1539	false,
		1540	false,
		1541	true,
		1542	false,
		1543	false,
		1544	false,
		1545	false,
		1546	false,
		1547	false,
		1548	true,
		1549	true,
		1550	true,
		1551	false,
		1552	false,
		1553	false,
		1554	true,
		1555	false,
		1556	true,
		1557	true,
		1558	false,
		1559	false,
		1560	true,
		1561	true,
		1562	false,
		1563	true,
		1564	true,
		1565	true,
		1566	true,
		1567	true,
		1568	true,
		1569	true,
		1570	false,
		1571	true,
		1572	true,
		1573	false,
		1574	false,
		1575	true,
		1576	true,
		1577	false,
		1578	true,
		1579	false,
		1580	false,
		1581	true,
		1582	false,
		1583	true,
		1584	true,
		1585	true,
		1586	true,
		1587	true,
		1588	false,
		1589	false,
		1590	false,
		1591	false,
		1592	true,
		1593	true,
		1594	false,
		1595	true,
		1596	false,
		1597	false,
		1598	true,
		1599	false,
		1600	false,
		1601	true,
		1602	false,
		1603	true,
		1604	true,
		1605	true,
		1606	true,
		1607	false,
		1608	true,
		1609	true,
		1610	false,
		1611	false,
		1612	true,
		1613	false,
		1614	false,
		1615	true,
		1616	false,
		1617	true,
		1618	false,
		1619	true,
		1620	true,
		1621	true,
		1622	true,
		1623	false,
		1624	true,
		1625	false,
		1626	false,
		1627	false,
		1628	true,
		1629	true,
		1630	true,
		1631	true,
		1632	true,
		1633	false,
		1634	true,
		1635	false,
		1636	false,
		1637	false,
		1638	true,
		1639	true,
		1640	false,
		1641	true,
		1642	true,
		1643	false,
		1644	false,
		1645	false,
		1646	false,
		1647	true,
		1648	false,
		1649	true,
		1650	false,
		1651	false,
		1652	false,
		1653	false,
		1654	true,
		1655	true,
		1656	true,
		1657	false,
		1658	true,
		1659	false,
		1660	true,
		1661	true,
		1662	false,
		1663	false,
		1664	true,
		1665	false,
		1666	false,
		1667	false,
		1668	false,
		1669	true,
		1670	true,
		1671	true,
		1672	true,
		1673	true,
		1674	true,
		1675	true,
		1676	false,
		1677	true,
		1678	false,
		1679	false,
		1680	true,
		1681	false,
		1682	true,
		1683	true,
		1684	true,
		1685	false,
		1686	false,
		1687	true,
		1688	true,
		1689	true,
		1690	false,
		1691	true,
		1692	true,
		1693	true,
		1694	true,
		1695	true,
		1696	false,
		1697	false,
		1698	false,
		1699	false,
		1700	false,
		1701	true,
		1702	true,
		1703	false,
		1704	true,
		1705	false,
		1706	false,
		1707	true,
		1708	false,
		1709	true,
		1710	false,
		1711	false,
		1712	false,
		1713	true,
		1714	false,
		1715	false,
		1716	false,
		1717	true,
		1718	true,
		1719	true,
		1720	true,
		1721	true,
		1722	true,
		1723	false,
		1724	false,
		1725	true,
		1726	false,
		1727	true,
		1728	true,
		1729	false,
		1730	true,
		1731	true,
		1732	true,
		1733	false,
		1734	});
		1735
		1736	const vec = c_ret_vector_256_bool();
		1737	try expect(vec[0] == true);
		1738	try expect(vec[1] == false);
		1739	try expect(vec[2] == true);
		1740	try expect(vec[3] == true);
		1741	try expect(vec[4] == false);
		1742	try expect(vec[5] == false);
		1743	try expect(vec[6] == false);
		1744	try expect(vec[7] == false);
		1745	try expect(vec[8] == false);
		1746	try expect(vec[9] == true);
		1747	try expect(vec[10] == false);
		1748	try expect(vec[11] == true);
		1749	try expect(vec[12] == false);
		1750	try expect(vec[13] == true);
		1751	try expect(vec[14] == false);
		1752	try expect(vec[15] == false);
		1753	try expect(vec[16] == true);
		1754	try expect(vec[17] == true);
		1755	try expect(vec[18] == true);
		1756	try expect(vec[19] == false);
		1757	try expect(vec[20] == false);
		1758	try expect(vec[21] == false);
		1759	try expect(vec[22] == true);
		1760	try expect(vec[23] == false);
		1761	try expect(vec[24] == true);
		1762	try expect(vec[25] == false);
		1763	try expect(vec[26] == false);
		1764	try expect(vec[27] == true);
		1765	try expect(vec[28] == true);
		1766	try expect(vec[29] == true);
		1767	try expect(vec[30] == false);
		1768	try expect(vec[31] == false);
		1769	try expect(vec[32] == true);
		1770	try expect(vec[33] == true);
		1771	try expect(vec[34] == true);
		1772	try expect(vec[35] == false);
		1773	try expect(vec[36] == true);
		1774	try expect(vec[37] == true);
		1775	try expect(vec[38] == true);
		1776	try expect(vec[39] == false);
		1777	try expect(vec[40] == true);
		1778	try expect(vec[41] == false);
		1779	try expect(vec[42] == true);
		1780	try expect(vec[43] == true);
		1781	try expect(vec[44] == false);
		1782	try expect(vec[45] == true);
		1783	try expect(vec[46] == false);
		1784	try expect(vec[47] == true);
		1785	try expect(vec[48] == true);
		1786	try expect(vec[49] == false);
		1787	try expect(vec[50] == false);
		1788	try expect(vec[51] == true);
		1789	try expect(vec[52] == true);
		1790	try expect(vec[53] == false);
		1791	try expect(vec[54] == false);
		1792	try expect(vec[55] == true);
		1793	try expect(vec[56] == false);
		1794	try expect(vec[57] == true);
		1795	try expect(vec[58] == true);
		1796	try expect(vec[59] == true);
		1797	try expect(vec[60] == false);
		1798	try expect(vec[61] == true);
		1799	try expect(vec[62] == true);
		1800	try expect(vec[63] == false);
		1801	try expect(vec[64] == true);
		1802	try expect(vec[65] == true);
		1803	try expect(vec[66] == false);
		1804	try expect(vec[67] == true);
		1805	try expect(vec[68] == false);
		1806	try expect(vec[69] == true);
		1807	try expect(vec[70] == true);
		1808	try expect(vec[71] == true);
		1809	try expect(vec[72] == false);
		1810	try expect(vec[73] == true);
		1811	try expect(vec[74] == true);
		1812	try expect(vec[75] == false);
		1813	try expect(vec[76] == true);
		1814	try expect(vec[77] == true);
		1815	try expect(vec[78] == true);
		1816	try expect(vec[79] == true);
		1817	try expect(vec[80] == false);
		1818	try expect(vec[81] == true);
		1819	try expect(vec[82] == false);
		1820	try expect(vec[83] == true);
		1821	try expect(vec[84] == true);
		1822	try expect(vec[85] == true);
		1823	try expect(vec[86] == false);
		1824	try expect(vec[87] == true);
		1825	try expect(vec[88] == false);
		1826	try expect(vec[89] == true);
		1827	try expect(vec[90] == false);
		1828	try expect(vec[91] == false);
		1829	try expect(vec[92] == true);
		1830	try expect(vec[93] == false);
		1831	try expect(vec[94] == false);
		1832	try expect(vec[95] == false);
		1833	try expect(vec[96] == true);
		1834	try expect(vec[97] == true);
		1835	try expect(vec[98] == false);
		1836	try expect(vec[99] == false);
		1837	try expect(vec[100] == false);
		1838	try expect(vec[101] == true);
		1839	try expect(vec[102] == true);
		1840	try expect(vec[103] == true);
		1841	try expect(vec[104] == false);
		1842	try expect(vec[105] == false);
		1843	try expect(vec[106] == false);
		1844	try expect(vec[107] == true);
		1845	try expect(vec[108] == false);
		1846	try expect(vec[109] == true);
		1847	try expect(vec[110] == true);
		1848	try expect(vec[111] == true);
		1849	try expect(vec[112] == true);
		1850	try expect(vec[113] == true);
		1851	try expect(vec[114] == true);
		1852	try expect(vec[115] == true);
		1853	try expect(vec[116] == true);
		1854	try expect(vec[117] == false);
		1855	try expect(vec[118] == true);
		1856	try expect(vec[119] == false);
		1857	try expect(vec[120] == true);
		1858	try expect(vec[121] == false);
		1859	try expect(vec[122] == false);
		1860	try expect(vec[123] == true);
		1861	try expect(vec[124] == true);
		1862	try expect(vec[125] == false);
		1863	try expect(vec[126] == true);
		1864	try expect(vec[127] == false);
		1865	try expect(vec[128] == false);
		1866	try expect(vec[129] == false);
		1867	try expect(vec[130] == false);
		1868	try expect(vec[131] == true);
		1869	try expect(vec[132] == false);
		1870	try expect(vec[133] == false);
		1871	try expect(vec[134] == true);
		1872	try expect(vec[135] == false);
		1873	try expect(vec[136] == false);
		1874	try expect(vec[137] == false);
		1875	try expect(vec[138] == false);
		1876	try expect(vec[139] == false);
		1877	try expect(vec[140] == false);
		1878	try expect(vec[141] == true);
		1879	try expect(vec[142] == false);
		1880	try expect(vec[143] == true);
		1881	try expect(vec[144] == false);
		1882	try expect(vec[145] == true);
		1883	try expect(vec[146] == true);
		1884	try expect(vec[147] == true);
		1885	try expect(vec[148] == false);
		1886	try expect(vec[149] == true);
		1887	try expect(vec[150] == true);
		1888	try expect(vec[151] == false);
		1889	try expect(vec[152] == true);
		1890	try expect(vec[153] == true);
		1891	try expect(vec[154] == false);
		1892	try expect(vec[155] == true);
		1893	try expect(vec[156] == true);
		1894	try expect(vec[157] == true);
		1895	try expect(vec[158] == true);
		1896	try expect(vec[159] == true);
		1897	try expect(vec[160] == true);
		1898	try expect(vec[161] == true);
		1899	try expect(vec[162] == false);
		1900	try expect(vec[163] == false);
		1901	try expect(vec[164] == false);
		1902	try expect(vec[165] == true);
		1903	try expect(vec[166] == false);
		1904	try expect(vec[167] == false);
		1905	try expect(vec[168] == true);
		1906	try expect(vec[169] == false);
		1907	try expect(vec[170] == true);
		1908	try expect(vec[171] == true);
		1909	try expect(vec[172] == true);
		1910	try expect(vec[173] == false);
		1911	try expect(vec[174] == false);
		1912	try expect(vec[175] == true);
		1913	try expect(vec[176] == true);
		1914	try expect(vec[177] == true);
		1915	try expect(vec[178] == true);
		1916	try expect(vec[179] == false);
		1917	try expect(vec[180] == true);
		1918	try expect(vec[181] == true);
		1919	try expect(vec[182] == false);
		1920	try expect(vec[183] == true);
		1921	try expect(vec[184] == false);
		1922	try expect(vec[185] == false);
		1923	try expect(vec[186] == false);
		1924	try expect(vec[187] == true);
		1925	try expect(vec[188] == true);
		1926	try expect(vec[189] == true);
		1927	try expect(vec[190] == true);
		1928	try expect(vec[191] == true);
		1929	try expect(vec[192] == true);
		1930	try expect(vec[193] == true);
		1931	try expect(vec[194] == true);
		1932	try expect(vec[195] == false);
		1933	try expect(vec[196] == false);
		1934	try expect(vec[197] == true);
		1935	try expect(vec[198] == false);
		1936	try expect(vec[199] == false);
		1937	try expect(vec[200] == false);
		1938	try expect(vec[201] == true);
		1939	try expect(vec[202] == true);
		1940	try expect(vec[203] == true);
		1941	try expect(vec[204] == true);
		1942	try expect(vec[205] == true);
		1943	try expect(vec[206] == true);
		1944	try expect(vec[207] == false);
		1945	try expect(vec[208] == false);
		1946	try expect(vec[209] == false);
		1947	try expect(vec[210] == true);
		1948	try expect(vec[211] == true);
		1949	try expect(vec[212] == true);
		1950	try expect(vec[213] == false);
		1951	try expect(vec[214] == true);
		1952	try expect(vec[215] == false);
		1953	try expect(vec[216] == true);
		1954	try expect(vec[217] == false);
		1955	try expect(vec[218] == true);
		1956	try expect(vec[219] == false);
		1957	try expect(vec[220] == true);
		1958	try expect(vec[221] == true);
		1959	try expect(vec[222] == true);
		1960	try expect(vec[223] == false);
		1961	try expect(vec[224] == true);
		1962	try expect(vec[225] == false);
		1963	try expect(vec[226] == true);
		1964	try expect(vec[227] == false);
		1965	try expect(vec[228] == true);
		1966	try expect(vec[229] == false);
		1967	try expect(vec[230] == true);
		1968	try expect(vec[231] == false);
		1969	try expect(vec[232] == false);
		1970	try expect(vec[233] == true);
		1971	try expect(vec[234] == false);
		1972	try expect(vec[235] == true);
		1973	try expect(vec[236] == true);
		1974	try expect(vec[237] == false);
		1975	try expect(vec[238] == false);
		1976	try expect(vec[239] == true);
		1977	try expect(vec[240] == false);
		1978	try expect(vec[241] == false);
		1979	try expect(vec[242] == false);
		1980	try expect(vec[243] == true);
		1981	try expect(vec[244] == true);
		1982	try expect(vec[245] == false);
		1983	try expect(vec[246] == false);
		1984	try expect(vec[247] == false);
		1985	try expect(vec[248] == false);
		1986	try expect(vec[249] == false);
		1987	try expect(vec[250] == true);
		1988	try expect(vec[251] == false);
		1989	try expect(vec[252] == true);
		1990	try expect(vec[253] == false);
		1991	try expect(vec[254] == false);
		1992	try expect(vec[255] == false);
		1993	}
		1994	{
		1995	c_vector_512_bool(.{
		1996	true,
		1997	true,
		1998	true,
		1999	true,
		2000	true,
		2001	false,
		2002	false,
		2003	true,
		2004	true,
		2005	true,
		2006	true,
		2007	false,
		2008	true,
		2009	true,
		2010	false,
		2011	false,
		2012	false,
		2013	true,
		2014	true,
		2015	true,
		2016	true,
		2017	true,
		2018	false,
		2019	false,
		2020	true,
		2021	true,
		2022	false,
		2023	false,
		2024	false,
		2025	false,
		2026	false,
		2027	true,
		2028	true,
		2029	false,
		2030	true,
		2031	true,
		2032	true,
		2033	true,
		2034	true,
		2035	true,
		2036	false,
		2037	true,
		2038	true,
		2039	false,
		2040	false,
		2041	false,
		2042	true,
		2043	true,
		2044	false,
		2045	true,
		2046	false,
		2047	true,
		2048	true,
		2049	false,
		2050	true,
		2051	false,
		2052	false,
		2053	true,
		2054	true,
		2055	false,
		2056	true,
		2057	true,
		2058	false,
		2059	true,
		2060	false,
		2061	true,
		2062	true,
		2063	true,
		2064	true,
		2065	true,
		2066	true,
		2067	true,
		2068	true,
		2069	true,
		2070	false,
		2071	true,
		2072	false,
		2073	true,
		2074	false,
		2075	false,
		2076	false,
		2077	true,
		2078	false,
		2079	true,
		2080	true,
		2081	false,
		2082	true,
		2083	true,
		2084	true,
		2085	false,
		2086	true,
		2087	true,
		2088	false,
		2089	true,
		2090	false,
		2091	true,
		2092	true,
		2093	false,
		2094	false,
		2095	false,
		2096	true,
		2097	true,
		2098	false,
		2099	true,
		2100	false,
		2101	false,
		2102	true,
		2103	false,
		2104	false,
		2105	true,
		2106	false,
		2107	false,
		2108	false,
		2109	false,
		2110	false,
		2111	true,
		2112	true,
		2113	false,
		2114	false,
		2115	false,
		2116	false,
		2117	true,
		2118	false,
		2119	false,
		2120	true,
		2121	true,
		2122	false,
		2123	true,
		2124	false,
		2125	true,
		2126	true,
		2127	false,
		2128	true,
		2129	false,
		2130	false,
		2131	false,
		2132	false,
		2133	true,
		2134	true,
		2135	false,
		2136	false,
		2137	false,
		2138	true,
		2139	true,
		2140	false,
		2141	false,
		2142	true,
		2143	true,
		2144	true,
		2145	true,
		2146	true,
		2147	true,
		2148	true,
		2149	false,
		2150	true,
		2151	false,
		2152	false,
		2153	true,
		2154	false,
		2155	true,
		2156	false,
		2157	true,
		2158	true,
		2159	true,
		2160	true,
		2161	true,
		2162	true,
		2163	true,
		2164	true,
		2165	false,
		2166	true,
		2167	true,
		2168	false,
		2169	true,
		2170	true,
		2171	false,
		2172	false,
		2173	false,
		2174	true,
		2175	false,
		2176	false,
		2177	true,
		2178	true,
		2179	true,
		2180	true,
		2181	true,
		2182	true,
		2183	true,
		2184	true,
		2185	true,
		2186	false,
		2187	true,
		2188	true,
		2189	false,
		2190	false,
		2191	true,
		2192	true,
		2193	false,
		2194	true,
		2195	true,
		2196	false,
		2197	true,
		2198	true,
		2199	false,
		2200	true,
		2201	true,
		2202	true,
		2203	true,
		2204	false,
		2205	true,
		2206	false,
		2207	true,
		2208	true,
		2209	false,
		2210	true,
		2211	false,
		2212	true,
		2213	false,
		2214	true,
		2215	false,
		2216	false,
		2217	true,
		2218	false,
		2219	false,
		2220	false,
		2221	true,
		2222	true,
		2223	false,
		2224	false,
		2225	false,
		2226	true,
		2227	false,
		2228	true,
		2229	false,
		2230	false,
		2231	false,
		2232	true,
		2233	true,
		2234	false,
		2235	false,
		2236	false,
		2237	false,
		2238	false,
		2239	true,
		2240	true,
		2241	false,
		2242	true,
		2243	false,
		2244	false,
		2245	true,
		2246	false,
		2247	false,
		2248	false,
		2249	true,
		2250	false,
		2251	false,
		2252	false,
		2253	false,
		2254	true,
		2255	true,
		2256	true,
		2257	true,
		2258	false,
		2259	true,
		2260	false,
		2261	false,
		2262	false,
		2263	true,
		2264	false,
		2265	false,
		2266	true,
		2267	true,
		2268	false,
		2269	false,
		2270	false,
		2271	false,
		2272	false,
		2273	true,
		2274	false,
		2275	true,
		2276	true,
		2277	true,
		2278	true,
		2279	true,
		2280	false,
		2281	false,
		2282	false,
		2283	false,
		2284	false,
		2285	false,
		2286	false,
		2287	false,
		2288	false,
		2289	true,
		2290	true,
		2291	true,
		2292	true,
		2293	true,
		2294	true,
		2295	false,
		2296	true,
		2297	false,
		2298	true,
		2299	true,
		2300	true,
		2301	false,
		2302	false,
		2303	true,
		2304	true,
		2305	true,
		2306	false,
		2307	true,
		2308	true,
		2309	true,
		2310	false,
		2311	true,
		2312	true,
		2313	true,
		2314	false,
		2315	true,
		2316	true,
		2317	false,
		2318	false,
		2319	true,
		2320	false,
		2321	false,
		2322	false,
		2323	false,
		2324	true,
		2325	false,
		2326	true,
		2327	true,
		2328	true,
		2329	true,
		2330	false,
		2331	false,
		2332	true,
		2333	false,
		2334	true,
		2335	false,
		2336	false,
		2337	false,
		2338	true,
		2339	false,
		2340	true,
		2341	false,
		2342	false,
		2343	true,
		2344	true,
		2345	true,
		2346	true,
		2347	false,
		2348	false,
		2349	false,
		2350	true,
		2351	true,
		2352	false,
		2353	true,
		2354	false,
		2355	false,
		2356	true,
		2357	false,
		2358	true,
		2359	false,
		2360	true,
		2361	true,
		2362	false,
		2363	false,
		2364	true,
		2365	true,
		2366	true,
		2367	true,
		2368	false,
		2369	false,
		2370	true,
		2371	false,
		2372	true,
		2373	true,
		2374	false,
		2375	true,
		2376	true,
		2377	false,
		2378	true,
		2379	true,
		2380	true,
		2381	false,
		2382	true,
		2383	true,
		2384	true,
		2385	false,
		2386	false,
		2387	true,
		2388	false,
		2389	true,
		2390	true,
		2391	true,
		2392	false,
		2393	false,
		2394	false,
		2395	false,
		2396	false,
		2397	true,
		2398	false,
		2399	false,
		2400	false,
		2401	false,
		2402	true,
		2403	false,
		2404	false,
		2405	true,
		2406	true,
		2407	false,
		2408	false,
		2409	false,
		2410	false,
		2411	true,
		2412	true,
		2413	true,
		2414	true,
		2415	true,
		2416	false,
		2417	false,
		2418	false,
		2419	true,
		2420	false,
		2421	false,
		2422	false,
		2423	false,
		2424	true,
		2425	false,
		2426	true,
		2427	false,
		2428	true,
		2429	true,
		2430	true,
		2431	true,
		2432	false,
		2433	false,
		2434	false,
		2435	false,
		2436	false,
		2437	true,
		2438	true,
		2439	true,
		2440	true,
		2441	true,
		2442	true,
		2443	true,
		2444	true,
		2445	true,
		2446	false,
		2447	false,
		2448	true,
		2449	false,
		2450	true,
		2451	false,
		2452	false,
		2453	true,
		2454	false,
		2455	false,
		2456	true,
		2457	true,
		2458	true,
		2459	true,
		2460	true,
		2461	true,
		2462	false,
		2463	true,
		2464	false,
		2465	false,
		2466	false,
		2467	true,
		2468	true,
		2469	false,
		2470	true,
		2471	true,
		2472	false,
		2473	false,
		2474	true,
		2475	true,
		2476	false,
		2477	false,
		2478	true,
		2479	true,
		2480	false,
		2481	true,
		2482	false,
		2483	true,
		2484	true,
		2485	true,
		2486	true,
		2487	true,
		2488	true,
		2489	true,
		2490	true,
		2491	true,
		2492	false,
		2493	true,
		2494	true,
		2495	true,
		2496	false,
		2497	false,
		2498	true,
		2499	false,
		2500	false,
		2501	false,
		2502	true,
		2503	true,
		2504	false,
		2505	true,
		2506	false,
		2507	true,
		2508	});
		2509
		2510	const vec = c_ret_vector_512_bool();
		2511	try expect(vec[0] == false);
		2512	try expect(vec[1] == true);
		2513	try expect(vec[2] == false);
		2514	try expect(vec[3] == false);
		2515	try expect(vec[4] == false);
		2516	try expect(vec[5] == true);
		2517	try expect(vec[6] == false);
		2518	try expect(vec[7] == false);
		2519	try expect(vec[8] == false);
		2520	try expect(vec[9] == true);
		2521	try expect(vec[10] == false);
		2522	try expect(vec[11] == false);
		2523	try expect(vec[12] == false);
		2524	try expect(vec[13] == true);
		2525	try expect(vec[14] == false);
		2526	try expect(vec[15] == true);
		2527	try expect(vec[16] == false);
		2528	try expect(vec[17] == false);
		2529	try expect(vec[18] == false);
		2530	try expect(vec[19] == false);
		2531	try expect(vec[20] == false);
		2532	try expect(vec[21] == false);
		2533	try expect(vec[22] == true);
		2534	try expect(vec[23] == true);
		2535	try expect(vec[24] == false);
		2536	try expect(vec[25] == false);
		2537	try expect(vec[26] == false);
		2538	try expect(vec[27] == false);
		2539	try expect(vec[28] == true);
		2540	try expect(vec[29] == true);
		2541	try expect(vec[30] == false);
		2542	try expect(vec[31] == true);
		2543	try expect(vec[32] == false);
		2544	try expect(vec[33] == true);
		2545	try expect(vec[34] == true);
		2546	try expect(vec[35] == true);
		2547	try expect(vec[36] == false);
		2548	try expect(vec[37] == false);
		2549	try expect(vec[38] == true);
		2550	try expect(vec[39] == true);
		2551	try expect(vec[40] == false);
		2552	try expect(vec[41] == false);
		2553	try expect(vec[42] == false);
		2554	try expect(vec[43] == false);
		2555	try expect(vec[44] == false);
		2556	try expect(vec[45] == true);
		2557	try expect(vec[46] == false);
		2558	try expect(vec[47] == true);
		2559	try expect(vec[48] == true);
		2560	try expect(vec[49] == false);
		2561	try expect(vec[50] == true);
		2562	try expect(vec[51] == true);
		2563	try expect(vec[52] == true);
		2564	try expect(vec[53] == true);
		2565	try expect(vec[54] == false);
		2566	try expect(vec[55] == false);
		2567	try expect(vec[56] == false);
		2568	try expect(vec[57] == true);
		2569	try expect(vec[58] == true);
		2570	try expect(vec[59] == false);
		2571	try expect(vec[60] == false);
		2572	try expect(vec[61] == false);
		2573	try expect(vec[62] == false);
		2574	try expect(vec[63] == true);
		2575	try expect(vec[64] == true);
		2576	try expect(vec[65] == true);
		2577	try expect(vec[66] == true);
		2578	try expect(vec[67] == true);
		2579	try expect(vec[68] == false);
		2580	try expect(vec[69] == false);
		2581	try expect(vec[70] == false);
		2582	try expect(vec[71] == false);
		2583	try expect(vec[72] == false);
		2584	try expect(vec[73] == true);
		2585	try expect(vec[74] == false);
		2586	try expect(vec[75] == true);
		2587	try expect(vec[76] == false);
		2588	try expect(vec[77] == false);
		2589	try expect(vec[78] == true);
		2590	try expect(vec[79] == true);
		2591	try expect(vec[80] == false);
		2592	try expect(vec[81] == false);
		2593	try expect(vec[82] == false);
		2594	try expect(vec[83] == true);
		2595	try expect(vec[84] == false);
		2596	try expect(vec[85] == true);
		2597	try expect(vec[86] == true);
		2598	try expect(vec[87] == true);
		2599	try expect(vec[88] == false);
		2600	try expect(vec[89] == true);
		2601	try expect(vec[90] == false);
		2602	try expect(vec[91] == false);
		2603	try expect(vec[92] == true);
		2604	try expect(vec[93] == true);
		2605	try expect(vec[94] == false);
		2606	try expect(vec[95] == true);
		2607	try expect(vec[96] == true);
		2608	try expect(vec[97] == false);
		2609	try expect(vec[98] == true);
		2610	try expect(vec[99] == false);
		2611	try expect(vec[100] == true);
		2612	try expect(vec[101] == true);
		2613	try expect(vec[102] == false);
		2614	try expect(vec[103] == true);
		2615	try expect(vec[104] == true);
		2616	try expect(vec[105] == false);
		2617	try expect(vec[106] == false);
		2618	try expect(vec[107] == false);
		2619	try expect(vec[108] == true);
		2620	try expect(vec[109] == false);
		2621	try expect(vec[110] == false);
		2622	try expect(vec[111] == false);
		2623	try expect(vec[112] == true);
		2624	try expect(vec[113] == true);
		2625	try expect(vec[114] == true);
		2626	try expect(vec[115] == false);
		2627	try expect(vec[116] == true);
		2628	try expect(vec[117] == false);
		2629	try expect(vec[118] == true);
		2630	try expect(vec[119] == false);
		2631	try expect(vec[120] == true);
		2632	try expect(vec[121] == true);
		2633	try expect(vec[122] == false);
		2634	try expect(vec[123] == true);
		2635	try expect(vec[124] == false);
		2636	try expect(vec[125] == true);
		2637	try expect(vec[126] == true);
		2638	try expect(vec[127] == true);
		2639	try expect(vec[128] == false);
		2640	try expect(vec[129] == true);
		2641	try expect(vec[130] == false);
		2642	try expect(vec[131] == false);
		2643	try expect(vec[132] == false);
		2644	try expect(vec[133] == false);
		2645	try expect(vec[134] == false);
		2646	try expect(vec[135] == false);
		2647	try expect(vec[136] == true);
		2648	try expect(vec[137] == false);
		2649	try expect(vec[138] == true);
		2650	try expect(vec[139] == false);
		2651	try expect(vec[140] == true);
		2652	try expect(vec[141] == true);
		2653	try expect(vec[142] == false);
		2654	try expect(vec[143] == true);
		2655	try expect(vec[144] == false);
		2656	try expect(vec[145] == false);
		2657	try expect(vec[146] == true);
		2658	try expect(vec[147] == false);
		2659	try expect(vec[148] == false);
		2660	try expect(vec[149] == true);
		2661	try expect(vec[150] == false);
		2662	try expect(vec[151] == true);
		2663	try expect(vec[152] == false);
		2664	try expect(vec[153] == true);
		2665	try expect(vec[154] == false);
		2666	try expect(vec[155] == false);
		2667	try expect(vec[156] == true);
		2668	try expect(vec[157] == false);
		2669	try expect(vec[158] == true);
		2670	try expect(vec[159] == true);
		2671	try expect(vec[160] == true);
		2672	try expect(vec[161] == false);
		2673	try expect(vec[162] == false);
		2674	try expect(vec[163] == true);
		2675	try expect(vec[164] == false);
		2676	try expect(vec[165] == false);
		2677	try expect(vec[166] == false);
		2678	try expect(vec[167] == true);
		2679	try expect(vec[168] == true);
		2680	try expect(vec[169] == true);
		2681	try expect(vec[170] == false);
		2682	try expect(vec[171] == true);
		2683	try expect(vec[172] == false);
		2684	try expect(vec[173] == false);
		2685	try expect(vec[174] == false);
		2686	try expect(vec[175] == false);
		2687	try expect(vec[176] == false);
		2688	try expect(vec[177] == true);
		2689	try expect(vec[178] == true);
		2690	try expect(vec[179] == false);
		2691	try expect(vec[180] == false);
		2692	try expect(vec[181] == true);
		2693	try expect(vec[182] == false);
		2694	try expect(vec[183] == false);
		2695	try expect(vec[184] == false);
		2696	try expect(vec[185] == false);
		2697	try expect(vec[186] == false);
		2698	try expect(vec[187] == true);
		2699	try expect(vec[188] == true);
		2700	try expect(vec[189] == false);
		2701	try expect(vec[190] == false);
		2702	try expect(vec[191] == false);
		2703	try expect(vec[192] == false);
		2704	try expect(vec[193] == false);
		2705	try expect(vec[194] == false);
		2706	try expect(vec[195] == true);
		2707	try expect(vec[196] == true);
		2708	try expect(vec[197] == false);
		2709	try expect(vec[198] == true);
		2710	try expect(vec[199] == true);
		2711	try expect(vec[200] == true);
		2712	try expect(vec[201] == true);
		2713	try expect(vec[202] == true);
		2714	try expect(vec[203] == true);
		2715	try expect(vec[204] == false);
		2716	try expect(vec[205] == false);
		2717	try expect(vec[206] == false);
		2718	try expect(vec[207] == false);
		2719	try expect(vec[208] == true);
		2720	try expect(vec[209] == false);
		2721	try expect(vec[210] == true);
		2722	try expect(vec[211] == true);
		2723	try expect(vec[212] == true);
		2724	try expect(vec[213] == true);
		2725	try expect(vec[214] == false);
		2726	try expect(vec[215] == false);
		2727	try expect(vec[216] == false);
		2728	try expect(vec[217] == true);
		2729	try expect(vec[218] == true);
		2730	try expect(vec[219] == false);
		2731	try expect(vec[220] == true);
		2732	try expect(vec[221] == true);
		2733	try expect(vec[222] == false);
		2734	try expect(vec[223] == false);
		2735	try expect(vec[224] == false);
		2736	try expect(vec[225] == true);
		2737	try expect(vec[226] == true);
		2738	try expect(vec[227] == true);
		2739	try expect(vec[228] == true);
		2740	try expect(vec[229] == false);
		2741	try expect(vec[230] == true);
		2742	try expect(vec[231] == false);
		2743	try expect(vec[232] == true);
		2744	try expect(vec[233] == true);
		2745	try expect(vec[234] == true);
		2746	try expect(vec[235] == true);
		2747	try expect(vec[236] == false);
		2748	try expect(vec[237] == true);
		2749	try expect(vec[238] == false);
		2750	try expect(vec[239] == true);
		2751	try expect(vec[240] == false);
		2752	try expect(vec[241] == true);
		2753	try expect(vec[242] == false);
		2754	try expect(vec[243] == false);
		2755	try expect(vec[244] == false);
		2756	try expect(vec[245] == true);
		2757	try expect(vec[246] == true);
		2758	try expect(vec[247] == false);
		2759	try expect(vec[248] == true);
		2760	try expect(vec[249] == false);
		2761	try expect(vec[250] == false);
		2762	try expect(vec[251] == false);
		2763	try expect(vec[252] == true);
		2764	try expect(vec[253] == true);
		2765	try expect(vec[254] == true);
		2766	try expect(vec[255] == true);
		2767	try expect(vec[256] == true);
		2768	try expect(vec[257] == false);
		2769	try expect(vec[258] == true);
		2770	try expect(vec[259] == true);
		2771	try expect(vec[260] == true);
		2772	try expect(vec[261] == true);
		2773	try expect(vec[262] == false);
		2774	try expect(vec[263] == true);
		2775	try expect(vec[264] == false);
		2776	try expect(vec[265] == false);
		2777	try expect(vec[266] == true);
		2778	try expect(vec[267] == false);
		2779	try expect(vec[268] == true);
		2780	try expect(vec[269] == false);
		2781	try expect(vec[270] == false);
		2782	try expect(vec[271] == true);
		2783	try expect(vec[272] == true);
		2784	try expect(vec[273] == false);
		2785	try expect(vec[274] == true);
		2786	try expect(vec[275] == false);
		2787	try expect(vec[276] == false);
		2788	try expect(vec[277] == true);
		2789	try expect(vec[278] == false);
		2790	try expect(vec[279] == false);
		2791	try expect(vec[280] == true);
		2792	try expect(vec[281] == true);
		2793	try expect(vec[282] == true);
		2794	try expect(vec[283] == false);
		2795	try expect(vec[284] == false);
		2796	try expect(vec[285] == true);
		2797	try expect(vec[286] == true);
		2798	try expect(vec[287] == true);
		2799	try expect(vec[288] == false);
		2800	try expect(vec[289] == false);
		2801	try expect(vec[290] == false);
		2802	try expect(vec[291] == false);
		2803	try expect(vec[292] == false);
		2804	try expect(vec[293] == false);
		2805	try expect(vec[294] == true);
		2806	try expect(vec[295] == false);
		2807	try expect(vec[296] == true);
		2808	try expect(vec[297] == false);
		2809	try expect(vec[298] == true);
		2810	try expect(vec[299] == true);
		2811	try expect(vec[300] == false);
		2812	try expect(vec[301] == false);
		2813	try expect(vec[302] == false);
		2814	try expect(vec[303] == false);
		2815	try expect(vec[304] == true);
		2816	try expect(vec[305] == true);
		2817	try expect(vec[306] == true);
		2818	try expect(vec[307] == true);
		2819	try expect(vec[308] == true);
		2820	try expect(vec[309] == false);
		2821	try expect(vec[310] == true);
		2822	try expect(vec[311] == true);
		2823	try expect(vec[312] == true);
		2824	try expect(vec[313] == true);
		2825	try expect(vec[314] == true);
		2826	try expect(vec[315] == false);
		2827	try expect(vec[316] == true);
		2828	try expect(vec[317] == true);
		2829	try expect(vec[318] == true);
		2830	try expect(vec[319] == false);
		2831	try expect(vec[320] == true);
		2832	try expect(vec[321] == false);
		2833	try expect(vec[322] == true);
		2834	try expect(vec[323] == true);
		2835	try expect(vec[324] == true);
		2836	try expect(vec[325] == false);
		2837	try expect(vec[326] == false);
		2838	try expect(vec[327] == true);
		2839	try expect(vec[328] == true);
		2840	try expect(vec[329] == true);
		2841	try expect(vec[330] == false);
		2842	try expect(vec[331] == false);
		2843	try expect(vec[332] == true);
		2844	try expect(vec[333] == true);
		2845	try expect(vec[334] == false);
		2846	try expect(vec[335] == true);
		2847	try expect(vec[336] == true);
		2848	try expect(vec[337] == true);
		2849	try expect(vec[338] == true);
		2850	try expect(vec[339] == true);
		2851	try expect(vec[340] == true);
		2852	try expect(vec[341] == false);
		2853	try expect(vec[342] == true);
		2854	try expect(vec[343] == false);
		2855	try expect(vec[344] == true);
		2856	try expect(vec[345] == false);
		2857	try expect(vec[346] == false);
		2858	try expect(vec[347] == false);
		2859	try expect(vec[348] == false);
		2860	try expect(vec[349] == true);
		2861	try expect(vec[350] == true);
		2862	try expect(vec[351] == true);
		2863	try expect(vec[352] == true);
		2864	try expect(vec[353] == false);
		2865	try expect(vec[354] == true);
		2866	try expect(vec[355] == false);
		2867	try expect(vec[356] == true);
		2868	try expect(vec[357] == true);
		2869	try expect(vec[358] == false);
		2870	try expect(vec[359] == true);
		2871	try expect(vec[360] == false);
		2872	try expect(vec[361] == false);
		2873	try expect(vec[362] == true);
		2874	try expect(vec[363] == false);
		2875	try expect(vec[364] == false);
		2876	try expect(vec[365] == false);
		2877	try expect(vec[366] == false);
		2878	try expect(vec[367] == false);
		2879	try expect(vec[368] == false);
		2880	try expect(vec[369] == false);
		2881	try expect(vec[370] == true);
		2882	try expect(vec[371] == false);
		2883	try expect(vec[372] == true);
		2884	try expect(vec[373] == true);
		2885	try expect(vec[374] == false);
		2886	try expect(vec[375] == false);
		2887	try expect(vec[376] == true);
		2888	try expect(vec[377] == false);
		2889	try expect(vec[378] == false);
		2890	try expect(vec[379] == true);
		2891	try expect(vec[380] == false);
		2892	try expect(vec[381] == false);
		2893	try expect(vec[382] == true);
		2894	try expect(vec[383] == false);
		2895	try expect(vec[384] == false);
		2896	try expect(vec[385] == false);
		2897	try expect(vec[386] == false);
		2898	try expect(vec[387] == true);
		2899	try expect(vec[388] == true);
		2900	try expect(vec[389] == true);
		2901	try expect(vec[390] == true);
		2902	try expect(vec[391] == true);
		2903	try expect(vec[392] == true);
		2904	try expect(vec[393] == true);
		2905	try expect(vec[394] == false);
		2906	try expect(vec[395] == true);
		2907	try expect(vec[396] == true);
		2908	try expect(vec[397] == false);
		2909	try expect(vec[398] == false);
		2910	try expect(vec[399] == false);
		2911	try expect(vec[400] == true);
		2912	try expect(vec[401] == false);
		2913	try expect(vec[402] == true);
		2914	try expect(vec[403] == true);
		2915	try expect(vec[404] == false);
		2916	try expect(vec[405] == true);
		2917	try expect(vec[406] == true);
		2918	try expect(vec[407] == true);
		2919	try expect(vec[408] == true);
		2920	try expect(vec[409] == false);
		2921	try expect(vec[410] == false);
		2922	try expect(vec[411] == false);
		2923	try expect(vec[412] == true);
		2924	try expect(vec[413] == true);
		2925	try expect(vec[414] == false);
		2926	try expect(vec[415] == true);
		2927	try expect(vec[416] == false);
		2928	try expect(vec[417] == true);
		2929	try expect(vec[418] == false);
		2930	try expect(vec[419] == false);
		2931	try expect(vec[420] == false);
		2932	try expect(vec[421] == false);
		2933	try expect(vec[422] == true);
		2934	try expect(vec[423] == true);
		2935	try expect(vec[424] == true);
		2936	try expect(vec[425] == false);
		2937	try expect(vec[426] == true);
		2938	try expect(vec[427] == false);
		2939	try expect(vec[428] == false);
		2940	try expect(vec[429] == false);
		2941	try expect(vec[430] == true);
		2942	try expect(vec[431] == true);
		2943	try expect(vec[432] == false);
		2944	try expect(vec[433] == true);
		2945	try expect(vec[434] == false);
		2946	try expect(vec[435] == false);
		2947	try expect(vec[436] == true);
		2948	try expect(vec[437] == true);
		2949	try expect(vec[438] == true);
		2950	try expect(vec[439] == true);
		2951	try expect(vec[440] == true);
		2952	try expect(vec[441] == true);
		2953	try expect(vec[442] == false);
		2954	try expect(vec[443] == false);
		2955	try expect(vec[444] == false);
		2956	try expect(vec[445] == true);
		2957	try expect(vec[446] == true);
		2958	try expect(vec[447] == true);
		2959	try expect(vec[448] == false);
		2960	try expect(vec[449] == false);
		2961	try expect(vec[450] == false);
		2962	try expect(vec[451] == false);
		2963	try expect(vec[452] == false);
		2964	try expect(vec[453] == false);
		2965	try expect(vec[454] == false);
		2966	try expect(vec[455] == false);
		2967	try expect(vec[456] == false);
		2968	try expect(vec[457] == false);
		2969	try expect(vec[458] == false);
		2970	try expect(vec[459] == true);
		2971	try expect(vec[460] == false);
		2972	try expect(vec[461] == false);
		2973	try expect(vec[462] == false);
		2974	try expect(vec[463] == true);
		2975	try expect(vec[464] == false);
		2976	try expect(vec[465] == false);
		2977	try expect(vec[466] == false);
		2978	try expect(vec[467] == false);
		2979	try expect(vec[468] == true);
		2980	try expect(vec[469] == true);
		2981	try expect(vec[470] == true);
		2982	try expect(vec[471] == true);
		2983	try expect(vec[472] == true);
		2984	try expect(vec[473] == false);
		2985	try expect(vec[474] == false);
		2986	try expect(vec[475] == true);
		2987	try expect(vec[476] == true);
		2988	try expect(vec[477] == true);
		2989	try expect(vec[478] == false);
		2990	try expect(vec[479] == true);
		2991	try expect(vec[480] == true);
		2992	try expect(vec[481] == true);
		2993	try expect(vec[482] == false);
		2994	try expect(vec[483] == true);
		2995	try expect(vec[484] == false);
		2996	try expect(vec[485] == true);
		2997	try expect(vec[486] == false);
		2998	try expect(vec[487] == true);
		2999	try expect(vec[488] == false);
		3000	try expect(vec[489] == true);
		3001	try expect(vec[490] == true);
		3002	try expect(vec[491] == true);
		3003	try expect(vec[492] == true);
		3004	try expect(vec[493] == false);
		3005	try expect(vec[494] == true);
		3006	try expect(vec[495] == true);
		3007	try expect(vec[496] == false);
		3008	try expect(vec[497] == true);
		3009	try expect(vec[498] == false);
		3010	try expect(vec[499] == false);
		3011	try expect(vec[500] == false);
		3012	try expect(vec[501] == false);
		3013	try expect(vec[502] == false);
		3014	try expect(vec[503] == false);
		3015	try expect(vec[504] == false);
		3016	try expect(vec[505] == false);
		3017	try expect(vec[506] == false);
		3018	try expect(vec[507] == true);
		3019	try expect(vec[508] == true);
		3020	try expect(vec[509] == false);
		3021	try expect(vec[510] == true);
		3022	try expect(vec[511] == false);
		3023	}
		3024	}
		3025
		3026	comptime {
		3027	skip: {
		3028	if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .wasm32) break :skip;
		3029	if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .x86_64) break :skip;
		3030
		3031	_ = struct {
		3032	export fn zig_vector_2_bool(vec: Vector2Bool) void {
		3033	expect(vec[0] == false) catch @panic("test failure");
		3034	expect(vec[1] == true) catch @panic("test failure");
		3035	}
		3036
		3037	export fn zig_vector_4_bool(vec: Vector4Bool) void {
		3038	expect(vec[0] == false) catch @panic("test failure");
		3039	expect(vec[1] == false) catch @panic("test failure");
		3040	expect(vec[2] == false) catch @panic("test failure");
		3041	expect(vec[3] == false) catch @panic("test failure");
		3042	}
		3043
		3044	export fn zig_vector_8_bool(vec: Vector8Bool) void {
		3045	expect(vec[0] == true) catch @panic("test failure");
		3046	expect(vec[1] == true) catch @panic("test failure");
		3047	expect(vec[2] == false) catch @panic("test failure");
		3048	expect(vec[3] == true) catch @panic("test failure");
		3049	expect(vec[4] == false) catch @panic("test failure");
		3050	expect(vec[5] == true) catch @panic("test failure");
		3051	expect(vec[6] == true) catch @panic("test failure");
		3052	expect(vec[7] == false) catch @panic("test failure");
		3053	}
		3054
		3055	export fn zig_vector_16_bool(vec: Vector16Bool) void {
		3056	expect(vec[0] == true) catch @panic("test failure");
		3057	expect(vec[1] == false) catch @panic("test failure");
		3058	expect(vec[2] == true) catch @panic("test failure");
		3059	expect(vec[3] == true) catch @panic("test failure");
		3060	expect(vec[4] == true) catch @panic("test failure");
		3061	expect(vec[5] == false) catch @panic("test failure");
		3062	expect(vec[6] == false) catch @panic("test failure");
		3063	expect(vec[7] == false) catch @panic("test failure");
		3064	expect(vec[8] == true) catch @panic("test failure");
		3065	expect(vec[9] == true) catch @panic("test failure");
		3066	expect(vec[10] == true) catch @panic("test failure");
		3067	expect(vec[11] == true) catch @panic("test failure");
		3068	expect(vec[12] == false) catch @panic("test failure");
		3069	expect(vec[13] == false) catch @panic("test failure");
		3070	expect(vec[14] == false) catch @panic("test failure");
		3071	expect(vec[15] == true) catch @panic("test failure");
		3072	}
		3073
		3074	export fn zig_vector_32_bool(vec: Vector32Bool) void {
		3075	expect(vec[0] == false) catch @panic("test failure");
		3076	expect(vec[1] == false) catch @panic("test failure");
		3077	expect(vec[2] == false) catch @panic("test failure");
		3078	expect(vec[3] == true) catch @panic("test failure");
		3079	expect(vec[4] == true) catch @panic("test failure");
		3080	expect(vec[5] == false) catch @panic("test failure");
		3081	expect(vec[6] == false) catch @panic("test failure");
		3082	expect(vec[7] == true) catch @panic("test failure");
		3083	expect(vec[8] == false) catch @panic("test failure");
		3084	expect(vec[9] == true) catch @panic("test failure");
		3085	expect(vec[10] == true) catch @panic("test failure");
		3086	expect(vec[11] == true) catch @panic("test failure");
		3087	expect(vec[12] == false) catch @panic("test failure");
		3088	expect(vec[13] == false) catch @panic("test failure");
		3089	expect(vec[14] == true) catch @panic("test failure");
		3090	expect(vec[15] == true) catch @panic("test failure");
		3091	expect(vec[16] == true) catch @panic("test failure");
		3092	expect(vec[17] == true) catch @panic("test failure");
		3093	expect(vec[18] == true) catch @panic("test failure");
		3094	expect(vec[19] == false) catch @panic("test failure");
		3095	expect(vec[20] == true) catch @panic("test failure");
		3096	expect(vec[21] == true) catch @panic("test failure");
		3097	expect(vec[22] == true) catch @panic("test failure");
		3098	expect(vec[23] == false) catch @panic("test failure");
		3099	expect(vec[24] == false) catch @panic("test failure");
		3100	expect(vec[25] == true) catch @panic("test failure");
		3101	expect(vec[26] == true) catch @panic("test failure");
		3102	expect(vec[27] == false) catch @panic("test failure");
		3103	expect(vec[28] == true) catch @panic("test failure");
		3104	expect(vec[29] == true) catch @panic("test failure");
		3105	expect(vec[30] == false) catch @panic("test failure");
		3106	expect(vec[31] == true) catch @panic("test failure");
		3107	}
		3108
		3109	export fn zig_vector_64_bool(vec: Vector64Bool) void {
		3110	expect(vec[0] == true) catch @panic("test failure");
		3111	expect(vec[1] == true) catch @panic("test failure");
		3112	expect(vec[2] == false) catch @panic("test failure");
		3113	expect(vec[3] == true) catch @panic("test failure");
		3114	expect(vec[4] == false) catch @panic("test failure");
		3115	expect(vec[5] == true) catch @panic("test failure");
		3116	expect(vec[6] == false) catch @panic("test failure");
		3117	expect(vec[7] == false) catch @panic("test failure");
		3118	expect(vec[8] == true) catch @panic("test failure");
		3119	expect(vec[9] == true) catch @panic("test failure");
		3120	expect(vec[10] == true) catch @panic("test failure");
		3121	expect(vec[11] == true) catch @panic("test failure");
		3122	expect(vec[12] == true) catch @panic("test failure");
		3123	expect(vec[13] == true) catch @panic("test failure");
		3124	expect(vec[14] == true) catch @panic("test failure");
		3125	expect(vec[15] == false) catch @panic("test failure");
		3126	expect(vec[16] == false) catch @panic("test failure");
		3127	expect(vec[17] == true) catch @panic("test failure");
		3128	expect(vec[18] == true) catch @panic("test failure");
		3129	expect(vec[19] == false) catch @panic("test failure");
		3130	expect(vec[20] == true) catch @panic("test failure");
		3131	expect(vec[21] == true) catch @panic("test failure");
		3132	expect(vec[22] == true) catch @panic("test failure");
		3133	expect(vec[23] == true) catch @panic("test failure");
		3134	expect(vec[24] == false) catch @panic("test failure");
		3135	expect(vec[25] == false) catch @panic("test failure");
		3136	expect(vec[26] == true) catch @panic("test failure");
		3137	expect(vec[27] == false) catch @panic("test failure");
		3138	expect(vec[28] == false) catch @panic("test failure");
		3139	expect(vec[29] == true) catch @panic("test failure");
		3140	expect(vec[30] == false) catch @panic("test failure");
		3141	expect(vec[31] == true) catch @panic("test failure");
		3142	expect(vec[32] == false) catch @panic("test failure");
		3143	expect(vec[33] == true) catch @panic("test failure");
		3144	expect(vec[34] == true) catch @panic("test failure");
		3145	expect(vec[35] == false) catch @panic("test failure");
		3146	expect(vec[36] == true) catch @panic("test failure");
		3147	expect(vec[37] == true) catch @panic("test failure");
		3148	expect(vec[38] == false) catch @panic("test failure");
		3149	expect(vec[39] == false) catch @panic("test failure");
		3150	expect(vec[40] == true) catch @panic("test failure");
		3151	expect(vec[41] == true) catch @panic("test failure");
		3152	expect(vec[42] == true) catch @panic("test failure");
		3153	expect(vec[43] == true) catch @panic("test failure");
		3154	expect(vec[44] == true) catch @panic("test failure");
		3155	expect(vec[45] == false) catch @panic("test failure");
		3156	expect(vec[46] == true) catch @panic("test failure");
		3157	expect(vec[47] == false) catch @panic("test failure");
		3158	expect(vec[48] == false) catch @panic("test failure");
		3159	expect(vec[49] == false) catch @panic("test failure");
		3160	expect(vec[50] == false) catch @panic("test failure");
		3161	expect(vec[51] == false) catch @panic("test failure");
		3162	expect(vec[52] == true) catch @panic("test failure");
		3163	expect(vec[53] == false) catch @panic("test failure");
		3164	expect(vec[54] == false) catch @panic("test failure");
		3165	expect(vec[55] == true) catch @panic("test failure");
		3166	expect(vec[56] == true) catch @panic("test failure");
		3167	expect(vec[57] == false) catch @panic("test failure");
		3168	expect(vec[58] == false) catch @panic("test failure");
		3169	expect(vec[59] == false) catch @panic("test failure");
		3170	expect(vec[60] == true) catch @panic("test failure");
		3171	expect(vec[61] == true) catch @panic("test failure");
		3172	expect(vec[62] == true) catch @panic("test failure");
		3173	expect(vec[63] == true) catch @panic("test failure");
		3174	}
		3175
		3176	export fn zig_vector_128_bool(vec: Vector128Bool) void {
		3177	expect(vec[0] == true) catch @panic("test failure");
		3178	expect(vec[1] == true) catch @panic("test failure");
		3179	expect(vec[2] == false) catch @panic("test failure");
		3180	expect(vec[3] == true) catch @panic("test failure");
		3181	expect(vec[4] == true) catch @panic("test failure");
		3182	expect(vec[5] == false) catch @panic("test failure");
		3183	expect(vec[6] == false) catch @panic("test failure");
		3184	expect(vec[7] == true) catch @panic("test failure");
		3185	expect(vec[8] == true) catch @panic("test failure");
		3186	expect(vec[9] == true) catch @panic("test failure");
		3187	expect(vec[10] == true) catch @panic("test failure");
		3188	expect(vec[11] == true) catch @panic("test failure");
		3189	expect(vec[12] == false) catch @panic("test failure");
		3190	expect(vec[13] == false) catch @panic("test failure");
		3191	expect(vec[14] == false) catch @panic("test failure");
		3192	expect(vec[15] == true) catch @panic("test failure");
		3193	expect(vec[16] == false) catch @panic("test failure");
		3194	expect(vec[17] == true) catch @panic("test failure");
		3195	expect(vec[18] == false) catch @panic("test failure");
		3196	expect(vec[19] == false) catch @panic("test failure");
		3197	expect(vec[20] == true) catch @panic("test failure");
		3198	expect(vec[21] == false) catch @panic("test failure");
		3199	expect(vec[22] == true) catch @panic("test failure");
		3200	expect(vec[23] == false) catch @panic("test failure");
		3201	expect(vec[24] == false) catch @panic("test failure");
		3202	expect(vec[25] == false) catch @panic("test failure");
		3203	expect(vec[26] == true) catch @panic("test failure");
		3204	expect(vec[27] == false) catch @panic("test failure");
		3205	expect(vec[28] == true) catch @panic("test failure");
		3206	expect(vec[29] == true) catch @panic("test failure");
		3207	expect(vec[30] == false) catch @panic("test failure");
		3208	expect(vec[31] == true) catch @panic("test failure");
		3209	expect(vec[32] == false) catch @panic("test failure");
		3210	expect(vec[33] == true) catch @panic("test failure");
		3211	expect(vec[34] == true) catch @panic("test failure");
		3212	expect(vec[35] == false) catch @panic("test failure");
		3213	expect(vec[36] == false) catch @panic("test failure");
		3214	expect(vec[37] == false) catch @panic("test failure");
		3215	expect(vec[38] == false) catch @panic("test failure");
		3216	expect(vec[39] == true) catch @panic("test failure");
		3217	expect(vec[40] == true) catch @panic("test failure");
		3218	expect(vec[41] == false) catch @panic("test failure");
		3219	expect(vec[42] == true) catch @panic("test failure");
		3220	expect(vec[43] == false) catch @panic("test failure");
		3221	expect(vec[44] == false) catch @panic("test failure");
		3222	expect(vec[45] == true) catch @panic("test failure");
		3223	expect(vec[46] == false) catch @panic("test failure");
		3224	expect(vec[47] == false) catch @panic("test failure");
		3225	expect(vec[48] == true) catch @panic("test failure");
		3226	expect(vec[49] == true) catch @panic("test failure");
		3227	expect(vec[50] == false) catch @panic("test failure");
		3228	expect(vec[51] == false) catch @panic("test failure");
		3229	expect(vec[52] == true) catch @panic("test failure");
		3230	expect(vec[53] == false) catch @panic("test failure");
		3231	expect(vec[54] == false) catch @panic("test failure");
		3232	expect(vec[55] == true) catch @panic("test failure");
		3233	expect(vec[56] == true) catch @panic("test failure");
		3234	expect(vec[57] == true) catch @panic("test failure");
		3235	expect(vec[58] == true) catch @panic("test failure");
		3236	expect(vec[59] == true) catch @panic("test failure");
		3237	expect(vec[60] == true) catch @panic("test failure");
		3238	expect(vec[61] == true) catch @panic("test failure");
		3239	expect(vec[62] == true) catch @panic("test failure");
		3240	expect(vec[63] == false) catch @panic("test failure");
		3241	expect(vec[64] == false) catch @panic("test failure");
		3242	expect(vec[65] == true) catch @panic("test failure");
		3243	expect(vec[66] == false) catch @panic("test failure");
		3244	expect(vec[67] == true) catch @panic("test failure");
		3245	expect(vec[68] == true) catch @panic("test failure");
		3246	expect(vec[69] == true) catch @panic("test failure");
		3247	expect(vec[70] == true) catch @panic("test failure");
		3248	expect(vec[71] == false) catch @panic("test failure");
		3249	expect(vec[72] == false) catch @panic("test failure");
		3250	expect(vec[73] == false) catch @panic("test failure");
		3251	expect(vec[74] == true) catch @panic("test failure");
		3252	expect(vec[75] == true) catch @panic("test failure");
		3253	expect(vec[76] == false) catch @panic("test failure");
		3254	expect(vec[77] == true) catch @panic("test failure");
		3255	expect(vec[78] == true) catch @panic("test failure");
		3256	expect(vec[79] == true) catch @panic("test failure");
		3257	expect(vec[80] == true) catch @panic("test failure");
		3258	expect(vec[81] == false) catch @panic("test failure");
		3259	expect(vec[82] == true) catch @panic("test failure");
		3260	expect(vec[83] == true) catch @panic("test failure");
		3261	expect(vec[84] == true) catch @panic("test failure");
		3262	expect(vec[85] == true) catch @panic("test failure");
		3263	expect(vec[86] == true) catch @panic("test failure");
		3264	expect(vec[87] == true) catch @panic("test failure");
		3265	expect(vec[88] == false) catch @panic("test failure");
		3266	expect(vec[89] == true) catch @panic("test failure");
		3267	expect(vec[90] == true) catch @panic("test failure");
		3268	expect(vec[91] == true) catch @panic("test failure");
		3269	expect(vec[92] == true) catch @panic("test failure");
		3270	expect(vec[93] == true) catch @panic("test failure");
		3271	expect(vec[94] == true) catch @panic("test failure");
		3272	expect(vec[95] == false) catch @panic("test failure");
		3273	expect(vec[96] == false) catch @panic("test failure");
		3274	expect(vec[97] == false) catch @panic("test failure");
		3275	expect(vec[98] == true) catch @panic("test failure");
		3276	expect(vec[99] == true) catch @panic("test failure");
		3277	expect(vec[100] == true) catch @panic("test failure");
		3278	expect(vec[101] == true) catch @panic("test failure");
		3279	expect(vec[102] == true) catch @panic("test failure");
		3280	expect(vec[103] == true) catch @panic("test failure");
		3281	expect(vec[104] == true) catch @panic("test failure");
		3282	expect(vec[105] == false) catch @panic("test failure");
		3283	expect(vec[106] == false) catch @panic("test failure");
		3284	expect(vec[107] == false) catch @panic("test failure");
		3285	expect(vec[108] == false) catch @panic("test failure");
		3286	expect(vec[109] == false) catch @panic("test failure");
		3287	expect(vec[110] == true) catch @panic("test failure");
		3288	expect(vec[111] == true) catch @panic("test failure");
		3289	expect(vec[112] == true) catch @panic("test failure");
		3290	expect(vec[113] == false) catch @panic("test failure");
		3291	expect(vec[114] == false) catch @panic("test failure");
		3292	expect(vec[115] == false) catch @panic("test failure");
		3293	expect(vec[116] == false) catch @panic("test failure");
		3294	expect(vec[117] == false) catch @panic("test failure");
		3295	expect(vec[118] == true) catch @panic("test failure");
		3296	expect(vec[119] == false) catch @panic("test failure");
		3297	expect(vec[120] == false) catch @panic("test failure");
		3298	expect(vec[121] == false) catch @panic("test failure");
		3299	expect(vec[122] == false) catch @panic("test failure");
		3300	expect(vec[123] == true) catch @panic("test failure");
		3301	expect(vec[124] == true) catch @panic("test failure");
		3302	expect(vec[125] == false) catch @panic("test failure");
		3303	expect(vec[126] == true) catch @panic("test failure");
		3304	expect(vec[127] == false) catch @panic("test failure");
		3305	}
		3306
		3307	export fn zig_vector_256_bool(vec: Vector256Bool) void {
		3308	expect(vec[0] == false) catch @panic("test failure");
		3309	expect(vec[1] == false) catch @panic("test failure");
		3310	expect(vec[2] == false) catch @panic("test failure");
		3311	expect(vec[3] == false) catch @panic("test failure");
		3312	expect(vec[4] == true) catch @panic("test failure");
		3313	expect(vec[5] == true) catch @panic("test failure");
		3314	expect(vec[6] == false) catch @panic("test failure");
		3315	expect(vec[7] == false) catch @panic("test failure");
		3316	expect(vec[8] == false) catch @panic("test failure");
		3317	expect(vec[9] == true) catch @panic("test failure");
		3318	expect(vec[10] == true) catch @panic("test failure");
		3319	expect(vec[11] == false) catch @panic("test failure");
		3320	expect(vec[12] == true) catch @panic("test failure");
		3321	expect(vec[13] == false) catch @panic("test failure");
		3322	expect(vec[14] == false) catch @panic("test failure");
		3323	expect(vec[15] == false) catch @panic("test failure");
		3324	expect(vec[16] == false) catch @panic("test failure");
		3325	expect(vec[17] == true) catch @panic("test failure");
		3326	expect(vec[18] == true) catch @panic("test failure");
		3327	expect(vec[19] == true) catch @panic("test failure");
		3328	expect(vec[20] == false) catch @panic("test failure");
		3329	expect(vec[21] == true) catch @panic("test failure");
		3330	expect(vec[22] == true) catch @panic("test failure");
		3331	expect(vec[23] == false) catch @panic("test failure");
		3332	expect(vec[24] == true) catch @panic("test failure");
		3333	expect(vec[25] == false) catch @panic("test failure");
		3334	expect(vec[26] == false) catch @panic("test failure");
		3335	expect(vec[27] == true) catch @panic("test failure");
		3336	expect(vec[28] == true) catch @panic("test failure");
		3337	expect(vec[29] == true) catch @panic("test failure");
		3338	expect(vec[30] == false) catch @panic("test failure");
		3339	expect(vec[31] == true) catch @panic("test failure");
		3340	expect(vec[32] == false) catch @panic("test failure");
		3341	expect(vec[33] == true) catch @panic("test failure");
		3342	expect(vec[34] == false) catch @panic("test failure");
		3343	expect(vec[35] == false) catch @panic("test failure");
		3344	expect(vec[36] == false) catch @panic("test failure");
		3345	expect(vec[37] == true) catch @panic("test failure");
		3346	expect(vec[38] == false) catch @panic("test failure");
		3347	expect(vec[39] == false) catch @panic("test failure");
		3348	expect(vec[40] == true) catch @panic("test failure");
		3349	expect(vec[41] == true) catch @panic("test failure");
		3350	expect(vec[42] == false) catch @panic("test failure");
		3351	expect(vec[43] == true) catch @panic("test failure");
		3352	expect(vec[44] == true) catch @panic("test failure");
		3353	expect(vec[45] == false) catch @panic("test failure");
		3354	expect(vec[46] == true) catch @panic("test failure");
		3355	expect(vec[47] == false) catch @panic("test failure");
		3356	expect(vec[48] == true) catch @panic("test failure");
		3357	expect(vec[49] == false) catch @panic("test failure");
		3358	expect(vec[50] == true) catch @panic("test failure");
		3359	expect(vec[51] == false) catch @panic("test failure");
		3360	expect(vec[52] == true) catch @panic("test failure");
		3361	expect(vec[53] == true) catch @panic("test failure");
		3362	expect(vec[54] == true) catch @panic("test failure");
		3363	expect(vec[55] == false) catch @panic("test failure");
		3364	expect(vec[56] == false) catch @panic("test failure");
		3365	expect(vec[57] == true) catch @panic("test failure");
		3366	expect(vec[58] == true) catch @panic("test failure");
		3367	expect(vec[59] == false) catch @panic("test failure");
		3368	expect(vec[60] == false) catch @panic("test failure");
		3369	expect(vec[61] == true) catch @panic("test failure");
		3370	expect(vec[62] == true) catch @panic("test failure");
		3371	expect(vec[63] == false) catch @panic("test failure");
		3372	expect(vec[64] == false) catch @panic("test failure");
		3373	expect(vec[65] == false) catch @panic("test failure");
		3374	expect(vec[66] == true) catch @panic("test failure");
		3375	expect(vec[67] == true) catch @panic("test failure");
		3376	expect(vec[68] == false) catch @panic("test failure");
		3377	expect(vec[69] == true) catch @panic("test failure");
		3378	expect(vec[70] == false) catch @panic("test failure");
		3379	expect(vec[71] == true) catch @panic("test failure");
		3380	expect(vec[72] == false) catch @panic("test failure");
		3381	expect(vec[73] == true) catch @panic("test failure");
		3382	expect(vec[74] == false) catch @panic("test failure");
		3383	expect(vec[75] == false) catch @panic("test failure");
		3384	expect(vec[76] == true) catch @panic("test failure");
		3385	expect(vec[77] == false) catch @panic("test failure");
		3386	expect(vec[78] == false) catch @panic("test failure");
		3387	expect(vec[79] == false) catch @panic("test failure");
		3388	expect(vec[80] == false) catch @panic("test failure");
		3389	expect(vec[81] == false) catch @panic("test failure");
		3390	expect(vec[82] == true) catch @panic("test failure");
		3391	expect(vec[83] == false) catch @panic("test failure");
		3392	expect(vec[84] == false) catch @panic("test failure");
		3393	expect(vec[85] == false) catch @panic("test failure");
		3394	expect(vec[86] == true) catch @panic("test failure");
		3395	expect(vec[87] == true) catch @panic("test failure");
		3396	expect(vec[88] == true) catch @panic("test failure");
		3397	expect(vec[89] == false) catch @panic("test failure");
		3398	expect(vec[90] == true) catch @panic("test failure");
		3399	expect(vec[91] == false) catch @panic("test failure");
		3400	expect(vec[92] == true) catch @panic("test failure");
		3401	expect(vec[93] == false) catch @panic("test failure");
		3402	expect(vec[94] == true) catch @panic("test failure");
		3403	expect(vec[95] == true) catch @panic("test failure");
		3404	expect(vec[96] == true) catch @panic("test failure");
		3405	expect(vec[97] == true) catch @panic("test failure");
		3406	expect(vec[98] == false) catch @panic("test failure");
		3407	expect(vec[99] == true) catch @panic("test failure");
		3408	expect(vec[100] == false) catch @panic("test failure");
		3409	expect(vec[101] == true) catch @panic("test failure");
		3410	expect(vec[102] == true) catch @panic("test failure");
		3411	expect(vec[103] == false) catch @panic("test failure");
		3412	expect(vec[104] == false) catch @panic("test failure");
		3413	expect(vec[105] == true) catch @panic("test failure");
		3414	expect(vec[106] == false) catch @panic("test failure");
		3415	expect(vec[107] == true) catch @panic("test failure");
		3416	expect(vec[108] == false) catch @panic("test failure");
		3417	expect(vec[109] == false) catch @panic("test failure");
		3418	expect(vec[110] == false) catch @panic("test failure");
		3419	expect(vec[111] == false) catch @panic("test failure");
		3420	expect(vec[112] == false) catch @panic("test failure");
		3421	expect(vec[113] == false) catch @panic("test failure");
		3422	expect(vec[114] == false) catch @panic("test failure");
		3423	expect(vec[115] == false) catch @panic("test failure");
		3424	expect(vec[116] == false) catch @panic("test failure");
		3425	expect(vec[117] == false) catch @panic("test failure");
		3426	expect(vec[118] == false) catch @panic("test failure");
		3427	expect(vec[119] == false) catch @panic("test failure");
		3428	expect(vec[120] == false) catch @panic("test failure");
		3429	expect(vec[121] == false) catch @panic("test failure");
		3430	expect(vec[122] == true) catch @panic("test failure");
		3431	expect(vec[123] == true) catch @panic("test failure");
		3432	expect(vec[124] == false) catch @panic("test failure");
		3433	expect(vec[125] == false) catch @panic("test failure");
		3434	expect(vec[126] == false) catch @panic("test failure");
		3435	expect(vec[127] == true) catch @panic("test failure");
		3436	expect(vec[128] == true) catch @panic("test failure");
		3437	expect(vec[129] == true) catch @panic("test failure");
		3438	expect(vec[130] == true) catch @panic("test failure");
		3439	expect(vec[131] == false) catch @panic("test failure");
		3440	expect(vec[132] == false) catch @panic("test failure");
		3441	expect(vec[133] == false) catch @panic("test failure");
		3442	expect(vec[134] == true) catch @panic("test failure");
		3443	expect(vec[135] == true) catch @panic("test failure");
		3444	expect(vec[136] == false) catch @panic("test failure");
		3445	expect(vec[137] == false) catch @panic("test failure");
		3446	expect(vec[138] == true) catch @panic("test failure");
		3447	expect(vec[139] == true) catch @panic("test failure");
		3448	expect(vec[140] == true) catch @panic("test failure");
		3449	expect(vec[141] == true) catch @panic("test failure");
		3450	expect(vec[142] == true) catch @panic("test failure");
		3451	expect(vec[143] == false) catch @panic("test failure");
		3452	expect(vec[144] == true) catch @panic("test failure");
		3453	expect(vec[145] == true) catch @panic("test failure");
		3454	expect(vec[146] == true) catch @panic("test failure");
		3455	expect(vec[147] == false) catch @panic("test failure");
		3456	expect(vec[148] == false) catch @panic("test failure");
		3457	expect(vec[149] == false) catch @panic("test failure");
		3458	expect(vec[150] == false) catch @panic("test failure");
		3459	expect(vec[151] == false) catch @panic("test failure");
		3460	expect(vec[152] == false) catch @panic("test failure");
		3461	expect(vec[153] == false) catch @panic("test failure");
		3462	expect(vec[154] == true) catch @panic("test failure");
		3463	expect(vec[155] == false) catch @panic("test failure");
		3464	expect(vec[156] == false) catch @panic("test failure");
		3465	expect(vec[157] == false) catch @panic("test failure");
		3466	expect(vec[158] == true) catch @panic("test failure");
		3467	expect(vec[159] == true) catch @panic("test failure");
		3468	expect(vec[160] == false) catch @panic("test failure");
		3469	expect(vec[161] == true) catch @panic("test failure");
		3470	expect(vec[162] == false) catch @panic("test failure");
		3471	expect(vec[163] == false) catch @panic("test failure");
		3472	expect(vec[164] == false) catch @panic("test failure");
		3473	expect(vec[165] == true) catch @panic("test failure");
		3474	expect(vec[166] == false) catch @panic("test failure");
		3475	expect(vec[167] == true) catch @panic("test failure");
		3476	expect(vec[168] == false) catch @panic("test failure");
		3477	expect(vec[169] == false) catch @panic("test failure");
		3478	expect(vec[170] == false) catch @panic("test failure");
		3479	expect(vec[171] == false) catch @panic("test failure");
		3480	expect(vec[172] == true) catch @panic("test failure");
		3481	expect(vec[173] == true) catch @panic("test failure");
		3482	expect(vec[174] == true) catch @panic("test failure");
		3483	expect(vec[175] == true) catch @panic("test failure");
		3484	expect(vec[176] == true) catch @panic("test failure");
		3485	expect(vec[177] == true) catch @panic("test failure");
		3486	expect(vec[178] == false) catch @panic("test failure");
		3487	expect(vec[179] == true) catch @panic("test failure");
		3488	expect(vec[180] == true) catch @panic("test failure");
		3489	expect(vec[181] == false) catch @panic("test failure");
		3490	expect(vec[182] == true) catch @panic("test failure");
		3491	expect(vec[183] == false) catch @panic("test failure");
		3492	expect(vec[184] == true) catch @panic("test failure");
		3493	expect(vec[185] == false) catch @panic("test failure");
		3494	expect(vec[186] == true) catch @panic("test failure");
		3495	expect(vec[187] == false) catch @panic("test failure");
		3496	expect(vec[188] == true) catch @panic("test failure");
		3497	expect(vec[189] == false) catch @panic("test failure");
		3498	expect(vec[190] == false) catch @panic("test failure");
		3499	expect(vec[191] == false) catch @panic("test failure");
		3500	expect(vec[192] == false) catch @panic("test failure");
		3501	expect(vec[193] == true) catch @panic("test failure");
		3502	expect(vec[194] == true) catch @panic("test failure");
		3503	expect(vec[195] == true) catch @panic("test failure");
		3504	expect(vec[196] == false) catch @panic("test failure");
		3505	expect(vec[197] == false) catch @panic("test failure");
		3506	expect(vec[198] == true) catch @panic("test failure");
		3507	expect(vec[199] == false) catch @panic("test failure");
		3508	expect(vec[200] == false) catch @panic("test failure");
		3509	expect(vec[201] == true) catch @panic("test failure");
		3510	expect(vec[202] == true) catch @panic("test failure");
		3511	expect(vec[203] == false) catch @panic("test failure");
		3512	expect(vec[204] == true) catch @panic("test failure");
		3513	expect(vec[205] == false) catch @panic("test failure");
		3514	expect(vec[206] == true) catch @panic("test failure");
		3515	expect(vec[207] == false) catch @panic("test failure");
		3516	expect(vec[208] == false) catch @panic("test failure");
		3517	expect(vec[209] == false) catch @panic("test failure");
		3518	expect(vec[210] == true) catch @panic("test failure");
		3519	expect(vec[211] == true) catch @panic("test failure");
		3520	expect(vec[212] == false) catch @panic("test failure");
		3521	expect(vec[213] == false) catch @panic("test failure");
		3522	expect(vec[214] == false) catch @panic("test failure");
		3523	expect(vec[215] == true) catch @panic("test failure");
		3524	expect(vec[216] == false) catch @panic("test failure");
		3525	expect(vec[217] == true) catch @panic("test failure");
		3526	expect(vec[218] == true) catch @panic("test failure");
		3527	expect(vec[219] == true) catch @panic("test failure");
		3528	expect(vec[220] == false) catch @panic("test failure");
		3529	expect(vec[221] == true) catch @panic("test failure");
		3530	expect(vec[222] == false) catch @panic("test failure");
		3531	expect(vec[223] == true) catch @panic("test failure");
		3532	expect(vec[224] == false) catch @panic("test failure");
		3533	expect(vec[225] == false) catch @panic("test failure");
		3534	expect(vec[226] == false) catch @panic("test failure");
		3535	expect(vec[227] == true) catch @panic("test failure");
		3536	expect(vec[228] == true) catch @panic("test failure");
		3537	expect(vec[229] == false) catch @panic("test failure");
		3538	expect(vec[230] == false) catch @panic("test failure");
		3539	expect(vec[231] == false) catch @panic("test failure");
		3540	expect(vec[232] == false) catch @panic("test failure");
		3541	expect(vec[233] == false) catch @panic("test failure");
		3542	expect(vec[234] == true) catch @panic("test failure");
		3543	expect(vec[235] == false) catch @panic("test failure");
		3544	expect(vec[236] == false) catch @panic("test failure");
		3545	expect(vec[237] == false) catch @panic("test failure");
		3546	expect(vec[238] == true) catch @panic("test failure");
		3547	expect(vec[239] == false) catch @panic("test failure");
		3548	expect(vec[240] == true) catch @panic("test failure");
		3549	expect(vec[241] == true) catch @panic("test failure");
		3550	expect(vec[242] == true) catch @panic("test failure");
		3551	expect(vec[243] == false) catch @panic("test failure");
		3552	expect(vec[244] == false) catch @panic("test failure");
		3553	expect(vec[245] == true) catch @panic("test failure");
		3554	expect(vec[246] == false) catch @panic("test failure");
		3555	expect(vec[247] == false) catch @panic("test failure");
		3556	expect(vec[248] == false) catch @panic("test failure");
		3557	expect(vec[249] == true) catch @panic("test failure");
		3558	expect(vec[250] == false) catch @panic("test failure");
		3559	expect(vec[251] == false) catch @panic("test failure");
		3560	expect(vec[252] == true) catch @panic("test failure");
		3561	expect(vec[253] == true) catch @panic("test failure");
		3562	expect(vec[254] == true) catch @panic("test failure");
		3563	expect(vec[255] == true) catch @panic("test failure");
		3564	}
		3565
		3566	export fn zig_vector_512_bool(vec: Vector512Bool) void {
		3567	expect(vec[0] == false) catch @panic("test failure");
		3568	expect(vec[1] == true) catch @panic("test failure");
		3569	expect(vec[2] == true) catch @panic("test failure");
		3570	expect(vec[3] == false) catch @panic("test failure");
		3571	expect(vec[4] == true) catch @panic("test failure");
		3572	expect(vec[5] == false) catch @panic("test failure");
		3573	expect(vec[6] == true) catch @panic("test failure");
		3574	expect(vec[7] == false) catch @panic("test failure");
		3575	expect(vec[8] == false) catch @panic("test failure");
		3576	expect(vec[9] == false) catch @panic("test failure");
		3577	expect(vec[10] == false) catch @panic("test failure");
		3578	expect(vec[11] == false) catch @panic("test failure");
		3579	expect(vec[12] == true) catch @panic("test failure");
		3580	expect(vec[13] == false) catch @panic("test failure");
		3581	expect(vec[14] == true) catch @panic("test failure");
		3582	expect(vec[15] == false) catch @panic("test failure");
		3583	expect(vec[16] == false) catch @panic("test failure");
		3584	expect(vec[17] == false) catch @panic("test failure");
		3585	expect(vec[18] == true) catch @panic("test failure");
		3586	expect(vec[19] == true) catch @panic("test failure");
		3587	expect(vec[20] == true) catch @panic("test failure");
		3588	expect(vec[21] == true) catch @panic("test failure");
		3589	expect(vec[22] == false) catch @panic("test failure");
		3590	expect(vec[23] == false) catch @panic("test failure");
		3591	expect(vec[24] == false) catch @panic("test failure");
		3592	expect(vec[25] == true) catch @panic("test failure");
		3593	expect(vec[26] == true) catch @panic("test failure");
		3594	expect(vec[27] == false) catch @panic("test failure");
		3595	expect(vec[28] == true) catch @panic("test failure");
		3596	expect(vec[29] == true) catch @panic("test failure");
		3597	expect(vec[30] == false) catch @panic("test failure");
		3598	expect(vec[31] == false) catch @panic("test failure");
		3599	expect(vec[32] == true) catch @panic("test failure");
		3600	expect(vec[33] == true) catch @panic("test failure");
		3601	expect(vec[34] == false) catch @panic("test failure");
		3602	expect(vec[35] == false) catch @panic("test failure");
		3603	expect(vec[36] == false) catch @panic("test failure");
		3604	expect(vec[37] == false) catch @panic("test failure");
		3605	expect(vec[38] == false) catch @panic("test failure");
		3606	expect(vec[39] == false) catch @panic("test failure");
		3607	expect(vec[40] == false) catch @panic("test failure");
		3608	expect(vec[41] == true) catch @panic("test failure");
		3609	expect(vec[42] == true) catch @panic("test failure");
		3610	expect(vec[43] == true) catch @panic("test failure");
		3611	expect(vec[44] == false) catch @panic("test failure");
		3612	expect(vec[45] == true) catch @panic("test failure");
		3613	expect(vec[46] == true) catch @panic("test failure");
		3614	expect(vec[47] == true) catch @panic("test failure");
		3615	expect(vec[48] == true) catch @panic("test failure");
		3616	expect(vec[49] == true) catch @panic("test failure");
		3617	expect(vec[50] == false) catch @panic("test failure");
		3618	expect(vec[51] == true) catch @panic("test failure");
		3619	expect(vec[52] == true) catch @panic("test failure");
		3620	expect(vec[53] == true) catch @panic("test failure");
		3621	expect(vec[54] == false) catch @panic("test failure");
		3622	expect(vec[55] == true) catch @panic("test failure");
		3623	expect(vec[56] == false) catch @panic("test failure");
		3624	expect(vec[57] == false) catch @panic("test failure");
		3625	expect(vec[58] == true) catch @panic("test failure");
		3626	expect(vec[59] == false) catch @panic("test failure");
		3627	expect(vec[60] == true) catch @panic("test failure");
		3628	expect(vec[61] == true) catch @panic("test failure");
		3629	expect(vec[62] == false) catch @panic("test failure");
		3630	expect(vec[63] == false) catch @panic("test failure");
		3631	expect(vec[64] == false) catch @panic("test failure");
		3632	expect(vec[65] == true) catch @panic("test failure");
		3633	expect(vec[66] == true) catch @panic("test failure");
		3634	expect(vec[67] == true) catch @panic("test failure");
		3635	expect(vec[68] == true) catch @panic("test failure");
		3636	expect(vec[69] == false) catch @panic("test failure");
		3637	expect(vec[70] == false) catch @panic("test failure");
		3638	expect(vec[71] == true) catch @panic("test failure");
		3639	expect(vec[72] == true) catch @panic("test failure");
		3640	expect(vec[73] == false) catch @panic("test failure");
		3641	expect(vec[74] == true) catch @panic("test failure");
		3642	expect(vec[75] == true) catch @panic("test failure");
		3643	expect(vec[76] == false) catch @panic("test failure");
		3644	expect(vec[77] == false) catch @panic("test failure");
		3645	expect(vec[78] == true) catch @panic("test failure");
		3646	expect(vec[79] == false) catch @panic("test failure");
		3647	expect(vec[80] == false) catch @panic("test failure");
		3648	expect(vec[81] == false) catch @panic("test failure");
		3649	expect(vec[82] == true) catch @panic("test failure");
		3650	expect(vec[83] == true) catch @panic("test failure");
		3651	expect(vec[84] == true) catch @panic("test failure");
		3652	expect(vec[85] == false) catch @panic("test failure");
		3653	expect(vec[86] == false) catch @panic("test failure");
		3654	expect(vec[87] == true) catch @panic("test failure");
		3655	expect(vec[88] == false) catch @panic("test failure");
		3656	expect(vec[89] == true) catch @panic("test failure");
		3657	expect(vec[90] == false) catch @panic("test failure");
		3658	expect(vec[91] == false) catch @panic("test failure");
		3659	expect(vec[92] == true) catch @panic("test failure");
		3660	expect(vec[93] == false) catch @panic("test failure");
		3661	expect(vec[94] == false) catch @panic("test failure");
		3662	expect(vec[95] == true) catch @panic("test failure");
		3663	expect(vec[96] == true) catch @panic("test failure");
		3664	expect(vec[97] == false) catch @panic("test failure");
		3665	expect(vec[98] == false) catch @panic("test failure");
		3666	expect(vec[99] == false) catch @panic("test failure");
		3667	expect(vec[100] == false) catch @panic("test failure");
		3668	expect(vec[101] == true) catch @panic("test failure");
		3669	expect(vec[102] == false) catch @panic("test failure");
		3670	expect(vec[103] == false) catch @panic("test failure");
		3671	expect(vec[104] == false) catch @panic("test failure");
		3672	expect(vec[105] == false) catch @panic("test failure");
		3673	expect(vec[106] == false) catch @panic("test failure");
		3674	expect(vec[107] == false) catch @panic("test failure");
		3675	expect(vec[108] == true) catch @panic("test failure");
		3676	expect(vec[109] == true) catch @panic("test failure");
		3677	expect(vec[110] == true) catch @panic("test failure");
		3678	expect(vec[111] == true) catch @panic("test failure");
		3679	expect(vec[112] == true) catch @panic("test failure");
		3680	expect(vec[113] == false) catch @panic("test failure");
		3681	expect(vec[114] == false) catch @panic("test failure");
		3682	expect(vec[115] == false) catch @panic("test failure");
		3683	expect(vec[116] == false) catch @panic("test failure");
		3684	expect(vec[117] == true) catch @panic("test failure");
		3685	expect(vec[118] == true) catch @panic("test failure");
		3686	expect(vec[119] == false) catch @panic("test failure");
		3687	expect(vec[120] == true) catch @panic("test failure");
		3688	expect(vec[121] == true) catch @panic("test failure");
		3689	expect(vec[122] == false) catch @panic("test failure");
		3690	expect(vec[123] == false) catch @panic("test failure");
		3691	expect(vec[124] == true) catch @panic("test failure");
		3692	expect(vec[125] == false) catch @panic("test failure");
		3693	expect(vec[126] == false) catch @panic("test failure");
		3694	expect(vec[127] == false) catch @panic("test failure");
		3695	expect(vec[128] == false) catch @panic("test failure");
		3696	expect(vec[129] == true) catch @panic("test failure");
		3697	expect(vec[130] == true) catch @panic("test failure");
		3698	expect(vec[131] == true) catch @panic("test failure");
		3699	expect(vec[132] == true) catch @panic("test failure");
		3700	expect(vec[133] == false) catch @panic("test failure");
		3701	expect(vec[134] == false) catch @panic("test failure");
		3702	expect(vec[135] == false) catch @panic("test failure");
		3703	expect(vec[136] == false) catch @panic("test failure");
		3704	expect(vec[137] == true) catch @panic("test failure");
		3705	expect(vec[138] == false) catch @panic("test failure");
		3706	expect(vec[139] == false) catch @panic("test failure");
		3707	expect(vec[140] == false) catch @panic("test failure");
		3708	expect(vec[141] == false) catch @panic("test failure");
		3709	expect(vec[142] == true) catch @panic("test failure");
		3710	expect(vec[143] == true) catch @panic("test failure");
		3711	expect(vec[144] == false) catch @panic("test failure");
		3712	expect(vec[145] == true) catch @panic("test failure");
		3713	expect(vec[146] == false) catch @panic("test failure");
		3714	expect(vec[147] == true) catch @panic("test failure");
		3715	expect(vec[148] == false) catch @panic("test failure");
		3716	expect(vec[149] == false) catch @panic("test failure");
		3717	expect(vec[150] == true) catch @panic("test failure");
		3718	expect(vec[151] == true) catch @panic("test failure");
		3719	expect(vec[152] == false) catch @panic("test failure");
		3720	expect(vec[153] == true) catch @panic("test failure");
		3721	expect(vec[154] == true) catch @panic("test failure");
		3722	expect(vec[155] == false) catch @panic("test failure");
		3723	expect(vec[156] == false) catch @panic("test failure");
		3724	expect(vec[157] == false) catch @panic("test failure");
		3725	expect(vec[158] == true) catch @panic("test failure");
		3726	expect(vec[159] == false) catch @panic("test failure");
		3727	expect(vec[160] == false) catch @panic("test failure");
		3728	expect(vec[161] == false) catch @panic("test failure");
		3729	expect(vec[162] == false) catch @panic("test failure");
		3730	expect(vec[163] == true) catch @panic("test failure");
		3731	expect(vec[164] == true) catch @panic("test failure");
		3732	expect(vec[165] == false) catch @panic("test failure");
		3733	expect(vec[166] == false) catch @panic("test failure");
		3734	expect(vec[167] == true) catch @panic("test failure");
		3735	expect(vec[168] == false) catch @panic("test failure");
		3736	expect(vec[169] == true) catch @panic("test failure");
		3737	expect(vec[170] == true) catch @panic("test failure");
		3738	expect(vec[171] == false) catch @panic("test failure");
		3739	expect(vec[172] == false) catch @panic("test failure");
		3740	expect(vec[173] == false) catch @panic("test failure");
		3741	expect(vec[174] == false) catch @panic("test failure");
		3742	expect(vec[175] == false) catch @panic("test failure");
		3743	expect(vec[176] == false) catch @panic("test failure");
		3744	expect(vec[177] == true) catch @panic("test failure");
		3745	expect(vec[178] == false) catch @panic("test failure");
		3746	expect(vec[179] == false) catch @panic("test failure");
		3747	expect(vec[180] == false) catch @panic("test failure");
		3748	expect(vec[181] == false) catch @panic("test failure");
		3749	expect(vec[182] == false) catch @panic("test failure");
		3750	expect(vec[183] == false) catch @panic("test failure");
		3751	expect(vec[184] == true) catch @panic("test failure");
		3752	expect(vec[185] == false) catch @panic("test failure");
		3753	expect(vec[186] == false) catch @panic("test failure");
		3754	expect(vec[187] == false) catch @panic("test failure");
		3755	expect(vec[188] == false) catch @panic("test failure");
		3756	expect(vec[189] == true) catch @panic("test failure");
		3757	expect(vec[190] == false) catch @panic("test failure");
		3758	expect(vec[191] == false) catch @panic("test failure");
		3759	expect(vec[192] == false) catch @panic("test failure");
		3760	expect(vec[193] == false) catch @panic("test failure");
		3761	expect(vec[194] == false) catch @panic("test failure");
		3762	expect(vec[195] == false) catch @panic("test failure");
		3763	expect(vec[196] == true) catch @panic("test failure");
		3764	expect(vec[197] == true) catch @panic("test failure");
		3765	expect(vec[198] == true) catch @panic("test failure");
		3766	expect(vec[199] == false) catch @panic("test failure");
		3767	expect(vec[200] == true) catch @panic("test failure");
		3768	expect(vec[201] == true) catch @panic("test failure");
		3769	expect(vec[202] == false) catch @panic("test failure");
		3770	expect(vec[203] == false) catch @panic("test failure");
		3771	expect(vec[204] == false) catch @panic("test failure");
		3772	expect(vec[205] == false) catch @panic("test failure");
		3773	expect(vec[206] == false) catch @panic("test failure");
		3774	expect(vec[207] == true) catch @panic("test failure");
		3775	expect(vec[208] == true) catch @panic("test failure");
		3776	expect(vec[209] == false) catch @panic("test failure");
		3777	expect(vec[210] == false) catch @panic("test failure");
		3778	expect(vec[211] == false) catch @panic("test failure");
		3779	expect(vec[212] == true) catch @panic("test failure");
		3780	expect(vec[213] == false) catch @panic("test failure");
		3781	expect(vec[214] == false) catch @panic("test failure");
		3782	expect(vec[215] == true) catch @panic("test failure");
		3783	expect(vec[216] == true) catch @panic("test failure");
		3784	expect(vec[217] == true) catch @panic("test failure");
		3785	expect(vec[218] == false) catch @panic("test failure");
		3786	expect(vec[219] == false) catch @panic("test failure");
		3787	expect(vec[220] == true) catch @panic("test failure");
		3788	expect(vec[221] == false) catch @panic("test failure");
		3789	expect(vec[222] == true) catch @panic("test failure");
		3790	expect(vec[223] == true) catch @panic("test failure");
		3791	expect(vec[224] == true) catch @panic("test failure");
		3792	expect(vec[225] == true) catch @panic("test failure");
		3793	expect(vec[226] == false) catch @panic("test failure");
		3794	expect(vec[227] == true) catch @panic("test failure");
		3795	expect(vec[228] == false) catch @panic("test failure");
		3796	expect(vec[229] == false) catch @panic("test failure");
		3797	expect(vec[230] == false) catch @panic("test failure");
		3798	expect(vec[231] == true) catch @panic("test failure");
		3799	expect(vec[232] == false) catch @panic("test failure");
		3800	expect(vec[233] == false) catch @panic("test failure");
		3801	expect(vec[234] == false) catch @panic("test failure");
		3802	expect(vec[235] == false) catch @panic("test failure");
		3803	expect(vec[236] == false) catch @panic("test failure");
		3804	expect(vec[237] == false) catch @panic("test failure");
		3805	expect(vec[238] == false) catch @panic("test failure");
		3806	expect(vec[239] == true) catch @panic("test failure");
		3807	expect(vec[240] == false) catch @panic("test failure");
		3808	expect(vec[241] == false) catch @panic("test failure");
		3809	expect(vec[242] == false) catch @panic("test failure");
		3810	expect(vec[243] == true) catch @panic("test failure");
		3811	expect(vec[244] == true) catch @panic("test failure");
		3812	expect(vec[245] == true) catch @panic("test failure");
		3813	expect(vec[246] == true) catch @panic("test failure");
		3814	expect(vec[247] == false) catch @panic("test failure");
		3815	expect(vec[248] == true) catch @panic("test failure");
		3816	expect(vec[249] == true) catch @panic("test failure");
		3817	expect(vec[250] == false) catch @panic("test failure");
		3818	expect(vec[251] == false) catch @panic("test failure");
		3819	expect(vec[252] == false) catch @panic("test failure");
		3820	expect(vec[253] == true) catch @panic("test failure");
		3821	expect(vec[254] == false) catch @panic("test failure");
		3822	expect(vec[255] == false) catch @panic("test failure");
		3823	expect(vec[256] == true) catch @panic("test failure");
		3824	expect(vec[257] == true) catch @panic("test failure");
		3825	expect(vec[258] == false) catch @panic("test failure");
		3826	expect(vec[259] == true) catch @panic("test failure");
		3827	expect(vec[260] == false) catch @panic("test failure");
		3828	expect(vec[261] == true) catch @panic("test failure");
		3829	expect(vec[262] == true) catch @panic("test failure");
		3830	expect(vec[263] == false) catch @panic("test failure");
		3831	expect(vec[264] == false) catch @panic("test failure");
		3832	expect(vec[265] == false) catch @panic("test failure");
		3833	expect(vec[266] == false) catch @panic("test failure");
		3834	expect(vec[267] == true) catch @panic("test failure");
		3835	expect(vec[268] == false) catch @panic("test failure");
		3836	expect(vec[269] == true) catch @panic("test failure");
		3837	expect(vec[270] == true) catch @panic("test failure");
		3838	expect(vec[271] == false) catch @panic("test failure");
		3839	expect(vec[272] == false) catch @panic("test failure");
		3840	expect(vec[273] == true) catch @panic("test failure");
		3841	expect(vec[274] == true) catch @panic("test failure");
		3842	expect(vec[275] == true) catch @panic("test failure");
		3843	expect(vec[276] == false) catch @panic("test failure");
		3844	expect(vec[277] == true) catch @panic("test failure");
		3845	expect(vec[278] == false) catch @panic("test failure");
		3846	expect(vec[279] == false) catch @panic("test failure");
		3847	expect(vec[280] == true) catch @panic("test failure");
		3848	expect(vec[281] == true) catch @panic("test failure");
		3849	expect(vec[282] == false) catch @panic("test failure");
		3850	expect(vec[283] == true) catch @panic("test failure");
		3851	expect(vec[284] == false) catch @panic("test failure");
		3852	expect(vec[285] == true) catch @panic("test failure");
		3853	expect(vec[286] == true) catch @panic("test failure");
		3854	expect(vec[287] == true) catch @panic("test failure");
		3855	expect(vec[288] == true) catch @panic("test failure");
		3856	expect(vec[289] == true) catch @panic("test failure");
		3857	expect(vec[290] == true) catch @panic("test failure");
		3858	expect(vec[291] == true) catch @panic("test failure");
		3859	expect(vec[292] == true) catch @panic("test failure");
		3860	expect(vec[293] == true) catch @panic("test failure");
		3861	expect(vec[294] == true) catch @panic("test failure");
		3862	expect(vec[295] == false) catch @panic("test failure");
		3863	expect(vec[296] == true) catch @panic("test failure");
		3864	expect(vec[297] == false) catch @panic("test failure");
		3865	expect(vec[298] == true) catch @panic("test failure");
		3866	expect(vec[299] == false) catch @panic("test failure");
		3867	expect(vec[300] == true) catch @panic("test failure");
		3868	expect(vec[301] == true) catch @panic("test failure");
		3869	expect(vec[302] == false) catch @panic("test failure");
		3870	expect(vec[303] == true) catch @panic("test failure");
		3871	expect(vec[304] == false) catch @panic("test failure");
		3872	expect(vec[305] == true) catch @panic("test failure");
		3873	expect(vec[306] == false) catch @panic("test failure");
		3874	expect(vec[307] == true) catch @panic("test failure");
		3875	expect(vec[308] == true) catch @panic("test failure");
		3876	expect(vec[309] == false) catch @panic("test failure");
		3877	expect(vec[310] == true) catch @panic("test failure");
		3878	expect(vec[311] == true) catch @panic("test failure");
		3879	expect(vec[312] == true) catch @panic("test failure");
		3880	expect(vec[313] == false) catch @panic("test failure");
		3881	expect(vec[314] == false) catch @panic("test failure");
		3882	expect(vec[315] == false) catch @panic("test failure");
		3883	expect(vec[316] == false) catch @panic("test failure");
		3884	expect(vec[317] == true) catch @panic("test failure");
		3885	expect(vec[318] == true) catch @panic("test failure");
		3886	expect(vec[319] == true) catch @panic("test failure");
		3887	expect(vec[320] == true) catch @panic("test failure");
		3888	expect(vec[321] == true) catch @panic("test failure");
		3889	expect(vec[322] == true) catch @panic("test failure");
		3890	expect(vec[323] == true) catch @panic("test failure");
		3891	expect(vec[324] == true) catch @panic("test failure");
		3892	expect(vec[325] == true) catch @panic("test failure");
		3893	expect(vec[326] == false) catch @panic("test failure");
		3894	expect(vec[327] == true) catch @panic("test failure");
		3895	expect(vec[328] == false) catch @panic("test failure");
		3896	expect(vec[329] == false) catch @panic("test failure");
		3897	expect(vec[330] == true) catch @panic("test failure");
		3898	expect(vec[331] == false) catch @panic("test failure");
		3899	expect(vec[332] == false) catch @panic("test failure");
		3900	expect(vec[333] == false) catch @panic("test failure");
		3901	expect(vec[334] == false) catch @panic("test failure");
		3902	expect(vec[335] == false) catch @panic("test failure");
		3903	expect(vec[336] == false) catch @panic("test failure");
		3904	expect(vec[337] == false) catch @panic("test failure");
		3905	expect(vec[338] == false) catch @panic("test failure");
		3906	expect(vec[339] == false) catch @panic("test failure");
		3907	expect(vec[340] == false) catch @panic("test failure");
		3908	expect(vec[341] == false) catch @panic("test failure");
		3909	expect(vec[342] == true) catch @panic("test failure");
		3910	expect(vec[343] == true) catch @panic("test failure");
		3911	expect(vec[344] == false) catch @panic("test failure");
		3912	expect(vec[345] == false) catch @panic("test failure");
		3913	expect(vec[346] == false) catch @panic("test failure");
		3914	expect(vec[347] == false) catch @panic("test failure");
		3915	expect(vec[348] == false) catch @panic("test failure");
		3916	expect(vec[349] == true) catch @panic("test failure");
		3917	expect(vec[350] == true) catch @panic("test failure");
		3918	expect(vec[351] == true) catch @panic("test failure");
		3919	expect(vec[352] == true) catch @panic("test failure");
		3920	expect(vec[353] == false) catch @panic("test failure");
		3921	expect(vec[354] == false) catch @panic("test failure");
		3922	expect(vec[355] == false) catch @panic("test failure");
		3923	expect(vec[356] == false) catch @panic("test failure");
		3924	expect(vec[357] == true) catch @panic("test failure");
		3925	expect(vec[358] == true) catch @panic("test failure");
		3926	expect(vec[359] == false) catch @panic("test failure");
		3927	expect(vec[360] == false) catch @panic("test failure");
		3928	expect(vec[361] == false) catch @panic("test failure");
		3929	expect(vec[362] == true) catch @panic("test failure");
		3930	expect(vec[363] == true) catch @panic("test failure");
		3931	expect(vec[364] == false) catch @panic("test failure");
		3932	expect(vec[365] == false) catch @panic("test failure");
		3933	expect(vec[366] == false) catch @panic("test failure");
		3934	expect(vec[367] == false) catch @panic("test failure");
		3935	expect(vec[368] == false) catch @panic("test failure");
		3936	expect(vec[369] == true) catch @panic("test failure");
		3937	expect(vec[370] == true) catch @panic("test failure");
		3938	expect(vec[371] == false) catch @panic("test failure");
		3939	expect(vec[372] == true) catch @panic("test failure");
		3940	expect(vec[373] == true) catch @panic("test failure");
		3941	expect(vec[374] == false) catch @panic("test failure");
		3942	expect(vec[375] == true) catch @panic("test failure");
		3943	expect(vec[376] == true) catch @panic("test failure");
		3944	expect(vec[377] == false) catch @panic("test failure");
		3945	expect(vec[378] == true) catch @panic("test failure");
		3946	expect(vec[379] == true) catch @panic("test failure");
		3947	expect(vec[380] == false) catch @panic("test failure");
		3948	expect(vec[381] == true) catch @panic("test failure");
		3949	expect(vec[382] == true) catch @panic("test failure");
		3950	expect(vec[383] == false) catch @panic("test failure");
		3951	expect(vec[384] == true) catch @panic("test failure");
		3952	expect(vec[385] == false) catch @panic("test failure");
		3953	expect(vec[386] == true) catch @panic("test failure");
		3954	expect(vec[387] == true) catch @panic("test failure");
		3955	expect(vec[388] == true) catch @panic("test failure");
		3956	expect(vec[389] == true) catch @panic("test failure");
		3957	expect(vec[390] == false) catch @panic("test failure");
		3958	expect(vec[391] == false) catch @panic("test failure");
		3959	expect(vec[392] == false) catch @panic("test failure");
		3960	expect(vec[393] == true) catch @panic("test failure");
		3961	expect(vec[394] == true) catch @panic("test failure");
		3962	expect(vec[395] == true) catch @panic("test failure");
		3963	expect(vec[396] == true) catch @panic("test failure");
		3964	expect(vec[397] == false) catch @panic("test failure");
		3965	expect(vec[398] == true) catch @panic("test failure");
		3966	expect(vec[399] == true) catch @panic("test failure");
		3967	expect(vec[400] == true) catch @panic("test failure");
		3968	expect(vec[401] == false) catch @panic("test failure");
		3969	expect(vec[402] == false) catch @panic("test failure");
		3970	expect(vec[403] == true) catch @panic("test failure");
		3971	expect(vec[404] == false) catch @panic("test failure");
		3972	expect(vec[405] == false) catch @panic("test failure");
		3973	expect(vec[406] == false) catch @panic("test failure");
		3974	expect(vec[407] == true) catch @panic("test failure");
		3975	expect(vec[408] == true) catch @panic("test failure");
		3976	expect(vec[409] == true) catch @panic("test failure");
		3977	expect(vec[410] == false) catch @panic("test failure");
		3978	expect(vec[411] == true) catch @panic("test failure");
		3979	expect(vec[412] == false) catch @panic("test failure");
		3980	expect(vec[413] == false) catch @panic("test failure");
		3981	expect(vec[414] == false) catch @panic("test failure");
		3982	expect(vec[415] == true) catch @panic("test failure");
		3983	expect(vec[416] == false) catch @panic("test failure");
		3984	expect(vec[417] == false) catch @panic("test failure");
		3985	expect(vec[418] == true) catch @panic("test failure");
		3986	expect(vec[419] == true) catch @panic("test failure");
		3987	expect(vec[420] == true) catch @panic("test failure");
		3988	expect(vec[421] == true) catch @panic("test failure");
		3989	expect(vec[422] == false) catch @panic("test failure");
		3990	expect(vec[423] == true) catch @panic("test failure");
		3991	expect(vec[424] == true) catch @panic("test failure");
		3992	expect(vec[425] == false) catch @panic("test failure");
		3993	expect(vec[426] == false) catch @panic("test failure");
		3994	expect(vec[427] == false) catch @panic("test failure");
		3995	expect(vec[428] == true) catch @panic("test failure");
		3996	expect(vec[429] == false) catch @panic("test failure");
		3997	expect(vec[430] == true) catch @panic("test failure");
		3998	expect(vec[431] == true) catch @panic("test failure");
		3999	expect(vec[432] == false) catch @panic("test failure");
		4000	expect(vec[433] == false) catch @panic("test failure");
		4001	expect(vec[434] == false) catch @panic("test failure");
		4002	expect(vec[435] == false) catch @panic("test failure");
		4003	expect(vec[436] == true) catch @panic("test failure");
		4004	expect(vec[437] == false) catch @panic("test failure");
		4005	expect(vec[438] == true) catch @panic("test failure");
		4006	expect(vec[439] == false) catch @panic("test failure");
		4007	expect(vec[440] == false) catch @panic("test failure");
		4008	expect(vec[441] == false) catch @panic("test failure");
		4009	expect(vec[442] == false) catch @panic("test failure");
		4010	expect(vec[443] == true) catch @panic("test failure");
		4011	expect(vec[444] == false) catch @panic("test failure");
		4012	expect(vec[445] == false) catch @panic("test failure");
		4013	expect(vec[446] == true) catch @panic("test failure");
		4014	expect(vec[447] == true) catch @panic("test failure");
		4015	expect(vec[448] == true) catch @panic("test failure");
		4016	expect(vec[449] == false) catch @panic("test failure");
		4017	expect(vec[450] == true) catch @panic("test failure");
		4018	expect(vec[451] == true) catch @panic("test failure");
		4019	expect(vec[452] == false) catch @panic("test failure");
		4020	expect(vec[453] == true) catch @panic("test failure");
		4021	expect(vec[454] == false) catch @panic("test failure");
		4022	expect(vec[455] == true) catch @panic("test failure");
		4023	expect(vec[456] == false) catch @panic("test failure");
		4024	expect(vec[457] == false) catch @panic("test failure");
		4025	expect(vec[458] == false) catch @panic("test failure");
		4026	expect(vec[459] == true) catch @panic("test failure");
		4027	expect(vec[460] == false) catch @panic("test failure");
		4028	expect(vec[461] == false) catch @panic("test failure");
		4029	expect(vec[462] == false) catch @panic("test failure");
		4030	expect(vec[463] == true) catch @panic("test failure");
		4031	expect(vec[464] == true) catch @panic("test failure");
		4032	expect(vec[465] == true) catch @panic("test failure");
		4033	expect(vec[466] == true) catch @panic("test failure");
		4034	expect(vec[467] == true) catch @panic("test failure");
		4035	expect(vec[468] == false) catch @panic("test failure");
		4036	expect(vec[469] == false) catch @panic("test failure");
		4037	expect(vec[470] == false) catch @panic("test failure");
		4038	expect(vec[471] == false) catch @panic("test failure");
		4039	expect(vec[472] == false) catch @panic("test failure");
		4040	expect(vec[473] == false) catch @panic("test failure");
		4041	expect(vec[474] == true) catch @panic("test failure");
		4042	expect(vec[475] == true) catch @panic("test failure");
		4043	expect(vec[476] == true) catch @panic("test failure");
		4044	expect(vec[477] == true) catch @panic("test failure");
		4045	expect(vec[478] == true) catch @panic("test failure");
		4046	expect(vec[479] == false) catch @panic("test failure");
		4047	expect(vec[480] == true) catch @panic("test failure");
		4048	expect(vec[481] == true) catch @panic("test failure");
		4049	expect(vec[482] == false) catch @panic("test failure");
		4050	expect(vec[483] == true) catch @panic("test failure");
		4051	expect(vec[484] == false) catch @panic("test failure");
		4052	expect(vec[485] == true) catch @panic("test failure");
		4053	expect(vec[486] == false) catch @panic("test failure");
		4054	expect(vec[487] == true) catch @panic("test failure");
		4055	expect(vec[488] == false) catch @panic("test failure");
		4056	expect(vec[489] == false) catch @panic("test failure");
		4057	expect(vec[490] == false) catch @panic("test failure");
		4058	expect(vec[491] == true) catch @panic("test failure");
		4059	expect(vec[492] == false) catch @panic("test failure");
		4060	expect(vec[493] == false) catch @panic("test failure");
		4061	expect(vec[494] == false) catch @panic("test failure");
		4062	expect(vec[495] == true) catch @panic("test failure");
		4063	expect(vec[496] == true) catch @panic("test failure");
		4064	expect(vec[497] == false) catch @panic("test failure");
		4065	expect(vec[498] == false) catch @panic("test failure");
		4066	expect(vec[499] == true) catch @panic("test failure");
		4067	expect(vec[500] == false) catch @panic("test failure");
		4068	expect(vec[501] == true) catch @panic("test failure");
		4069	expect(vec[502] == false) catch @panic("test failure");
		4070	expect(vec[503] == false) catch @panic("test failure");
		4071	expect(vec[504] == false) catch @panic("test failure");
		4072	expect(vec[505] == true) catch @panic("test failure");
		4073	expect(vec[506] == true) catch @panic("test failure");
		4074	expect(vec[507] == true) catch @panic("test failure");
		4075	expect(vec[508] == true) catch @panic("test failure");
		4076	expect(vec[509] == false) catch @panic("test failure");
		4077	expect(vec[510] == false) catch @panic("test failure");
		4078	expect(vec[511] == true) catch @panic("test failure");
		4079	}
		4080
		4081	export fn zig_ret_vector_2_bool() Vector2Bool {
		4082	return .{
		4083	false,
		4084	false,
		4085	};
		4086	}
		4087
		4088	export fn zig_ret_vector_4_bool() Vector4Bool {
		4089	return .{
		4090	false,
		4091	true,
		4092	true,
		4093	true,
		4094	};
		4095	}
		4096
		4097	export fn zig_ret_vector_8_bool() Vector8Bool {
		4098	return .{
		4099	false,
		4100	false,
		4101	false,
		4102	false,
		4103	true,
		4104	false,
		4105	false,
		4106	false,
		4107	};
		4108	}
		4109
		4110	export fn zig_ret_vector_16_bool() Vector16Bool {
		4111	return .{
		4112	false,
		4113	true,
		4114	false,
		4115	false,
		4116	false,
		4117	true,
		4118	false,
		4119	false,
		4120	true,
		4121	false,
		4122	false,
		4123	false,
		4124	false,
		4125	true,
		4126	false,
		4127	false,
		4128	};
		4129	}
		4130
		4131	export fn zig_ret_vector_32_bool() Vector32Bool {
		4132	return .{
		4133	false,
		4134	true,
		4135	false,
		4136	false,
		4137	true,
		4138	false,
		4139	true,
		4140	true,
		4141	true,
		4142	true,
		4143	true,
		4144	true,
		4145	false,
		4146	false,
		4147	false,
		4148	false,
		4149	false,
		4150	false,
		4151	true,
		4152	true,
		4153	true,
		4154	false,
		4155	true,
		4156	false,
		4157	true,
		4158	false,
		4159	false,
		4160	true,
		4161	false,
		4162	false,
		4163	true,
		4164	true,
		4165	};
		4166	}
		4167
		4168	export fn zig_ret_vector_64_bool() Vector64Bool {
		4169	return .{
		4170	true,
		4171	false,
		4172	true,
		4173	false,
		4174	false,
		4175	true,
		4176	false,
		4177	true,
		4178	true,
		4179	false,
		4180	true,
		4181	false,
		4182	true,
		4183	false,
		4184	false,
		4185	true,
		4186	false,
		4187	false,
		4188	true,
		4189	true,
		4190	false,
		4191	false,
		4192	true,
		4193	false,
		4194	false,
		4195	true,
		4196	true,
		4197	true,
		4198	true,
		4199	true,
		4200	false,
		4201	false,
		4202	true,
		4203	true,
		4204	true,
		4205	true,
		4206	false,
		4207	true,
		4208	false,
		4209	true,
		4210	true,
		4211	true,
		4212	true,
		4213	true,
		4214	false,
		4215	false,
		4216	false,
		4217	true,
		4218	true,
		4219	true,
		4220	false,
		4221	true,
		4222	true,
		4223	true,
		4224	false,
		4225	false,
		4226	false,
		4227	true,
		4228	false,
		4229	false,
		4230	true,
		4231	false,
		4232	true,
		4233	false,
		4234	};
		4235	}
		4236
		4237	export fn zig_ret_vector_128_bool() Vector128Bool {
		4238	return .{
		4239	true,
		4240	true,
		4241	false,
		4242	false,
		4243	false,
		4244	true,
		4245	true,
		4246	false,
		4247	false,
		4248	true,
		4249	false,
		4250	false,
		4251	false,
		4252	true,
		4253	false,
		4254	true,
		4255	true,
		4256	false,
		4257	false,
		4258	true,
		4259	true,
		4260	true,
		4261	true,
		4262	true,
		4263	false,
		4264	false,
		4265	true,
		4266	true,
		4267	true,
		4268	false,
		4269	false,
		4270	true,
		4271	true,
		4272	false,
		4273	true,
		4274	true,
		4275	true,
		4276	false,
		4277	true,
		4278	true,
		4279	true,
		4280	false,
		4281	true,
		4282	true,
		4283	false,
		4284	false,
		4285	false,
		4286	true,
		4287	false,
		4288	false,
		4289	false,
		4290	false,
		4291	true,
		4292	false,
		4293	true,
		4294	false,
		4295	true,
		4296	false,
		4297	false,
		4298	true,
		4299	true,
		4300	true,
		4301	true,
		4302	true,
		4303	false,
		4304	false,
		4305	false,
		4306	true,
		4307	true,
		4308	false,
		4309	true,
		4310	true,
		4311	false,
		4312	true,
		4313	true,
		4314	false,
		4315	false,
		4316	true,
		4317	false,
		4318	true,
		4319	false,
		4320	false,
		4321	true,
		4322	true,
		4323	false,
		4324	true,
		4325	false,
		4326	false,
		4327	true,
		4328	true,
		4329	true,
		4330	true,
		4331	true,
		4332	false,
		4333	false,
		4334	true,
		4335	false,
		4336	false,
		4337	true,
		4338	true,
		4339	true,
		4340	true,
		4341	true,
		4342	true,
		4343	true,
		4344	false,
		4345	false,
		4346	true,
		4347	false,
		4348	false,
		4349	true,
		4350	false,
		4351	false,
		4352	true,
		4353	false,
		4354	false,
		4355	false,
		4356	false,
		4357	false,
		4358	false,
		4359	true,
		4360	true,
		4361	true,
		4362	false,
		4363	true,
		4364	false,
		4365	false,
		4366	true,
		4367	};
		4368	}
		4369
		4370	export fn zig_ret_vector_256_bool() Vector256Bool {
		4371	return .{
		4372	true,
		4373	true,
		4374	true,
		4375	false,
		4376	true,
		4377	false,
		4378	false,
		4379	true,
		4380	false,
		4381	false,
		4382	false,
		4383	false,
		4384	false,
		4385	false,
		4386	false,
		4387	false,
		4388	true,
		4389	false,
		4390	true,
		4391	false,
		4392	false,
		4393	true,
		4394	true,
		4395	false,
		4396	false,
		4397	true,
		4398	true,
		4399	false,
		4400	true,
		4401	true,
		4402	true,
		4403	false,
		4404	true,
		4405	false,
		4406	true,
		4407	false,
		4408	true,
		4409	false,
		4410	true,
		4411	false,
		4412	false,
		4413	false,
		4414	true,
		4415	true,
		4416	true,
		4417	false,
		4418	false,
		4419	false,
		4420	true,
		4421	false,
		4422	true,
		4423	false,
		4424	true,
		4425	false,
		4426	true,
		4427	true,
		4428	false,
		4429	false,
		4430	false,
		4431	true,
		4432	true,
		4433	true,
		4434	false,
		4435	true,
		4436	false,
		4437	true,
		4438	false,
		4439	true,
		4440	true,
		4441	false,
		4442	true,
		4443	false,
		4444	true,
		4445	true,
		4446	false,
		4447	false,
		4448	false,
		4449	false,
		4450	false,
		4451	false,
		4452	false,
		4453	false,
		4454	false,
		4455	true,
		4456	false,
		4457	false,
		4458	false,
		4459	true,
		4460	false,
		4461	true,
		4462	true,
		4463	false,
		4464	false,
		4465	true,
		4466	true,
		4467	false,
		4468	false,
		4469	true,
		4470	false,
		4471	false,
		4472	false,
		4473	false,
		4474	false,
		4475	false,
		4476	false,
		4477	true,
		4478	true,
		4479	false,
		4480	true,
		4481	false,
		4482	true,
		4483	true,
		4484	false,
		4485	false,
		4486	false,
		4487	false,
		4488	false,
		4489	false,
		4490	false,
		4491	true,
		4492	true,
		4493	true,
		4494	false,
		4495	true,
		4496	true,
		4497	false,
		4498	false,
		4499	true,
		4500	true,
		4501	true,
		4502	true,
		4503	true,
		4504	false,
		4505	true,
		4506	true,
		4507	false,
		4508	false,
		4509	true,
		4510	true,
		4511	false,
		4512	true,
		4513	false,
		4514	true,
		4515	false,
		4516	true,
		4517	true,
		4518	true,
		4519	true,
		4520	false,
		4521	false,
		4522	false,
		4523	true,
		4524	false,
		4525	true,
		4526	false,
		4527	true,
		4528	true,
		4529	false,
		4530	true,
		4531	true,
		4532	true,
		4533	true,
		4534	true,
		4535	false,
		4536	false,
		4537	true,
		4538	false,
		4539	true,
		4540	true,
		4541	true,
		4542	true,
		4543	false,
		4544	true,
		4545	true,
		4546	true,
		4547	true,
		4548	true,
		4549	true,
		4550	true,
		4551	false,
		4552	true,
		4553	false,
		4554	false,
		4555	false,
		4556	true,
		4557	false,
		4558	true,
		4559	true,
		4560	false,
		4561	true,
		4562	false,
		4563	true,
		4564	false,
		4565	true,
		4566	false,
		4567	false,
		4568	true,
		4569	true,
		4570	true,
		4571	true,
		4572	true,
		4573	true,
		4574	true,
		4575	false,
		4576	true,
		4577	false,
		4578	false,
		4579	true,
		4580	true,
		4581	false,
		4582	false,
		4583	false,
		4584	true,
		4585	true,
		4586	true,
		4587	false,
		4588	false,
		4589	true,
		4590	true,
		4591	true,
		4592	true,
		4593	false,
		4594	true,
		4595	false,
		4596	true,
		4597	true,
		4598	true,
		4599	false,
		4600	false,
		4601	false,
		4602	false,
		4603	false,
		4604	true,
		4605	true,
		4606	false,
		4607	false,
		4608	false,
		4609	true,
		4610	true,
		4611	false,
		4612	true,
		4613	true,
		4614	true,
		4615	false,
		4616	true,
		4617	true,
		4618	false,
		4619	true,
		4620	false,
		4621	false,
		4622	true,
		4623	true,
		4624	false,
		4625	true,
		4626	false,
		4627	true,
		4628	};
		4629	}
		4630
		4631	export fn zig_ret_vector_512_bool() Vector512Bool {
		4632	return .{
		4633	true,
		4634	true,
		4635	true,
		4636	true,
		4637	false,
		4638	true,
		4639	false,
		4640	true,
		4641	true,
		4642	true,
		4643	false,
		4644	true,
		4645	false,
		4646	false,
		4647	false,
		4648	true,
		4649	true,
		4650	false,
		4651	false,
		4652	false,
		4653	true,
		4654	true,
		4655	false,
		4656	false,
		4657	false,
		4658	false,
		4659	true,
		4660	false,
		4661	false,
		4662	false,
		4663	true,
		4664	true,
		4665	true,
		4666	true,
		4667	false,
		4668	false,
		4669	false,
		4670	true,
		4671	true,
		4672	true,
		4673	false,
		4674	false,
		4675	true,
		4676	false,
		4677	false,
		4678	true,
		4679	false,
		4680	false,
		4681	true,
		4682	true,
		4683	true,
		4684	true,
		4685	false,
		4686	false,
		4687	false,
		4688	true,
		4689	false,
		4690	true,
		4691	false,
		4692	true,
		4693	true,
		4694	false,
		4695	false,
		4696	true,
		4697	true,
		4698	false,
		4699	true,
		4700	false,
		4701	false,
		4702	false,
		4703	true,
		4704	true,
		4705	true,
		4706	true,
		4707	true,
		4708	false,
		4709	true,
		4710	false,
		4711	true,
		4712	true,
		4713	true,
		4714	true,
		4715	true,
		4716	false,
		4717	true,
		4718	true,
		4719	false,
		4720	true,
		4721	false,
		4722	false,
		4723	true,
		4724	false,
		4725	true,
		4726	false,
		4727	false,
		4728	false,
		4729	true,
		4730	true,
		4731	false,
		4732	true,
		4733	true,
		4734	false,
		4735	true,
		4736	false,
		4737	true,
		4738	false,
		4739	true,
		4740	false,
		4741	false,
		4742	true,
		4743	false,
		4744	false,
		4745	true,
		4746	false,
		4747	true,
		4748	false,
		4749	true,
		4750	false,
		4751	false,
		4752	true,
		4753	true,
		4754	true,
		4755	false,
		4756	true,
		4757	false,
		4758	false,
		4759	true,
		4760	true,
		4761	false,
		4762	true,
		4763	true,
		4764	false,
		4765	true,
		4766	true,
		4767	false,
		4768	true,
		4769	true,
		4770	false,
		4771	false,
		4772	false,
		4773	true,
		4774	false,
		4775	true,
		4776	false,
		4777	false,
		4778	false,
		4779	true,
		4780	false,
		4781	true,
		4782	false,
		4783	false,
		4784	true,
		4785	false,
		4786	true,
		4787	true,
		4788	false,
		4789	true,
		4790	true,
		4791	false,
		4792	true,
		4793	true,
		4794	false,
		4795	false,
		4796	false,
		4797	true,
		4798	false,
		4799	true,
		4800	true,
		4801	true,
		4802	true,
		4803	false,
		4804	true,
		4805	false,
		4806	false,
		4807	true,
		4808	true,
		4809	true,
		4810	false,
		4811	false,
		4812	false,
		4813	true,
		4814	false,
		4815	false,
		4816	true,
		4817	true,
		4818	false,
		4819	true,
		4820	false,
		4821	true,
		4822	true,
		4823	true,
		4824	true,
		4825	true,
		4826	true,
		4827	true,
		4828	false,
		4829	false,
		4830	false,
		4831	false,
		4832	false,
		4833	true,
		4834	false,
		4835	true,
		4836	false,
		4837	true,
		4838	true,
		4839	false,
		4840	false,
		4841	false,
		4842	true,
		4843	true,
		4844	true,
		4845	false,
		4846	false,
		4847	true,
		4848	true,
		4849	true,
		4850	false,
		4851	false,
		4852	true,
		4853	false,
		4854	true,
		4855	true,
		4856	false,
		4857	true,
		4858	false,
		4859	false,
		4860	true,
		4861	false,
		4862	false,
		4863	true,
		4864	true,
		4865	false,
		4866	true,
		4867	true,
		4868	true,
		4869	true,
		4870	true,
		4871	false,
		4872	true,
		4873	false,
		4874	false,
		4875	true,
		4876	false,
		4877	true,
		4878	false,
		4879	true,
		4880	false,
		4881	true,
		4882	true,
		4883	true,
		4884	true,
		4885	true,
		4886	false,
		4887	false,
		4888	false,
		4889	false,
		4890	false,
		4891	false,
		4892	true,
		4893	true,
		4894	true,
		4895	true,
		4896	false,
		4897	false,
		4898	false,
		4899	true,
		4900	false,
		4901	true,
		4902	false,
		4903	true,
		4904	true,
		4905	true,
		4906	true,
		4907	true,
		4908	true,
		4909	false,
		4910	false,
		4911	true,
		4912	true,
		4913	false,
		4914	false,
		4915	false,
		4916	false,
		4917	true,
		4918	true,
		4919	true,
		4920	false,
		4921	false,
		4922	false,
		4923	true,
		4924	false,
		4925	true,
		4926	true,
		4927	false,
		4928	true,
		4929	true,
		4930	true,
		4931	false,
		4932	true,
		4933	true,
		4934	false,
		4935	false,
		4936	true,
		4937	false,
		4938	false,
		4939	true,
		4940	true,
		4941	true,
		4942	true,
		4943	false,
		4944	false,
		4945	false,
		4946	false,
		4947	false,
		4948	true,
		4949	false,
		4950	false,
		4951	true,
		4952	false,
		4953	false,
		4954	true,
		4955	true,
		4956	true,
		4957	true,
		4958	false,
		4959	false,
		4960	false,
		4961	true,
		4962	true,
		4963	false,
		4964	true,
		4965	true,
		4966	false,
		4967	false,
		4968	true,
		4969	true,
		4970	false,
		4971	true,
		4972	true,
		4973	true,
		4974	false,
		4975	false,
		4976	false,
		4977	true,
		4978	true,
		4979	false,
		4980	true,
		4981	false,
		4982	true,
		4983	false,
		4984	false,
		4985	true,
		4986	false,
		4987	true,
		4988	false,
		4989	false,
		4990	false,
		4991	false,
		4992	false,
		4993	true,
		4994	true,
		4995	false,
		4996	false,
		4997	false,
		4998	false,
		4999	true,
		5000	false,
		5001	true,
		5002	false,
		5003	true,
		5004	true,
		5005	false,
		5006	true,
		5007	true,
		5008	true,
		5009	true,
		5010	true,
		5011	false,
		5012	true,
		5013	false,
		5014	true,
		5015	true,
		5016	true,
		5017	true,
		5018	true,
		5019	false,
		5020	true,
		5021	true,
		5022	false,
		5023	true,
		5024	false,
		5025	true,
		5026	false,
		5027	true,
		5028	false,
		5029	true,
		5030	false,
		5031	false,
		5032	true,
		5033	true,
		5034	true,
		5035	true,
		5036	false,
		5037	false,
		5038	true,
		5039	false,
		5040	false,
		5041	false,
		5042	true,
		5043	false,
		5044	true,
		5045	true,
		5046	false,
		5047	true,
		5048	true,
		5049	false,
		5050	true,
		5051	true,
		5052	false,
		5053	false,
		5054	true,
		5055	false,
		5056	false,
		5057	true,
		5058	false,
		5059	true,
		5060	false,
		5061	false,
		5062	true,
		5063	false,
		5064	true,
		5065	true,
		5066	false,
		5067	true,
		5068	false,
		5069	true,
		5070	false,
		5071	true,
		5072	false,
		5073	false,
		5074	true,
		5075	true,
		5076	false,
		5077	true,
		5078	true,
		5079	false,
		5080	true,
		5081	true,
		5082	false,
		5083	false,
		5084	false,
		5085	false,
		5086	false,
		5087	true,
		5088	false,
		5089	false,
		5090	true,
		5091	false,
		5092	true,
		5093	false,
		5094	false,
		5095	false,
		5096	true,
		5097	false,
		5098	true,
		5099	false,
		5100	false,
		5101	false,
		5102	false,
		5103	true,
		5104	true,
		5105	false,
		5106	true,
		5107	true,
		5108	false,
		5109	false,
		5110	true,
		5111	true,
		5112	true,
		5113	false,
		5114	false,
		5115	true,
		5116	false,
		5117	false,
		5118	false,
		5119	true,
		5120	true,
		5121	false,
		5122	false,
		5123	false,
		5124	false,
		5125	false,
		5126	true,
		5127	true,
		5128	true,
		5129	true,
		5130	false,
		5131	false,
		5132	false,
		5133	true,
		5134	false,
		5135	true,
		5136	true,
		5137	true,
		5138	true,
		5139	false,
		5140	false,
		5141	true,
		5142	true,
		5143	false,
		5144	false,
		5145	};
		5146	}
		5147	};
		5148	}
		5149	}
		5150
893	const Vector2 = extern struct { x: f32, y: f32 };	5151	const Vector2 = extern struct { x: f32, y: f32 };
894		5152
895	extern fn c_ptr_size_float_struct(Vector2) void;	5153	extern fn c_ptr_size_float_struct(Vector2) void;

...	@@ -262,7 +262,6 @@ const hexToBytes = std.fmt.hexToBytes;	...	@@ -262,7 +262,6 @@ const hexToBytes = std.fmt.hexToBytes;
262		262
263	test "AesOcb test vector 1" {	263	test "AesOcb test vector 1" {
264	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;	264	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
265	if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
266		265
267	var k: [Aes128Ocb.key_length]u8 = undefined;	266	var k: [Aes128Ocb.key_length]u8 = undefined;
268	var nonce: [Aes128Ocb.nonce_length]u8 = undefined;	267	var nonce: [Aes128Ocb.nonce_length]u8 = undefined;
...	@@ -282,7 +281,6 @@ test "AesOcb test vector 1" {	...	@@ -282,7 +281,6 @@ test "AesOcb test vector 1" {
282		281
283	test "AesOcb test vector 2" {	282	test "AesOcb test vector 2" {
284	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;	283	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
285	if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
286		284
287	var k: [Aes128Ocb.key_length]u8 = undefined;	285	var k: [Aes128Ocb.key_length]u8 = undefined;
288	var nonce: [Aes128Ocb.nonce_length]u8 = undefined;	286	var nonce: [Aes128Ocb.nonce_length]u8 = undefined;
...	@@ -304,7 +302,6 @@ test "AesOcb test vector 2" {	...	@@ -304,7 +302,6 @@ test "AesOcb test vector 2" {
304		302
305	test "AesOcb test vector 3" {	303	test "AesOcb test vector 3" {
306	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;	304	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
307	if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
308		305
309	var k: [Aes128Ocb.key_length]u8 = undefined;	306	var k: [Aes128Ocb.key_length]u8 = undefined;
310	var nonce: [Aes128Ocb.nonce_length]u8 = undefined;	307	var nonce: [Aes128Ocb.nonce_length]u8 = undefined;
...	@@ -329,7 +326,6 @@ test "AesOcb test vector 3" {	...	@@ -329,7 +326,6 @@ test "AesOcb test vector 3" {
329		326
330	test "AesOcb test vector 4" {	327	test "AesOcb test vector 4" {
331	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;	328	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
332	if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
333		329
334	var k: [Aes128Ocb.key_length]u8 = undefined;	330	var k: [Aes128Ocb.key_length]u8 = undefined;
335	var nonce: [Aes128Ocb.nonce_length]u8 = undefined;	331	var nonce: [Aes128Ocb.nonce_length]u8 = undefined;

...	@@ -918,7 +918,6 @@ test "big.int mul multi-single" {	...	@@ -918,7 +918,6 @@ test "big.int mul multi-single" {
918		918
919	test "big.int mul multi-multi" {	919	test "big.int mul multi-multi" {
920	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;	920	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
921	if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
922		921
923	var op1: u256 = 0x998888efefefefefefefef;	922	var op1: u256 = 0x998888efefefefefefefef;
924	var op2: u256 = 0x333000abababababababab;	923	var op2: u256 = 0x333000abababababababab;
...	@@ -1042,7 +1041,6 @@ test "big.int mulWrap single-single signed" {	...	@@ -1042,7 +1041,6 @@ test "big.int mulWrap single-single signed" {
1042		1041
1043	test "big.int mulWrap multi-multi unsigned" {	1042	test "big.int mulWrap multi-multi unsigned" {
1044	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;	1043	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
1045	if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1046		1044
1047	var op1: u256 = 0x998888efefefefefefefef;	1045	var op1: u256 = 0x998888efefefefefefefef;
1048	var op2: u256 = 0x333000abababababababab;	1046	var op2: u256 = 0x333000abababababababab;
...	@@ -1698,7 +1696,6 @@ test "big.int div multi-multi (2 branch)" {	...	@@ -1698,7 +1696,6 @@ test "big.int div multi-multi (2 branch)" {
1698		1696
1699	test "big.int div multi-multi (3.1/3.3 branch)" {	1697	test "big.int div multi-multi (3.1/3.3 branch)" {
1700	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;	1698	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
1701	if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1702		1699
1703	var a = try Managed.initSet(testing.allocator, 0x11111111111111111111111111111111111111111111111111111111111111);	1700	var a = try Managed.initSet(testing.allocator, 0x11111111111111111111111111111111111111111111111111111111111111);
1704	defer a.deinit();	1701	defer a.deinit();
...	@@ -2187,7 +2184,6 @@ test "big.int bitNotWrap more than two limbs" {	...	@@ -2187,7 +2184,6 @@ test "big.int bitNotWrap more than two limbs" {
2187	// This test requires int sizes greater than 128 bits.	2184	// This test requires int sizes greater than 128 bits.
2188	if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO	2185	if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
2189	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO	2186	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
2190	if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
2191	if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO	2187	if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
2192	if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO	2188	if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
2193	// LLVM: unexpected runtime library name: __umodei4	2189	// LLVM: unexpected runtime library name: __umodei4
...	@@ -2537,7 +2533,6 @@ test "big.int gcd non-one large" {	...	@@ -2537,7 +2533,6 @@ test "big.int gcd non-one large" {
2537		2533
2538	test "big.int gcd large multi-limb result" {	2534	test "big.int gcd large multi-limb result" {
2539	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;	2535	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
2540	if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
2541		2536
2542	var a = try Managed.initSet(testing.allocator, 0x12345678123456781234567812345678123456781234567812345678);	2537	var a = try Managed.initSet(testing.allocator, 0x12345678123456781234567812345678123456781234567812345678);
2543	defer a.deinit();	2538	defer a.deinit();