| ... | ... | @@ -271,11 +271,11 @@ pub const Instruction = union(enum) { |
| 271 | 271 | }, |
| 272 | 272 | format_3h: packed struct { |
| 273 | 273 | op: u2, |
| 274 | | rd: u5, |
| 275 | | op3: u6, |
| 276 | | rs1: u5, |
| 274 | fixed1: u5 = 0b00000, |
| 275 | op3: u6 = 0b101000, |
| 276 | fixed2: u5 = 0b01111, |
| 277 | 277 | i: u1 = 0b1, |
| 278 | | reserved: u6, |
| 278 | reserved: u6 = 0b000000, |
| 279 | 279 | cmask: u3, |
| 280 | 280 | mmask: u4, |
| 281 | 281 | }, |
| ... | ... | @@ -462,12 +462,47 @@ pub const Instruction = union(enum) { |
| 462 | 462 | eq_zero, |
| 463 | 463 | le_zero, |
| 464 | 464 | lt_zero, |
| 465 | | reserved, |
| 465 | reserved2, |
| 466 | 466 | ne_zero, |
| 467 | 467 | gt_zero, |
| 468 | 468 | ge_zero, |
| 469 | 469 | }; |
| 470 | 470 | |
| 471 | pub const ASI = enum(u8) { |
| 472 | asi_nucleus = 0x04, |
| 473 | asi_nucleus_little = 0x0c, |
| 474 | asi_as_if_user_primary = 0x10, |
| 475 | asi_as_if_user_secondary = 0x11, |
| 476 | asi_as_if_user_primary_little = 0x18, |
| 477 | asi_as_if_user_secondary_little = 0x19, |
| 478 | asi_primary = 0x80, |
| 479 | asi_secondary = 0x81, |
| 480 | asi_primary_nofault = 0x82, |
| 481 | asi_secondary_nofault = 0x83, |
| 482 | asi_primary_little = 0x88, |
| 483 | asi_secondary_little = 0x89, |
| 484 | asi_primary_nofault_little = 0x8a, |
| 485 | asi_secondary_nofault_little = 0x8b, |
| 486 | }; |
| 487 | |
| 488 | pub const ShiftWidth = enum(u1) { |
| 489 | Shift32, |
| 490 | Shift64, |
| 491 | }; |
| 492 | |
| 493 | pub const MemOrderingConstraint = packed struct { |
| 494 | store_store: bool = false, |
| 495 | load_store: bool = false, |
| 496 | store_load: bool = false, |
| 497 | load_load: bool = false, |
| 498 | }; |
| 499 | |
| 500 | pub const MemCompletionConstraint = packed struct { |
| 501 | sync: bool = false, |
| 502 | mem_issue: bool = false, |
| 503 | lookaside: bool = false, |
| 504 | }; |
| 505 | |
| 471 | 506 | // TODO: Need to define an enum for `cond` values |
| 472 | 507 | // This is kinda challenging since the cond values have different meanings |
| 473 | 508 | // depending on whether it's operating on integer or FP CCR. |
| ... | ... | @@ -483,9 +518,11 @@ pub const Instruction = union(enum) { |
| 483 | 518 | |
| 484 | 519 | // Discard the last two bits since those are implicitly zero. |
| 485 | 520 | const udisp = @truncate(u30, @bitCast(u32, disp) >> 2); |
| 486 | | return Instruction{ .format_1 = .{ |
| 487 | | .disp30 = udisp, |
| 488 | | } }; |
| 521 | return Instruction{ |
| 522 | .format_1 = .{ |
| 523 | .disp30 = udisp, |
| 524 | }, |
| 525 | }; |
| 489 | 526 | } |
| 490 | 527 | |
| 491 | 528 | fn format2a(rd: Register, op2: u3, imm: i22) Instruction { |
| ... | ... | @@ -558,6 +595,196 @@ pub const Instruction = union(enum) { |
| 558 | 595 | }; |
| 559 | 596 | } |
| 560 | 597 | |
| 598 | fn format3a(rd: Register, op3: u6, rs1: Register, rs2: Register) Instruction { |
| 599 | return Instruction{ |
| 600 | .format_3a = .{ |
| 601 | .rd = rd.enc(), |
| 602 | .op3 = op3, |
| 603 | .rs1 = rs1.enc(), |
| 604 | .rs2 = rs2.enc(), |
| 605 | }, |
| 606 | }; |
| 607 | } |
| 608 | fn format3b(rd: Register, op3: u6, rs1: Register, imm: i13) Instruction { |
| 609 | return Instruction{ |
| 610 | .format_3b = .{ |
| 611 | .rd = rd.enc(), |
| 612 | .op3 = op3, |
| 613 | .rs1 = rs1.enc(), |
| 614 | .simm13 = @bitCast(u13, imm), |
| 615 | }, |
| 616 | }; |
| 617 | } |
| 618 | fn format3c(op3: u6, rs1: Register, rs2: Register) Instruction { |
| 619 | return Instruction{ |
| 620 | .format_3c = .{ |
| 621 | .op3 = op3, |
| 622 | .rs1 = rs1.enc(), |
| 623 | .rs2 = rs2.enc(), |
| 624 | }, |
| 625 | }; |
| 626 | } |
| 627 | fn format3d(op3: u6, rs1: Register, imm: i13) Instruction { |
| 628 | return Instruction{ |
| 629 | .format_3d = .{ |
| 630 | .op3 = op3, |
| 631 | .rs1 = rs1.enc(), |
| 632 | .simm13 = @bitCast(u13, imm), |
| 633 | }, |
| 634 | }; |
| 635 | } |
| 636 | fn format3e(rd: Register, op3: u6, rcond: RCondition, rs1: Register, rs2: Register) Instruction { |
| 637 | return Instruction{ |
| 638 | .format_3e = .{ |
| 639 | .rd = rd.enc(), |
| 640 | .op3 = op3, |
| 641 | .rs1 = rs1.enc(), |
| 642 | .rcond = @enumToInt(rcond), |
| 643 | .rs2 = rs2.enc(), |
| 644 | }, |
| 645 | }; |
| 646 | } |
| 647 | fn format3f(rd: Register, op3: u6, rs1: Register, rcond: RCondition, imm: i10) Instruction { |
| 648 | return Instruction{ |
| 649 | .format_3f = .{ |
| 650 | .rd = rd.enc(), |
| 651 | .op3 = op3, |
| 652 | .rs1 = rs1.enc(), |
| 653 | .rcond = @enumToInt(rcond), |
| 654 | .simm10 = @bitCast(u10, imm), |
| 655 | }, |
| 656 | }; |
| 657 | } |
| 658 | fn format3g(rd: Register, op3: u6, rs1: Register, rs2: Register) Instruction { |
| 659 | return Instruction{ |
| 660 | .format_3g = .{ |
| 661 | .rd = rd.enc(), |
| 662 | .op3 = op3, |
| 663 | .rs1 = rs1.enc(), |
| 664 | .rs2 = rs2.enc(), |
| 665 | }, |
| 666 | }; |
| 667 | } |
| 668 | fn format3h(cmask: MemCompletionConstraint, mmask: MemOrderingConstraint) Instruction { |
| 669 | return Instruction{ |
| 670 | .format_3h = .{ |
| 671 | .cmask = @bitCast(u3, cmask), |
| 672 | .mmask = @bitCast(u4, mmask), |
| 673 | }, |
| 674 | }; |
| 675 | } |
| 676 | fn format3i(rd: Register, op3: u6, rs1: Register, rs2: Register, asi: ASI) Instruction { |
| 677 | return Instruction{ |
| 678 | .format_3i = .{ |
| 679 | .rd = rd.enc(), |
| 680 | .op3 = op3, |
| 681 | .rs1 = rs1.enc(), |
| 682 | .imm_asi = @enumToInt(asi), |
| 683 | .rs2 = rs2.enc(), |
| 684 | }, |
| 685 | }; |
| 686 | } |
| 687 | fn format3j(op3: u6, impl_dep1: u5, impl_dep2: u19) Instruction { |
| 688 | return Instruction{ |
| 689 | .format_3j = .{ |
| 690 | .impl_dep1 = impl_dep1, |
| 691 | .op3 = op3, |
| 692 | .impl_dep2 = impl_dep2, |
| 693 | }, |
| 694 | }; |
| 695 | } |
| 696 | fn format3k(rd: Register, op3: u6, rs1: Register, rs2: Register, sw: ShiftWidth) Instruction { |
| 697 | return Instruction{ |
| 698 | .format_3k = .{ |
| 699 | .rd = rd.enc(), |
| 700 | .op3 = op3, |
| 701 | .rs1 = rs1.enc(), |
| 702 | .x = @enumToInt(sw), |
| 703 | .rs2 = rs2.enc(), |
| 704 | }, |
| 705 | }; |
| 706 | } |
| 707 | fn format3l(rd: Register, op3: u6, rs1: Register, shift_count: u5) Instruction { |
| 708 | return Instruction{ |
| 709 | .format_3l = .{ |
| 710 | .rd = rd.enc(), |
| 711 | .op3 = op3, |
| 712 | .rs1 = rs1.enc(), |
| 713 | .shift_count = shift_count, |
| 714 | }, |
| 715 | }; |
| 716 | } |
| 717 | fn format3m(rd: Register, op3: u6, rs1: Register, shift_count: u6) Instruction { |
| 718 | return Instruction{ |
| 719 | .format_3m = .{ |
| 720 | .rd = rd.enc(), |
| 721 | .op3 = op3, |
| 722 | .rs1 = rs1.enc(), |
| 723 | .shift_count = shift_count, |
| 724 | }, |
| 725 | }; |
| 726 | } |
| 727 | fn format3n(rd: Register, op3: u6, opf: u9, rs2: Register) Instruction { |
| 728 | return Instruction{ |
| 729 | .format_3n = .{ |
| 730 | .rd = rd.enc(), |
| 731 | .op3 = op3, |
| 732 | .opf = opf, |
| 733 | .rs2 = rs2.enc(), |
| 734 | }, |
| 735 | }; |
| 736 | } |
| 737 | fn format3o(cc: CCR, op3: u6, rs1: Register, opf: u9, rs2: Register) Instruction { |
| 738 | const ccr_cc1 = @truncate(u1, @enumToInt(cc) >> 1); |
| 739 | const ccr_cc0 = @truncate(u1, @enumToInt(cc)); |
| 740 | return Instruction{ |
| 741 | .format_3o = .{ |
| 742 | .cc1 = ccr_cc1, |
| 743 | .cc0 = ccr_cc0, |
| 744 | .op3 = op3, |
| 745 | .rs1 = rs1.enc(), |
| 746 | .opf = opf, |
| 747 | .rs2 = rs2.enc(), |
| 748 | }, |
| 749 | }; |
| 750 | } |
| 751 | fn format3p(rd: Register, op3: u6, rs1: Register, opf: u9, rs2: Register) Instruction { |
| 752 | return Instruction{ |
| 753 | .format_3p = .{ |
| 754 | .rd = rd.enc(), |
| 755 | .op3 = op3, |
| 756 | .rs1 = rs1.enc(), |
| 757 | .opf = opf, |
| 758 | .rs2 = rs2.enc(), |
| 759 | }, |
| 760 | }; |
| 761 | } |
| 762 | fn format3q(rd: Register, op3: u6, rs1: Register) Instruction { |
| 763 | return Instruction{ |
| 764 | .format_3q = .{ |
| 765 | .rd = rd.enc(), |
| 766 | .op3 = op3, |
| 767 | .rs1 = rs1.enc(), |
| 768 | }, |
| 769 | }; |
| 770 | } |
| 771 | fn format3r(fcn: u5, op3: u6) Instruction { |
| 772 | return Instruction{ |
| 773 | .format_3r = .{ |
| 774 | .fcn = fcn, |
| 775 | .op3 = op3, |
| 776 | }, |
| 777 | }; |
| 778 | } |
| 779 | fn format3s(rd: Register, op3: u6) Instruction { |
| 780 | return Instruction{ |
| 781 | .format_3s = .{ |
| 782 | .rd = rd.enc(), |
| 783 | .op3 = op3, |
| 784 | }, |
| 785 | }; |
| 786 | } |
| 787 | |
| 561 | 788 | fn format4a(rd: Register, op3: u6, rs1: Register, cc: CCR, rs2: Register) Instruction { |
| 562 | 789 | const ccr_cc1 = @truncate(u1, @enumToInt(cc) >> 1); |
| 563 | 790 | const ccr_cc0 = @truncate(u1, @enumToInt(cc)); |
Koakuma <koachan@protonmail.com> 2022-03-14 21:56:15+07:00
src