authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-08-05 13:24:32+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-08-05 13:42:53+02:00
log184234141d97f2b24f00626a3ed82cb44f4e4235
tree259b2b3f6c7d177f3a3c4d24db3b0133be75eb01
parent143767a05bae7247733b6f03b56d603080a83df7
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

behavior: disable some failing float vector comparison tests on powerpc64

https://github.com/llvm/llvm-project/issues/214198

1 files changed, 3 insertions(+), 3 deletions(-)

test/behavior/floatop.zig+3-3
...@@ -228,7 +228,7 @@ test "vector cmp f32" {...@@ -228,7 +228,7 @@ test "vector cmp f32" {
228 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO228 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
229 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;229 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
230 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.isArm()) return error.SkipZigTest;230 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.isArm()) return error.SkipZigTest;
231 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;231 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; // https://github.com/llvm/llvm-project/issues/214198
232 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;232 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;
233233
234 try testCmpVector(f32);234 try testCmpVector(f32);
...@@ -250,7 +250,7 @@ test "vector cmp f128" {...@@ -250,7 +250,7 @@ test "vector cmp f128" {
250 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO250 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
251 if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest;251 if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest;
252 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;252 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
253 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .powerpc64le) return error.SkipZigTest;253 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; // https://github.com/llvm/llvm-project/issues/214198
254 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;254 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;
255255
256 try testCmpVector(f128);256 try testCmpVector(f128);
...@@ -260,7 +260,7 @@ test "vector cmp f128" {...@@ -260,7 +260,7 @@ test "vector cmp f128" {
260test "vector cmp f80/c_longdouble" {260test "vector cmp f80/c_longdouble" {
261 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;261 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
262 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;262 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;
263 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .powerpc64le) return error.SkipZigTest;263 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; // https://github.com/llvm/llvm-project/issues/214198
264 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;264 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
265 if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest;265 if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest;
266266