Commit 1df79ab895a5740611b57fb091d0487ec21a762d | zig

lib/compiler/aro/aro/target.zig-3

...	...	@@ -486,7 +486,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
486	486	.kalimba,
487	487	.lanai,
488	488	.wasm32,
489		.spirv,
490	489	.spirv32,
491	490	.loongarch32,
492	491	.xtensa,
...	...	@@ -554,7 +553,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
554	553	.powerpcle => copy.cpu.arch = .powerpc64le,
555	554	.riscv32 => copy.cpu.arch = .riscv64,
556	555	.sparc => copy.cpu.arch = .sparc64,
557		.spirv => copy.cpu.arch = .spirv64,
558	556	.spirv32 => copy.cpu.arch = .spirv64,
559	557	.thumb => copy.cpu.arch = .aarch64,
560	558	.thumbeb => copy.cpu.arch = .aarch64_be,
...	...	@@ -609,7 +607,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
609	607	.xtensa => "xtensa",
610	608	.nvptx => "nvptx",
611	609	.nvptx64 => "nvptx64",
612		.spirv => "spirv",
613	610	.spirv32 => "spirv32",
614	611	.spirv64 => "spirv64",
615	612	.kalimba => "kalimba",

lib/compiler_rt/common.zig-1

...	...	@@ -120,7 +120,6 @@ pub fn F16T(comptime OtherType: type) type {
120	120	.nvptx64,
121	121	.riscv32,
122	122	.riscv64,
123		.spirv,
124	123	.spirv32,
125	124	.spirv64,
126	125	=> f16,

lib/std/Target.zig+5-13

...	...	@@ -1066,7 +1066,7 @@ pub const ObjectFormat = enum {
1066	1066	.uefi, .windows => .coff,
1067	1067	.zos => .goff,
1068	1068	else => switch (arch) {
1069		.spirv, .spirv32, .spirv64 => .spirv,
	1069	.spirv32, .spirv64 => .spirv,
1070	1070	.wasm32, .wasm64 => .wasm,
1071	1071	else => .elf,
1072	1072	},
...	...	@@ -1106,7 +1106,6 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
1106	1106
1107	1107	.nvptx,
1108	1108	.nvptx64,
1109		.spirv,
1110	1109	.spirv32,
1111	1110	.spirv64,
1112	1111	.wasm32,
...	...	@@ -1155,7 +1154,6 @@ pub fn toCoffMachine(target: *const Target) std.coff.MachineType {
1155	1154	.s390x,
1156	1155	.sparc,
1157	1156	.sparc64,
1158		.spirv,
1159	1157	.spirv32,
1160	1158	.spirv64,
1161	1159	.ve,
...	...	@@ -1368,7 +1366,6 @@ pub const Cpu = struct {
1368	1366	s390x,
1369	1367	sparc,
1370	1368	sparc64,
1371		spirv,
1372	1369	spirv32,
1373	1370	spirv64,
1374	1371	ve,
...	...	@@ -1454,7 +1451,7 @@ pub const Cpu = struct {
1454	1451	.riscv32, .riscv64 => .riscv,
1455	1452	.s390x => .s390x,
1456	1453	.sparc, .sparc64 => .sparc,
1457		.spirv, .spirv32, .spirv64 => .spirv,
	1454	.spirv32, .spirv64 => .spirv,
1458	1455	.ve => .ve,
1459	1456	.wasm32, .wasm64 => .wasm,
1460	1457	.x86, .x86_64 => .x86,
...	...	@@ -1558,7 +1555,7 @@ pub const Cpu = struct {
1558	1555
1559	1556	pub inline fn isSpirV(arch: Arch) bool {
1560	1557	return switch (arch) {
1561		.spirv, .spirv32, .spirv64 => true,
	1558	.spirv32, .spirv64 => true,
1562	1559	else => false,
1563	1560	};
1564	1561	}
...	...	@@ -1614,7 +1611,6 @@ pub const Cpu = struct {
1614	1611	.thumb,
1615	1612	.ve,
1616	1613	// GPU bitness is opaque. For now, assume little endian.
1617		.spirv,
1618	1614	.spirv32,
1619	1615	.spirv64,
1620	1616	.loongarch32,
...	...	@@ -1843,7 +1839,7 @@ pub const Cpu = struct {
1843	1839	.spirv_kernel,
1844	1840	.spirv_fragment,
1845	1841	.spirv_vertex,
1846		=> &.{ .spirv, .spirv32, .spirv64 },
	1842	=> &.{ .spirv32, .spirv64 },
1847	1843	};
1848	1844	}
1849	1845	};
...	...	@@ -2638,7 +2634,6 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
2638	2634	.sparc64,
2639	2635	.s390x,
2640	2636	.ve,
2641		.spirv,
2642	2637	.spirv64,
2643	2638	.loongarch64,
2644	2639	=> 64,
...	...	@@ -3157,7 +3152,6 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
3157	3152	.riscv32,
3158	3153	.riscv64,
3159	3154	.sparc64,
3160		.spirv,
3161	3155	.spirv32,
3162	3156	.spirv64,
3163	3157	.x86_64,
...	...	@@ -3250,7 +3244,6 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
3250	3244	.riscv32,
3251	3245	.riscv64,
3252	3246	.sparc64,
3253		.spirv,
3254	3247	.spirv32,
3255	3248	.spirv64,
3256	3249	.x86_64,
...	...	@@ -3319,7 +3312,6 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
3319	3312	.loongarch32,
3320	3313	.loongarch64,
3321	3314	.m68k,
3322		.spirv,
3323	3315	.spirv32,
3324	3316	.spirv64,
3325	3317	.ve,
...	...	@@ -3389,7 +3381,7 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
3389	3381	.xtensa => .{ .xtensa_call0 = .{} },
3390	3382	.amdgcn => .{ .amdgcn_device = .{} },
3391	3383	.nvptx, .nvptx64 => .nvptx_device,
3392		.spirv, .spirv32, .spirv64 => .spirv_device,
	3384	.spirv32, .spirv64 => .spirv_device,
3393	3385	};
3394	3386	}
3395	3387

lib/std/Target/spirv.zig+2-45

...	...	@@ -5,16 +5,11 @@ const CpuFeature = std.Target.Cpu.Feature;
5	5	const CpuModel = std.Target.Cpu.Model;
6	6
7	7	pub const Feature = enum {
8		addresses,
9	8	arbitrary_precision_integers,
10	9	float16,
11	10	float64,
12	11	generic_pointer,
13	12	int64,
14		kernel,
15		matrix,
16		physical_storage_buffer,
17		shader,
18	13	storage_push_constant16,
19	14	v1_0,
20	15	v1_1,
...	...	@@ -37,13 +32,6 @@ pub const all_features = blk: {
37	32	const len = @typeInfo(Feature).@"enum".fields.len;
38	33	std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
39	34	var result: [len]CpuFeature = undefined;
40		result[@intFromEnum(Feature.addresses)] = .{
41		.llvm_name = null,
42		.description = "Enable Addresses capability",
43		.dependencies = featureSet(&[_]Feature{
44		.v1_0,
45		}),
46		};
47	35	result[@intFromEnum(Feature.arbitrary_precision_integers)] = .{
48	36	.llvm_name = null,
49	37	.description = "Enable SPV_INTEL_arbitrary_precision_integers extension and the ArbitraryPrecisionIntegersINTEL capability",
...	...	@@ -69,7 +57,7 @@ pub const all_features = blk: {
69	57	.llvm_name = null,
70	58	.description = "Enable GenericPointer capability",
71	59	.dependencies = featureSet(&[_]Feature{
72		.addresses,
	60	.v1_0,
73	61	}),
74	62	};
75	63	result[@intFromEnum(Feature.int64)] = .{
...	...	@@ -79,34 +67,6 @@ pub const all_features = blk: {
79	67	.v1_0,
80	68	}),
81	69	};
82		result[@intFromEnum(Feature.kernel)] = .{
83		.llvm_name = null,
84		.description = "Enable Kernel capability",
85		.dependencies = featureSet(&[_]Feature{
86		.v1_0,
87		}),
88		};
89		result[@intFromEnum(Feature.matrix)] = .{
90		.llvm_name = null,
91		.description = "Enable Matrix capability",
92		.dependencies = featureSet(&[_]Feature{
93		.v1_0,
94		}),
95		};
96		result[@intFromEnum(Feature.physical_storage_buffer)] = .{
97		.llvm_name = null,
98		.description = "Enable SPV_KHR_variable_pointers extension and the (VariablePointers, VariablePointersStorageBuffer) capabilities",
99		.dependencies = featureSet(&[_]Feature{
100		.v1_0,
101		}),
102		};
103		result[@intFromEnum(Feature.shader)] = .{
104		.llvm_name = null,
105		.description = "Enable Shader capability",
106		.dependencies = featureSet(&[_]Feature{
107		.matrix,
108		}),
109		};
110	70	result[@intFromEnum(Feature.storage_push_constant16)] = .{
111	71	.llvm_name = null,
112	72	.description = "Enable SPV_KHR_16bit_storage extension and the StoragePushConstant16 capability",
...	...	@@ -172,7 +132,7 @@ pub const all_features = blk: {
172	132	.llvm_name = null,
173	133	.description = "Enable Vector16 capability",
174	134	.dependencies = featureSet(&[_]Feature{
175		.kernel,
	135	.v1_0,
176	136	}),
177	137	};
178	138	const ti = @typeInfo(Feature);
...	...	@@ -193,8 +153,6 @@ pub const cpu = struct {
193	153	.name = "opencl_v2",
194	154	.llvm_name = null,
195	155	.features = featureSet(&[_]Feature{
196		.generic_pointer,
197		.kernel,
198	156	.v1_2,
199	157	}),
200	158	};
...	...	@@ -202,7 +160,6 @@ pub const cpu = struct {
202	160	.name = "vulkan_v1_2",
203	161	.llvm_name = null,
204	162	.features = featureSet(&[_]Feature{
205		.shader,
206	163	.v1_5,
207	164	}),
208	165	};

lib/std/builtin.zig+1-1

...	...	@@ -189,7 +189,7 @@ pub const CallingConvention = union(enum(u8)) {
189	189	pub const kernel: CallingConvention = switch (builtin.target.cpu.arch) {
190	190	.amdgcn => .amdgcn_kernel,
191	191	.nvptx, .nvptx64 => .nvptx_kernel,
192		.spirv, .spirv32, .spirv64 => .spirv_kernel,
	192	.spirv32, .spirv64 => .spirv_kernel,
193	193	else => unreachable,
194	194	};
195	195

lib/std/debug/Dwarf/abi.zig-1

...	...	@@ -14,7 +14,6 @@ pub fn supportsUnwinding(target: *const std.Target) bool {
14	14	.amdgcn,
15	15	.nvptx,
16	16	.nvptx64,
17		.spirv,
18	17	.spirv32,
19	18	.spirv64,
20	19	=> false,

src/Sema.zig+1-1

...	...	@@ -26289,7 +26289,7 @@ fn zirWorkItem(
26289	26289
26290	26290	switch (target.cpu.arch) {
26291	26291	// TODO: Allow for other GPU targets.
26292		.amdgcn, .spirv, .spirv64, .spirv32, .nvptx, .nvptx64 => {},
	26292	.amdgcn, .spirv64, .spirv32, .nvptx, .nvptx64 => {},
26293	26293	else => {
26294	26294	return sema.fail(block, builtin_src, "builtin only available on GPU targets; targeted architecture is {s}", .{@tagName(target.cpu.arch)});
26295	26295	},

src/Zcu.zig-1

...	...	@@ -3935,7 +3935,6 @@ pub fn atomicPtrAlignment(
3935	3935	.s390x,
3936	3936	.wasm64,
3937	3937	.ve,
3938		.spirv,
3939	3938	.spirv64,
3940	3939	.loongarch64,
3941	3940	=> 64,

src/codegen.zig+1-1

...	...	@@ -37,7 +37,7 @@ fn devFeatureForBackend(backend: std.builtin.CompilerBackend) dev.Feature {
37	37	.stage2_powerpc => .powerpc_backend,
38	38	.stage2_riscv64 => .riscv64_backend,
39	39	.stage2_sparc64 => .sparc64_backend,
40		.stage2_spirv => .spirv64_backend,
	40	.stage2_spirv => .spirv_backend,
41	41	.stage2_wasm => .wasm_backend,
42	42	.stage2_x86 => .x86_backend,
43	43	.stage2_x86_64 => .x86_64_backend,

src/codegen/llvm.zig+8-8

...	...	@@ -93,8 +93,10 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8
93	93	.xtensa => "xtensa",
94	94	.nvptx => "nvptx",
95	95	.nvptx64 => "nvptx64",
96		.spirv => "spirv",
97		.spirv32 => "spirv32",
	96	.spirv32 => switch (target.os.tag) {
	97	.vulkan, .opengl => "spirv",
	98	else => "spirv32",
	99	},
98	100	.spirv64 => "spirv64",
99	101	.lanai => "lanai",
100	102	.wasm32 => "wasm32",
...	...	@@ -150,9 +152,6 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8
150	152	.powerpc => subArchName(target, .powerpc, .{
151	153	.{ .spe, "spe" },
152	154	}),
153		.spirv => subArchName(target, .spirv, .{
154		.{ .v1_5, "1.5" },
155		}),
156	155	.spirv32, .spirv64 => subArchName(target, .spirv, .{
157	156	.{ .v1_5, "1.5" },
158	157	.{ .v1_4, "1.4" },
...	...	@@ -441,8 +440,10 @@ pub fn dataLayout(target: *const std.Target) []const u8 {
441	440	else
442	441	"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128",
443	442	},
444		.spirv => "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1",
445		.spirv32 => "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1",
	443	.spirv32 => switch (target.os.tag) {
	444	.vulkan, .opengl => "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1",
	445	else => "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1",
	446	},
446	447	.spirv64 => "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1",
447	448	.wasm32 => if (target.os.tag == .emscripten)
448	449	"e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-f128:64-n32:64-S128-ni:1:10:20"
...	...	@@ -13129,7 +13130,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
13129	13130	llvm.LLVMInitializeLoongArchAsmPrinter();
13130	13131	llvm.LLVMInitializeLoongArchAsmParser();
13131	13132	},
13132		.spirv,
13133	13133	.spirv32,
13134	13134	.spirv64,
13135	13135	=> {

src/codegen/spirv.zig+92-74

...	...	@@ -439,7 +439,7 @@ const NavGen = struct {
439	439	fn importExtendedSet(self: *NavGen) !IdResult {
440	440	const target = self.spv.target;
441	441	return switch (target.os.tag) {
442		.opencl => try self.spv.importInstructionSet(.@"OpenCL.std"),
	442	.opencl, .amdhsa => try self.spv.importInstructionSet(.@"OpenCL.std"),
443	443	.vulkan, .opengl => try self.spv.importInstructionSet(.@"GLSL.std.450"),
444	444	else => unreachable,
445	445	};
...	...	@@ -561,7 +561,7 @@ const NavGen = struct {
561	561	}
562	562
563	563	fn castToGeneric(self: *NavGen, type_id: IdRef, ptr_id: IdRef) !IdRef {
564		if (self.spv.hasFeature(.kernel)) {
	564	if (self.spv.hasFeature(.generic_pointer)) {
565	565	const result_id = self.spv.allocId();
566	566	try self.func.body.emit(self.spv.gpa, .OpPtrCastToGeneric, .{
567	567	.id_result_type = type_id,
...	...	@@ -601,16 +601,18 @@ const NavGen = struct {
601	601
602	602	// We require Int8 and Int16 capabilities and benefit Int64 when available.
603	603	// 32-bit integers are always supported (see spec, 2.16.1, Data rules).
604		const ints = [_]struct { bits: u16, feature: ?Target.spirv.Feature }{
605		.{ .bits = 8, .feature = null },
606		.{ .bits = 16, .feature = null },
607		.{ .bits = 32, .feature = null },
608		.{ .bits = 64, .feature = .int64 },
	604	const ints = [_]struct { bits: u16, enabled: bool }{
	605	.{ .bits = 8, .enabled = true },
	606	.{ .bits = 16, .enabled = true },
	607	.{ .bits = 32, .enabled = true },
	608	.{
	609	.bits = 64,
	610	.enabled = self.spv.hasFeature(.int64) or self.spv.target.cpu.arch == .spirv64,
	611	},
609	612	};
610	613
611	614	for (ints) \|int\| {
612		const has_feature = if (int.feature) \|feature\| self.spv.hasFeature(feature) else true;
613		if (bits <= int.bits and has_feature) return .{ int.bits, false };
	615	if (bits <= int.bits and int.enabled) return .{ int.bits, false };
614	616	}
615	617
616	618	// Big int
...	...	@@ -624,7 +626,10 @@ const NavGen = struct {
624	626	/// is no way of knowing whether those are actually supported.
625	627	/// TODO: Maybe this should be cached?
626	628	fn largestSupportedIntBits(self: *NavGen) u16 {
627		return if (self.spv.hasFeature(.int64)) 64 else 32;
	629	if (self.spv.hasFeature(.int64) or self.spv.target.cpu.arch == .spirv64) {
	630	return 64;
	631	}
	632	return 32;
628	633	}
629	634
630	635	fn arithmeticTypeInfo(self: *NavGen, ty: Type) ArithmeticTypeInfo {
...	...	@@ -736,8 +741,8 @@ const NavGen = struct {
736	741	});
737	742	}
738	743
739		const final_value: spec.LiteralContextDependentNumber = blk: {
740		if (self.spv.hasFeature(.kernel)) {
	744	const final_value: spec.LiteralContextDependentNumber = switch (self.spv.target.os.tag) {
	745	.opencl, .amdhsa => blk: {
741	746	const value64: u64 = switch (signedness) {
742	747	.signed => @bitCast(@as(i64, @intCast(value))),
743	748	.unsigned => @as(u64, @intCast(value)),
...	...	@@ -754,13 +759,12 @@ const NavGen = struct {
754	759	33...64 => .{ .uint64 = truncated_value },
755	760	else => unreachable,
756	761	};
757		}
758
759		break :blk switch (backing_bits) {
	762	},
	763	else => switch (backing_bits) {
760	764	1...32 => if (signedness == .signed) .{ .int32 = @intCast(value) } else .{ .uint32 = @intCast(value) },
761	765	33...64 => if (signedness == .signed) .{ .int64 = value } else .{ .uint64 = value },
762	766	else => unreachable,
763		};
	767	},
764	768	};
765	769
766	770	const result_id = try self.spv.constant(result_ty_id, final_value);
...	...	@@ -1276,12 +1280,11 @@ const NavGen = struct {
1276	1280	return self.arrayType(backing_bits / big_int_bits, int_ty);
1277	1281	}
1278	1282
1279		// Kernel only supports unsigned ints.
1280		if (self.spv.hasFeature(.kernel)) {
1281		return self.spv.intType(.unsigned, backing_bits);
1282		}
1283
1284		return self.spv.intType(signedness, backing_bits);
	1283	return switch (self.spv.target.os.tag) {
	1284	// Kernel only supports unsigned ints.
	1285	.opencl, .amdhsa => return self.spv.intType(.unsigned, backing_bits),
	1286	else => self.spv.intType(signedness, backing_bits),
	1287	};
1285	1288	}
1286	1289
1287	1290	fn arrayType(self: *NavGen, len: u32, child_ty: IdRef) !IdRef {
...	...	@@ -1314,20 +1317,23 @@ const NavGen = struct {
1314	1317
1315	1318	const child_ty_id = try self.resolveType(child_ty, child_repr);
1316	1319
1317		if (self.spv.hasFeature(.shader)) {
1318		if (child_ty.zigTypeTag(zcu) == .@"struct") {
1319		switch (storage_class) {
1320		.Uniform, .PushConstant => try self.spv.decorate(child_ty_id, .Block),
1321		else => {},
	1320	switch (self.spv.target.os.tag) {
	1321	.vulkan, .opengl => {
	1322	if (child_ty.zigTypeTag(zcu) == .@"struct") {
	1323	switch (storage_class) {
	1324	.Uniform, .PushConstant => try self.spv.decorate(child_ty_id, .Block),
	1325	else => {},
	1326	}
1322	1327	}
1323		}
1324	1328
1325		switch (ip.indexToKey(child_ty.toIntern())) {
1326		.func_type, .opaque_type => {},
1327		else => {
1328		try self.spv.decorate(result_id, .{ .ArrayStride = .{ .array_stride = @intCast(child_ty.abiSize(zcu)) } });
1329		},
1330		}
	1329	switch (ip.indexToKey(child_ty.toIntern())) {
	1330	.func_type, .opaque_type => {},
	1331	else => {
	1332	try self.spv.decorate(result_id, .{ .ArrayStride = .{ .array_stride = @intCast(child_ty.abiSize(zcu)) } });
	1333	},
	1334	}
	1335	},
	1336	else => {},
1331	1337	}
1332	1338
1333	1339	try self.spv.sections.types_globals_constants.emit(self.spv.gpa, .OpTypePointer, .{
...	...	@@ -1554,10 +1560,13 @@ const NavGen = struct {
1554	1560	return try self.arrayType(1, elem_ty_id);
1555	1561	} else {
1556	1562	const result_id = try self.arrayType(total_len, elem_ty_id);
1557		if (self.spv.hasFeature(.shader)) {
1558		try self.spv.decorate(result_id, .{ .ArrayStride = .{
1559		.array_stride = @intCast(elem_ty.abiSize(zcu)),
1560		} });
	1563	switch (self.spv.target.os.tag) {
	1564	.vulkan, .opengl => {
	1565	try self.spv.decorate(result_id, .{ .ArrayStride = .{
	1566	.array_stride = @intCast(elem_ty.abiSize(zcu)),
	1567	} });
	1568	},
	1569	else => {},
1561	1570	}
1562	1571	return result_id;
1563	1572	}
...	...	@@ -1688,11 +1697,15 @@ const NavGen = struct {
1688	1697	continue;
1689	1698	}
1690	1699
1691		if (self.spv.hasFeature(.shader)) {
1692		try self.spv.decorateMember(result_id, index, .{ .Offset = .{
1693		.byte_offset = @intCast(ty.structFieldOffset(field_index, zcu)),
1694		} });
	1700	switch (self.spv.target.os.tag) {
	1701	.vulkan, .opengl => {
	1702	try self.spv.decorateMember(result_id, index, .{ .Offset = .{
	1703	.byte_offset = @intCast(ty.structFieldOffset(field_index, zcu)),
	1704	} });
	1705	},
	1706	else => {},
1695	1707	}
	1708
1696	1709	const field_name = struct_type.fieldName(ip, field_index).unwrap() orelse
1697	1710	try ip.getOrPutStringFmt(zcu.gpa, pt.tid, "{d}", .{field_index}, .no_embedded_nulls);
1698	1711	try member_types.append(try self.resolveType(field_ty, .indirect));
...	...	@@ -1795,28 +1808,23 @@ const NavGen = struct {
1795	1808	fn spvStorageClass(self: *NavGen, as: std.builtin.AddressSpace) StorageClass {
1796	1809	return switch (as) {
1797	1810	.generic => if (self.spv.hasFeature(.generic_pointer)) .Generic else .Function,
1798		.global => {
1799		if (self.spv.hasFeature(.kernel)) return .CrossWorkgroup;
1800		return .StorageBuffer;
	1811	.global => switch (self.spv.target.os.tag) {
	1812	.opencl, .amdhsa => .CrossWorkgroup,
	1813	else => .StorageBuffer,
1801	1814	},
1802	1815	.push_constant => {
1803		assert(self.spv.hasFeature(.shader));
1804	1816	return .PushConstant;
1805	1817	},
1806	1818	.output => {
1807		assert(self.spv.hasFeature(.shader));
1808	1819	return .Output;
1809	1820	},
1810	1821	.uniform => {
1811		assert(self.spv.hasFeature(.shader));
1812	1822	return .Uniform;
1813	1823	},
1814	1824	.storage_buffer => {
1815		assert(self.spv.hasFeature(.shader));
1816	1825	return .StorageBuffer;
1817	1826	},
1818	1827	.physical_storage_buffer => {
1819		assert(self.spv.hasFeature(.physical_storage_buffer));
1820	1828	return .PhysicalStorageBuffer;
1821	1829	},
1822	1830	.constant => .UniformConstant,
...	...	@@ -2768,7 +2776,7 @@ const NavGen = struct {
2768	2776
2769	2777	const p_error_id = self.spv.allocId();
2770	2778	switch (target.os.tag) {
2771		.opencl => {
	2779	.opencl, .amdhsa => {
2772	2780	const kernel_proto_ty_id = try self.functionType(Type.void, &.{ptr_anyerror_ty});
2773	2781
2774	2782	try section.emit(self.spv.gpa, .OpFunction, .{
...	...	@@ -2876,7 +2884,7 @@ const NavGen = struct {
2876	2884
2877	2885	const execution_mode: spec.ExecutionModel = switch (target.os.tag) {
2878	2886	.vulkan, .opengl => .GLCompute,
2879		.opencl => .Kernel,
	2887	.opencl, .amdhsa => .Kernel,
2880	2888	else => unreachable,
2881	2889	};
2882	2890
...	...	@@ -3630,8 +3638,13 @@ const NavGen = struct {
3630	3638	.integer, .strange_integer => {
3631	3639	const abs_value = try self.buildUnary(.i_abs, value);
3632	3640
3633		if (value.ty.intInfo(zcu).signedness == .signed and self.spv.hasFeature(.shader)) {
3634		return self.todo("perform bitcast after @abs", .{});
	3641	switch (self.spv.target.os.tag) {
	3642	.vulkan, .opengl => {
	3643	if (value.ty.intInfo(zcu).signedness == .signed) {
	3644	return self.todo("perform bitcast after @abs", .{});
	3645	}
	3646	},
	3647	else => {},
3635	3648	}
3636	3649
3637	3650	return try self.normalize(abs_value, self.arithmeticTypeInfo(result_ty));
...	...	@@ -4156,22 +4169,25 @@ const NavGen = struct {
4156	4169	defer self.gpa.free(ids);
4157	4170
4158	4171	const result_id = self.spv.allocId();
4159		if (self.spv.hasFeature(.addresses)) {
4160		try self.func.body.emit(self.spv.gpa, .OpInBoundsPtrAccessChain, .{
4161		.id_result_type = result_ty_id,
4162		.id_result = result_id,
4163		.base = base,
4164		.element = element,
4165		.indexes = ids,
4166		});
4167		} else {
4168		try self.func.body.emit(self.spv.gpa, .OpPtrAccessChain, .{
4169		.id_result_type = result_ty_id,
4170		.id_result = result_id,
4171		.base = base,
4172		.element = element,
4173		.indexes = ids,
4174		});
	4172	switch (self.spv.target.os.tag) {
	4173	.opencl, .amdhsa => {
	4174	try self.func.body.emit(self.spv.gpa, .OpInBoundsPtrAccessChain, .{
	4175	.id_result_type = result_ty_id,
	4176	.id_result = result_id,
	4177	.base = base,
	4178	.element = element,
	4179	.indexes = ids,
	4180	});
	4181	},
	4182	else => {
	4183	try self.func.body.emit(self.spv.gpa, .OpPtrAccessChain, .{
	4184	.id_result_type = result_ty_id,
	4185	.id_result = result_id,
	4186	.base = base,
	4187	.element = element,
	4188	.indexes = ids,
	4189	});
	4190	},
4175	4191	}
4176	4192	return result_id;
4177	4193	}
...	...	@@ -4681,9 +4697,8 @@ const NavGen = struct {
4681	4697	const field_int_ty = try self.pt.intType(.unsigned, ty_bit_size);
4682	4698	const field_int_id = blk: {
4683	4699	if (field_ty.isPtrAtRuntime(zcu)) {
4684		assert(self.spv.hasFeature(.addresses) or
4685		(self.spv.hasFeature(.physical_storage_buffer) and
4686		field_ty.ptrAddressSpace(zcu) == .storage_buffer));
	4700	assert(self.spv.target.cpu.arch == .spirv64 and
	4701	field_ty.ptrAddressSpace(zcu) == .storage_buffer);
4687	4702	break :blk try self.intFromPtr(field_id);
4688	4703	}
4689	4704	break :blk try self.bitCast(field_int_ty, field_ty, field_id);
...	...	@@ -5333,7 +5348,10 @@ const NavGen = struct {
5333	5348	.initializer = options.initializer,
5334	5349	});
5335	5350
5336		if (self.spv.hasFeature(.shader)) return var_id;
	5351	switch (self.spv.target.os.tag) {
	5352	.vulkan, .opengl => return var_id,
	5353	else => {},
	5354	}
5337	5355
5338	5356	switch (options.storage_class) {
5339	5357	.Generic => {

src/codegen/spirv/Module.zig+42-52

...	...	@@ -336,65 +336,55 @@ fn entryPoints(self: *Module) !Section {
336	336
337	337	pub fn finalize(self: *Module, a: Allocator) ![]Word {
338	338	// Emit capabilities and extensions
339		for (std.Target.spirv.all_features) \|feature\| {
340		if (self.target.cpu.features.isEnabled(feature.index)) {
341		const feature_tag: std.Target.spirv.Feature = @enumFromInt(feature.index);
342		switch (feature_tag) {
343		// Versions
344		.v1_0, .v1_1, .v1_2, .v1_3, .v1_4, .v1_5, .v1_6 => {},
345		// Features with no dependencies
346		.int64 => try self.addCapability(.Int64),
347		.float16 => try self.addCapability(.Float16),
348		.float64 => try self.addCapability(.Float64),
349		.matrix => try self.addCapability(.Matrix),
350		.storage_push_constant16 => {
351		try self.addExtension("SPV_KHR_16bit_storage");
352		try self.addCapability(.StoragePushConstant16);
353		},
354		.arbitrary_precision_integers => {
355		try self.addExtension("SPV_INTEL_arbitrary_precision_integers");
356		try self.addCapability(.ArbitraryPrecisionIntegersINTEL);
357		},
358		.addresses => try self.addCapability(.Addresses),
359		// Kernel
360		.kernel => try self.addCapability(.Kernel),
361		.generic_pointer => try self.addCapability(.GenericPointer),
362		.vector16 => try self.addCapability(.Vector16),
363		// Shader
364		.shader => try self.addCapability(.Shader),
365		.variable_pointers => {
366		try self.addExtension("SPV_KHR_variable_pointers");
367		try self.addCapability(.VariablePointersStorageBuffer);
368		try self.addCapability(.VariablePointers);
369		},
370		.physical_storage_buffer => {
371		try self.addExtension("SPV_KHR_physical_storage_buffer");
372		try self.addCapability(.PhysicalStorageBufferAddresses);
373		},
	339	switch (self.target.os.tag) {
	340	.opengl => {
	341	try self.addCapability(.Shader);
	342	try self.addCapability(.Matrix);
	343	},
	344	.vulkan => {
	345	try self.addCapability(.Shader);
	346	try self.addCapability(.Matrix);
	347	if (self.target.cpu.arch == .spirv64) {
	348	try self.addExtension("SPV_KHR_physical_storage_buffer");
	349	try self.addCapability(.PhysicalStorageBufferAddresses);
374	350	}
375		}
	351	},
	352	.opencl, .amdhsa => {
	353	try self.addCapability(.Kernel);
	354	try self.addCapability(.Addresses);
	355	},
	356	else => unreachable,
	357	}
	358	if (self.target.cpu.arch == .spirv64) try self.addCapability(.Int64);
	359	if (self.target.cpu.has(.spirv, .int64)) try self.addCapability(.Int64);
	360	if (self.target.cpu.has(.spirv, .float16)) try self.addCapability(.Float16);
	361	if (self.target.cpu.has(.spirv, .float64)) try self.addCapability(.Float64);
	362	if (self.target.cpu.has(.spirv, .generic_pointer)) try self.addCapability(.GenericPointer);
	363	if (self.target.cpu.has(.spirv, .vector16)) try self.addCapability(.Vector16);
	364	if (self.target.cpu.has(.spirv, .storage_push_constant16)) {
	365	try self.addExtension("SPV_KHR_16bit_storage");
	366	try self.addCapability(.StoragePushConstant16);
	367	}
	368	if (self.target.cpu.has(.spirv, .arbitrary_precision_integers)) {
	369	try self.addExtension("SPV_INTEL_arbitrary_precision_integers");
	370	try self.addCapability(.ArbitraryPrecisionIntegersINTEL);
	371	}
	372	if (self.target.cpu.has(.spirv, .variable_pointers)) {
	373	try self.addExtension("SPV_KHR_variable_pointers");
	374	try self.addCapability(.VariablePointersStorageBuffer);
	375	try self.addCapability(.VariablePointers);
376	376	}
377	377	// These are well supported
378	378	try self.addCapability(.Int8);
379	379	try self.addCapability(.Int16);
380	380
381	381	// Emit memory model
382		const addressing_model: spec.AddressingModel = blk: {
383		if (self.hasFeature(.shader)) {
384		if (self.hasFeature(.physical_storage_buffer)) {
385		assert(self.target.cpu.arch == .spirv64);
386		break :blk .PhysicalStorageBuffer64;
387		}
388		assert(self.target.cpu.arch == .spirv);
389		break :blk .Logical;
390		}
391
392		assert(self.hasFeature(.kernel));
393		break :blk switch (self.target.cpu.arch) {
394		.spirv32 => .Physical32,
395		.spirv64 => .Physical64,
396		else => unreachable,
397		};
	382	const addressing_model: spec.AddressingModel = switch (self.target.os.tag) {
	383	.opengl => .Logical,
	384	.vulkan => if (self.target.cpu.arch == .spirv32) .Logical else .PhysicalStorageBuffer64,
	385	.opencl => if (self.target.cpu.arch == .spirv32) .Physical32 else .Physical64,
	386	.amdhsa => .Physical64,
	387	else => unreachable,
398	388	};
399	389	try self.sections.memory_model.emit(self.gpa, .OpMemoryModel, .{
400	390	.addressing_model = addressing_model,

src/dev.zig+3-3

...	...	@@ -88,7 +88,7 @@ pub const Env = enum {
88	88	.powerpc_backend,
89	89	.riscv64_backend,
90	90	.sparc64_backend,
91		.spirv64_backend,
	91	.spirv_backend,
92	92	.lld_linker,
93	93	.coff_linker,
94	94	.elf_linker,
...	...	@@ -183,7 +183,7 @@ pub const Env = enum {
183	183	else => Env.sema.supports(feature),
184	184	},
185	185	.spirv => switch (feature) {
186		.spirv64_backend,
	186	.spirv_backend,
187	187	.spirv_linker,
188	188	=> true,
189	189	else => Env.sema.supports(feature),
...	...	@@ -258,7 +258,7 @@ pub const Feature = enum {
258	258	powerpc_backend,
259	259	riscv64_backend,
260	260	sparc64_backend,
261		spirv64_backend,
	261	spirv_backend,
262	262
263	263	lld_linker,
264	264	coff_linker,

src/link/SpirV.zig+1-1

...	...	@@ -64,7 +64,7 @@ pub fn createEmpty(
64	64	assert(!comp.config.use_llvm); // Caught by Compilation.Config.resolve
65	65	assert(target.ofmt == .spirv); // Caught by Compilation.Config.resolve
66	66	switch (target.cpu.arch) {
67		.spirv, .spirv32, .spirv64 => {},
	67	.spirv32, .spirv64 => {},
68	68	else => unreachable, // Caught by Compilation.Config.resolve.
69	69	}
70	70	switch (target.os.tag) {

src/target.zig+6-9

...	...	@@ -179,7 +179,6 @@ pub fn hasLlvmSupport(target: *const std.Target, ofmt: std.Target.ObjectFormat)
179	179	.riscv64,
180	180	.sparc,
181	181	.sparc64,
182		.spirv,
183	182	.spirv32,
184	183	.spirv64,
185	184	.s390x,
...	...	@@ -241,7 +240,7 @@ pub fn supportsStackProtector(target: *const std.Target, backend: std.builtin.Co
241	240	else => {},
242	241	}
243	242	switch (target.cpu.arch) {
244		.spirv, .spirv32, .spirv64 => return false,
	243	.spirv32, .spirv64 => return false,
245	244	else => {},
246	245	}
247	246	return switch (backend) {
...	...	@@ -252,7 +251,7 @@ pub fn supportsStackProtector(target: *const std.Target, backend: std.builtin.Co
252	251
253	252	pub fn clangSupportsStackProtector(target: *const std.Target) bool {
254	253	return switch (target.cpu.arch) {
255		.spirv, .spirv32, .spirv64 => return false,
	254	.spirv32, .spirv64 => return false,
256	255	else => true,
257	256	};
258	257	}
...	...	@@ -270,7 +269,7 @@ pub fn supportsReturnAddress(target: *const std.Target, optimize: std.builtin.Op
270	269	// overhead that we would prefer to avoid in release builds.
271	270	.wasm32, .wasm64 => target.os.tag == .emscripten and optimize == .Debug,
272	271	.bpfel, .bpfeb => false,
273		.spirv, .spirv32, .spirv64 => false,
	272	.spirv32, .spirv64 => false,
274	273	else => true,
275	274	};
276	275	}
...	...	@@ -335,7 +334,7 @@ pub fn canBuildLibCompilerRt(target: *const std.Target, use_llvm: bool, have_llv
335	334	else => {},
336	335	}
337	336	switch (target.cpu.arch) {
338		.spirv, .spirv32, .spirv64 => return false,
	337	.spirv32, .spirv64 => return false,
339	338	// Remove this once https://github.com/ziglang/zig/issues/23714 is fixed
340	339	.amdgcn => return false,
341	340	else => {},
...	...	@@ -352,7 +351,7 @@ pub fn canBuildLibCompilerRt(target: *const std.Target, use_llvm: bool, have_llv
352	351
353	352	pub fn canBuildLibUbsanRt(target: *const std.Target) bool {
354	353	switch (target.cpu.arch) {
355		.spirv, .spirv32, .spirv64 => return false,
	354	.spirv32, .spirv64 => return false,
356	355	// Remove this once https://github.com/ziglang/zig/issues/23715 is fixed
357	356	.nvptx, .nvptx64 => return false,
358	357	else => return true,
...	...	@@ -719,7 +718,6 @@ pub fn supportsFunctionAlignment(target: *const std.Target) bool {
719	718	return switch (target.cpu.arch) {
720	719	.nvptx,
721	720	.nvptx64,
722		.spirv,
723	721	.spirv32,
724	722	.spirv64,
725	723	.wasm32,
...	...	@@ -816,8 +814,7 @@ pub fn zigBackend(target: *const std.Target, use_llvm: bool) std.builtin.Compile
816	814	.powerpc, .powerpcle, .powerpc64, .powerpc64le => .stage2_powerpc,
817	815	.riscv64 => .stage2_riscv64,
818	816	.sparc64 => .stage2_sparc64,
819		.spirv32 => if (target.os.tag == .opencl) .stage2_spirv else .other,
820		.spirv, .spirv64 => .stage2_spirv,
	817	.spirv32, .spirv64 => .stage2_spirv,
821	818	.wasm32, .wasm64 => .stage2_wasm,
822	819	.x86 => .stage2_x86,
823	820	.x86_64 => .stage2_x86_64,

test/behavior/type_info.zig-1

...	...	@@ -389,7 +389,6 @@ fn testFunction() !void {
389	389
390	390	// Avoid looking at `typeInfoFooAligned` on targets which don't support function alignment.
391	391	switch (builtin.target.cpu.arch) {
392		.spirv,
393	392	.spirv32,
394	393	.spirv64,
395	394	.wasm32,

test/cases/compile_errors/function_alignment_on_unsupported_target.zig+1-1

...	...	@@ -2,6 +2,6 @@ export fn entry() align(64) void {}
2	2
3	3	// error
4	4	// backend=stage2
5		// target=nvptx-cuda,nvptx64-cuda,spirv-vulkan,spirv32-opencl,spirv64-opencl,wasm32-freestanding,wasm64-freestanding
	5	// target=nvptx-cuda,nvptx64-cuda,spirv32-opengl,spirv32-vulkan,spirv32-opencl,spirv64-opencl,spirv64-amdhsa,wasm32-freestanding,wasm64-freestanding
6	6	//
7	7	// :1:25: error: target does not support function alignment

test/tests.zig+2-2

...	...	@@ -1440,7 +1440,7 @@ const test_targets = blk: {
1440	1440	.{
1441	1441	.target = std.Target.Query.parse(.{
1442	1442	.arch_os_abi = "spirv64-vulkan",
1443		.cpu_features = "vulkan_v1_2+physical_storage_buffer+int64+float16+float64",
	1443	.cpu_features = "vulkan_v1_2+float16+float64",
1444	1444	}) catch unreachable,
1445	1445	.use_llvm = false,
1446	1446	.use_lld = false,
...	...	@@ -2527,7 +2527,7 @@ fn wouldUseLlvm(use_llvm: ?bool, query: std.Target.Query, optimize_mode: Optimiz
2527	2527	const cpu_arch = query.cpu_arch orelse builtin.cpu.arch;
2528	2528	switch (cpu_arch) {
2529	2529	.x86_64 => if (std.Target.ptrBitWidth_arch_abi(cpu_arch, query.abi orelse .none) != 64) return true,
2530		.spirv, .spirv32, .spirv64 => return false,
	2530	.spirv32, .spirv64 => return false,
2531	2531	else => return true,
2532	2532	}
2533	2533	return false;

tools/update_cpu_features.zig+4-29

...	...	@@ -1105,11 +1105,6 @@ const targets = [_]ArchTarget{
1105	1105	.desc = "Enable Float64 capability",
1106	1106	.deps = &.{"v1_0"},
1107	1107	},
1108		.{
1109		.zig_name = "matrix",
1110		.desc = "Enable Matrix capability",
1111		.deps = &.{"v1_0"},
1112		},
1113	1108	.{
1114	1109	.zig_name = "storage_push_constant16",
1115	1110	.desc = "Enable SPV_KHR_16bit_storage extension and the StoragePushConstant16 capability",
...	...	@@ -1120,52 +1115,32 @@ const targets = [_]ArchTarget{
1120	1115	.desc = "Enable SPV_INTEL_arbitrary_precision_integers extension and the ArbitraryPrecisionIntegersINTEL capability",
1121	1116	.deps = &.{"v1_5"},
1122	1117	},
1123		.{
1124		.zig_name = "kernel",
1125		.desc = "Enable Kernel capability",
1126		.deps = &.{"v1_0"},
1127		},
1128		.{
1129		.zig_name = "addresses",
1130		.desc = "Enable Addresses capability",
1131		.deps = &.{"v1_0"},
1132		},
1133	1118	.{
1134	1119	.zig_name = "generic_pointer",
1135	1120	.desc = "Enable GenericPointer capability",
1136		.deps = &.{ "v1_0", "addresses" },
	1121	.deps = &.{"v1_0"},
1137	1122	},
1138	1123	.{
1139	1124	.zig_name = "vector16",
1140	1125	.desc = "Enable Vector16 capability",
1141		.deps = &.{ "v1_0", "kernel" },
1142		},
1143		.{
1144		.zig_name = "shader",
1145		.desc = "Enable Shader capability",
1146		.deps = &.{ "v1_0", "matrix" },
	1126	.deps = &.{"v1_0"},
1147	1127	},
1148	1128	.{
1149	1129	.zig_name = "variable_pointers",
1150	1130	.desc = "Enable SPV_KHR_physical_storage_buffer extension and the PhysicalStorageBufferAddresses capability",
1151	1131	.deps = &.{"v1_0"},
1152	1132	},
1153		.{
1154		.zig_name = "physical_storage_buffer",
1155		.desc = "Enable SPV_KHR_variable_pointers extension and the (VariablePointers, VariablePointersStorageBuffer) capabilities",
1156		.deps = &.{"v1_0"},
1157		},
1158	1133	},
1159	1134	.extra_cpus = &.{
1160	1135	.{
1161	1136	.llvm_name = null,
1162	1137	.zig_name = "vulkan_v1_2",
1163		.features = &.{ "v1_5", "shader" },
	1138	.features = &.{"v1_5"},
1164	1139	},
1165	1140	.{
1166	1141	.llvm_name = null,
1167	1142	.zig_name = "opencl_v2",
1168		.features = &.{ "v1_2", "kernel", "addresses", "generic_pointer" },
	1143	.features = &.{"v1_2"},
1169	1144	},
1170	1145	},
1171	1146	},

author	Ali Chraghi <alichraghi@proton.me> 2025-06-17 09:21:33+03:30
committer	Andrew Kelley <andrew@ziglang.org> 2025-06-23 06:03:03+02:00
log	1df79ab895a5740611b57fb091d0487ec21a762d
tree	0485e74f1fa2cad32235078542e6de3c39d83329
parent	c71bb0f2b66f72122e25400c97a1213d59e4ad73

remove `spirv` cpu arch