| author | |
| committer | |
| log | 1dfdc21c31a027a34213a2e1f27433d4e609d634 |
| tree | f0f5477cad019e67ad8343372ea763239b04ad52 |
| parent | ffb63a05a3327e64bcf8ec7fd05c6aab8d304480 |
the recent merge strings PR made `got_addr` `i64` and now requires an `@intCast`.1 files changed, 1 insertions(+), 1 deletions(-)
src/arch/riscv64/CodeGen.zig+1-1| ... | ... | @@ -3592,7 +3592,7 @@ fn genCall( |
| 3592 | 3592 | |
| 3593 | 3593 | _ = try sym.getOrCreateZigGotEntry(sym_index, elf_file); |
| 3594 | 3594 | const got_addr = sym.zigGotAddress(elf_file); |
| 3595 | try self.genSetReg(Type.usize, .ra, .{ .memory = got_addr }); | |
| 3595 | try self.genSetReg(Type.usize, .ra, .{ .memory = @intCast(got_addr) }); | |
| 3596 | 3596 | |
| 3597 | 3597 | _ = try self.addInst(.{ |
| 3598 | 3598 | .tag = .jalr, |