authorgravatar for david@vortan.devDavid Rubin <david@vortan.dev> 2024-05-10 21:40:53-07:00
committergravatar for david@vortan.devDavid Rubin <david@vortan.dev> 2024-05-11 02:17:24-07:00
log1dfdc21c31a027a34213a2e1f27433d4e609d634
treef0f5477cad019e67ad8343372ea763239b04ad52
parentffb63a05a3327e64bcf8ec7fd05c6aab8d304480

riscv: intcast `got_addr`

the recent merge strings PR made `got_addr` `i64` and now requires an `@intCast`.

1 files changed, 1 insertions(+), 1 deletions(-)

src/arch/riscv64/CodeGen.zig+1-1
...@@ -3592,7 +3592,7 @@ fn genCall(...@@ -3592,7 +3592,7 @@ fn genCall(
35923592
3593 _ = try sym.getOrCreateZigGotEntry(sym_index, elf_file);3593 _ = try sym.getOrCreateZigGotEntry(sym_index, elf_file);
3594 const got_addr = sym.zigGotAddress(elf_file);3594 const got_addr = sym.zigGotAddress(elf_file);
3595 try self.genSetReg(Type.usize, .ra, .{ .memory = got_addr });3595 try self.genSetReg(Type.usize, .ra, .{ .memory = @intCast(got_addr) });
35963596
3597 _ = try self.addInst(.{3597 _ = try self.addInst(.{
3598 .tag = .jalr,3598 .tag = .jalr,