authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2025-03-11 16:11:09-04:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2025-03-12 12:25:05-07:00
log22b7d0228261e040d64b2706918ee7582d4d2b6d
treef8f54a2b8a28b3a1df4ecabb0dd72b2989a003ec
parent623d5cc7f6b7ef84e8a465b5818e7c1e6060e8b5

Merge pull request #23188 from jacobly0/fix-23143

x86_64: fix crashes with symbols

3 files changed, 212 insertions(+), 71 deletions(-)

src/arch/x86_64/CodeGen.zig+159-45
......@@ -97909,16 +97909,150 @@ fn airSelect(self: *CodeGen, inst: Air.Inst.Index) !void {
9790997909 switch (pred_mcv) {
9791097910 .register => |pred_reg| switch (pred_reg.class()) {
9791197911 .general_purpose => {},
97912 .sse => if (need_xmm0 and pred_reg.id() != comptime Register.xmm0.id()) {
97913 try self.register_manager.getKnownReg(.xmm0, null);
97914 try self.genSetReg(.xmm0, pred_ty, pred_mcv, .{});
97915 break :mask .xmm0;
97916 } else break :mask if (has_blend)
97917 pred_reg
97912 .sse => if (elem_ty.toIntern() == .bool_type)
97913 if (need_xmm0 and pred_reg.id() != comptime Register.xmm0.id()) {
97914 try self.register_manager.getKnownReg(.xmm0, null);
97915 try self.genSetReg(.xmm0, pred_ty, pred_mcv, .{});
97916 break :mask .xmm0;
97917 } else break :mask if (has_blend)
97918 pred_reg
97919 else
97920 try self.copyToTmpRegister(pred_ty, pred_mcv)
9791897921 else
97919 try self.copyToTmpRegister(pred_ty, pred_mcv),
97922 return self.fail("TODO implement airSelect for {}", .{ty.fmt(pt)}),
9792097923 else => unreachable,
9792197924 },
97925 .register_mask => |pred_reg_mask| {
97926 if (pred_reg_mask.info.scalar.bitSize(self.target) != 8 * elem_abi_size)
97927 return self.fail("TODO implement airSelect for {}", .{ty.fmt(pt)});
97928
97929 const mask_reg: Register = if (need_xmm0 and pred_reg_mask.reg.id() != comptime Register.xmm0.id()) mask_reg: {
97930 try self.register_manager.getKnownReg(.xmm0, null);
97931 try self.genSetReg(.xmm0, ty, .{ .register = pred_reg_mask.reg }, .{});
97932 break :mask_reg .xmm0;
97933 } else pred_reg_mask.reg;
97934 const mask_alias = registerAlias(mask_reg, abi_size);
97935 const mask_lock = self.register_manager.lockRegAssumeUnused(mask_reg);
97936 defer self.register_manager.unlockReg(mask_lock);
97937
97938 const lhs_mcv = try self.resolveInst(extra.lhs);
97939 const lhs_lock = switch (lhs_mcv) {
97940 .register => |lhs_reg| self.register_manager.lockRegAssumeUnused(lhs_reg),
97941 else => null,
97942 };
97943 defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
97944
97945 const rhs_mcv = try self.resolveInst(extra.rhs);
97946 const rhs_lock = switch (rhs_mcv) {
97947 .register => |rhs_reg| self.register_manager.lockReg(rhs_reg),
97948 else => null,
97949 };
97950 defer if (rhs_lock) |lock| self.register_manager.unlockReg(lock);
97951
97952 const order = has_blend != pred_reg_mask.info.inverted;
97953 const reuse_mcv, const other_mcv = if (order)
97954 .{ rhs_mcv, lhs_mcv }
97955 else
97956 .{ lhs_mcv, rhs_mcv };
97957 const dst_mcv: MCValue = if (reuse_mcv.isRegister() and self.reuseOperand(
97958 inst,
97959 if (order) extra.rhs else extra.lhs,
97960 @intFromBool(order),
97961 reuse_mcv,
97962 )) reuse_mcv else if (has_avx)
97963 .{ .register = try self.register_manager.allocReg(inst, abi.RegisterClass.sse) }
97964 else
97965 try self.copyToRegisterWithInstTracking(inst, ty, reuse_mcv);
97966 const dst_reg = dst_mcv.getReg().?;
97967 const dst_alias = registerAlias(dst_reg, abi_size);
97968 const dst_lock = self.register_manager.lockReg(dst_reg);
97969 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
97970
97971 const mir_tag = @as(?Mir.Inst.FixedTag, if ((pred_reg_mask.info.kind == .all and
97972 elem_ty.toIntern() != .f32_type and elem_ty.toIntern() != .f64_type) or pred_reg_mask.info.scalar == .byte)
97973 if (has_avx)
97974 .{ .vp_b, .blendv }
97975 else if (has_blend)
97976 .{ .p_b, .blendv }
97977 else if (pred_reg_mask.info.kind == .all)
97978 .{ .p_, undefined }
97979 else
97980 null
97981 else if ((pred_reg_mask.info.kind == .all and (elem_ty.toIntern() != .f64_type or !self.hasFeature(.sse2))) or
97982 pred_reg_mask.info.scalar == .dword)
97983 if (has_avx)
97984 .{ .v_ps, .blendv }
97985 else if (has_blend)
97986 .{ ._ps, .blendv }
97987 else if (pred_reg_mask.info.kind == .all)
97988 .{ ._ps, undefined }
97989 else
97990 null
97991 else if (pred_reg_mask.info.kind == .all or pred_reg_mask.info.scalar == .qword)
97992 if (has_avx)
97993 .{ .v_pd, .blendv }
97994 else if (has_blend)
97995 .{ ._pd, .blendv }
97996 else if (pred_reg_mask.info.kind == .all)
97997 .{ ._pd, undefined }
97998 else
97999 null
98000 else
98001 null) orelse return self.fail("TODO implement airSelect for {}", .{ty.fmt(pt)});
98002 if (has_avx) {
98003 const rhs_alias = if (reuse_mcv.isRegister())
98004 registerAlias(reuse_mcv.getReg().?, abi_size)
98005 else rhs: {
98006 try self.genSetReg(dst_reg, ty, reuse_mcv, .{});
98007 break :rhs dst_alias;
98008 };
98009 if (other_mcv.isBase()) try self.asmRegisterRegisterMemoryRegister(
98010 mir_tag,
98011 dst_alias,
98012 rhs_alias,
98013 try other_mcv.mem(self, .{ .size = self.memSize(ty) }),
98014 mask_alias,
98015 ) else try self.asmRegisterRegisterRegisterRegister(
98016 mir_tag,
98017 dst_alias,
98018 rhs_alias,
98019 registerAlias(if (other_mcv.isRegister())
98020 other_mcv.getReg().?
98021 else
98022 try self.copyToTmpRegister(ty, other_mcv), abi_size),
98023 mask_alias,
98024 );
98025 } else if (has_blend) if (other_mcv.isBase()) try self.asmRegisterMemoryRegister(
98026 mir_tag,
98027 dst_alias,
98028 try other_mcv.mem(self, .{ .size = self.memSize(ty) }),
98029 mask_alias,
98030 ) else try self.asmRegisterRegisterRegister(
98031 mir_tag,
98032 dst_alias,
98033 registerAlias(if (other_mcv.isRegister())
98034 other_mcv.getReg().?
98035 else
98036 try self.copyToTmpRegister(ty, other_mcv), abi_size),
98037 mask_alias,
98038 ) else {
98039 try self.asmRegisterRegister(.{ mir_tag[0], .@"and" }, dst_alias, mask_alias);
98040 if (other_mcv.isBase()) try self.asmRegisterMemory(
98041 .{ mir_tag[0], .andn },
98042 mask_alias,
98043 try other_mcv.mem(self, .{ .size = .fromSize(abi_size) }),
98044 ) else try self.asmRegisterRegister(
98045 .{ mir_tag[0], .andn },
98046 mask_alias,
98047 if (other_mcv.isRegister())
98048 other_mcv.getReg().?
98049 else
98050 try self.copyToTmpRegister(ty, other_mcv),
98051 );
98052 try self.asmRegisterRegister(.{ mir_tag[0], .@"or" }, dst_alias, mask_alias);
98053 }
98054 break :result dst_mcv;
98055 },
9792298056 else => {},
9792398057 }
9792498058 const mask_reg: Register = if (need_xmm0) mask_reg: {
......@@ -98121,7 +98255,7 @@ fn airSelect(self: *CodeGen, inst: Air.Inst.Index) !void {
9812198255 const dst_lock = self.register_manager.lockReg(dst_reg);
9812298256 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
9812398257
98124 const mir_tag = @as(?Mir.Inst.FixedTag, switch (ty.childType(zcu).zigTypeTag(zcu)) {
98258 const mir_tag = @as(?Mir.Inst.FixedTag, switch (elem_ty.zigTypeTag(zcu)) {
9812598259 else => null,
9812698260 .int => switch (abi_size) {
9812798261 0 => unreachable,
......@@ -98137,7 +98271,7 @@ fn airSelect(self: *CodeGen, inst: Air.Inst.Index) !void {
9813798271 null,
9813898272 else => null,
9813998273 },
98140 .float => switch (ty.childType(zcu).floatBits(self.target.*)) {
98274 .float => switch (elem_ty.floatBits(self.target.*)) {
9814198275 else => unreachable,
9814298276 16, 80, 128 => null,
9814398277 32 => switch (vec_len) {
......@@ -98191,30 +98325,20 @@ fn airSelect(self: *CodeGen, inst: Air.Inst.Index) !void {
9819198325 try self.copyToTmpRegister(ty, lhs_mcv), abi_size),
9819298326 mask_alias,
9819398327 ) else {
98194 const mir_fixes = @as(?Mir.Inst.Fixes, switch (elem_ty.zigTypeTag(zcu)) {
98195 else => null,
98196 .int => .p_,
98197 .float => switch (elem_ty.floatBits(self.target.*)) {
98198 32 => ._ps,
98199 64 => ._pd,
98200 16, 80, 128 => null,
98201 else => unreachable,
98202 },
98203 }) orelse return self.fail("TODO implement airSelect for {}", .{ty.fmt(pt)});
98204 try self.asmRegisterRegister(.{ mir_fixes, .@"and" }, dst_alias, mask_alias);
98328 try self.asmRegisterRegister(.{ mir_tag[0], .@"and" }, dst_alias, mask_alias);
9820598329 if (rhs_mcv.isBase()) try self.asmRegisterMemory(
98206 .{ mir_fixes, .andn },
98330 .{ mir_tag[0], .andn },
9820798331 mask_alias,
9820898332 try rhs_mcv.mem(self, .{ .size = .fromSize(abi_size) }),
9820998333 ) else try self.asmRegisterRegister(
98210 .{ mir_fixes, .andn },
98334 .{ mir_tag[0], .andn },
9821198335 mask_alias,
9821298336 if (rhs_mcv.isRegister())
9821398337 rhs_mcv.getReg().?
9821498338 else
9821598339 try self.copyToTmpRegister(ty, rhs_mcv),
9821698340 );
98217 try self.asmRegisterRegister(.{ mir_fixes, .@"or" }, dst_alias, mask_alias);
98341 try self.asmRegisterRegister(.{ mir_tag[0], .@"or" }, dst_alias, mask_alias);
9821898342 }
9821998343 break :result dst_mcv;
9822098344 };
......@@ -100753,11 +100877,11 @@ const Temp = struct {
100753100877 const new_temp_index = cg.next_temp_index;
100754100878 cg.temp_type[@intFromEnum(new_temp_index)] = .usize;
100755100879 cg.next_temp_index = @enumFromInt(@intFromEnum(new_temp_index) + 1);
100756 switch (temp.tracking(cg).short) {
100757 else => |mcv| std.debug.panic("{s}: {}\n", .{ @src().fn_name, mcv }),
100880 const mcv = temp.tracking(cg).short;
100881 switch (mcv) {
100882 else => std.debug.panic("{s}: {}\n", .{ @src().fn_name, mcv }),
100758100883 .register => |reg| {
100759 const new_reg =
100760 try cg.register_manager.allocReg(new_temp_index.toIndex(), abi.RegisterClass.gp);
100884 const new_reg = try cg.register_manager.allocReg(new_temp_index.toIndex(), abi.RegisterClass.gp);
100761100885 new_temp_index.tracking(cg).* = .init(.{ .register = new_reg });
100762100886 try cg.asmRegisterMemory(.{ ._, .lea }, new_reg.to64(), .{
100763100887 .base = .{ .reg = reg.to64() },
......@@ -100765,33 +100889,22 @@ const Temp = struct {
100765100889 });
100766100890 },
100767100891 .register_offset => |reg_off| {
100768 const new_reg =
100769 try cg.register_manager.allocReg(new_temp_index.toIndex(), abi.RegisterClass.gp);
100892 const new_reg = try cg.register_manager.allocReg(new_temp_index.toIndex(), abi.RegisterClass.gp);
100770100893 new_temp_index.tracking(cg).* = .init(.{ .register = new_reg });
100771100894 try cg.asmRegisterMemory(.{ ._, .lea }, new_reg.to64(), .{
100772100895 .base = .{ .reg = reg_off.reg.to64() },
100773100896 .mod = .{ .rm = .{ .disp = reg_off.off + off } },
100774100897 });
100775100898 },
100899 .load_symbol, .load_frame => {
100900 const new_reg = try cg.register_manager.allocReg(new_temp_index.toIndex(), abi.RegisterClass.gp);
100901 new_temp_index.tracking(cg).* = .init(.{ .register_offset = .{ .reg = new_reg, .off = off } });
100902 try cg.genSetReg(new_reg, .usize, mcv, .{});
100903 },
100776100904 .lea_symbol => |sym_off| new_temp_index.tracking(cg).* = .init(.{ .lea_symbol = .{
100777100905 .sym_index = sym_off.sym_index,
100778100906 .off = sym_off.off + off,
100779100907 } }),
100780 .load_frame => |frame_addr| {
100781 const new_reg =
100782 try cg.register_manager.allocReg(new_temp_index.toIndex(), abi.RegisterClass.gp);
100783 new_temp_index.tracking(cg).* = .init(.{ .register_offset = .{
100784 .reg = new_reg,
100785 .off = off,
100786 } });
100787 try cg.asmRegisterMemory(.{ ._, .mov }, new_reg.to64(), .{
100788 .base = .{ .frame = frame_addr.index },
100789 .mod = .{ .rm = .{
100790 .size = .qword,
100791 .disp = frame_addr.off,
100792 } },
100793 });
100794 },
100795100908 .lea_frame => |frame_addr| new_temp_index.tracking(cg).* = .init(.{ .lea_frame = .{
100796100909 .index = frame_addr.index,
100797100910 .off = frame_addr.off + off,
......@@ -101108,7 +101221,8 @@ const Temp = struct {
101108101221 => return temp.toRegClass(true, .general_purpose, cg),
101109101222 .lea_symbol => |sym_off| {
101110101223 const off = sym_off.off;
101111 if (off == 0) return false;
101224 // hack around linker relocation bugs
101225 if (false and off == 0) return false;
101112101226 try temp.toOffset(-off, cg);
101113101227 while (try temp.toRegClass(true, .general_purpose, cg)) {}
101114101228 try temp.toOffset(off, cg);
src/link/Dwarf.zig+33-26
......@@ -2008,9 +2008,9 @@ pub const WipNav = struct {
20082008 .decl_const_runtime_bits,
20092009 .decl_const_comptime_state,
20102010 .decl_const_runtime_bits_comptime_state,
2011 .decl_empty_func,
2011 .decl_nullary_func,
20122012 .decl_func,
2013 .decl_empty_func_generic,
2013 .decl_nullary_func_generic,
20142014 .decl_func_generic,
20152015 => false,
20162016 .generic_decl_var,
......@@ -2626,8 +2626,8 @@ pub fn finishWipNavFunc(
26262626 abbrev_code_buf,
26272627 try dwarf.refAbbrevCode(switch (abbrev_code) {
26282628 else => unreachable,
2629 .decl_func => .decl_empty_func,
2630 .decl_instance_func => .decl_instance_empty_func,
2629 .decl_func => .decl_nullary_func,
2630 .decl_instance_func => .decl_instance_nullary_func,
26312631 }),
26322632 );
26332633 }
......@@ -3012,29 +3012,34 @@ fn updateComptimeNavInner(dwarf: *Dwarf, pt: Zcu.PerThread, nav_index: InternPoo
30123012 if (nav_gop.found_existing) switch (try dwarf.debug_info.declAbbrevCode(wip_nav.unit, nav_gop.value_ptr.*)) {
30133013 .null => {},
30143014 else => unreachable,
3015 .decl_empty_func, .decl_func, .decl_instance_empty_func, .decl_instance_func => return,
3016 .decl_empty_func_generic,
3015 .decl_nullary_func, .decl_func, .decl_instance_nullary_func, .decl_instance_func => return,
3016 .decl_nullary_func_generic,
30173017 .decl_func_generic,
3018 .decl_instance_empty_func_generic,
3018 .decl_instance_nullary_func_generic,
30193019 .decl_instance_func_generic,
30203020 => dwarf.debug_info.section.getUnit(wip_nav.unit).getEntry(nav_gop.value_ptr.*).clear(),
30213021 } else nav_gop.value_ptr.* = try dwarf.addCommonEntry(wip_nav.unit);
30223022 wip_nav.entry = nav_gop.value_ptr.*;
30233023
30243024 const func_type = ip.indexToKey(func.ty).func_type;
3025 const is_nullary = !func_type.is_var_args and for (0..func_type.param_types.len) |param_index| {
3026 if (!func_type.paramIsComptime(std.math.cast(u5, param_index) orelse break false)) break false;
3027 } else true;
30253028 const diw = wip_nav.debug_info.writer(dwarf.gpa);
3026 try wip_nav.declCommon(if (func_type.param_types.len > 0 or func_type.is_var_args) .{
3027 .decl = .decl_func_generic,
3029 try wip_nav.declCommon(if (is_nullary) .{
3030 .decl = .decl_nullary_func_generic,
30283031 .generic_decl = .generic_decl_func,
3029 .decl_instance = .decl_instance_func_generic,
3032 .decl_instance = .decl_instance_nullary_func_generic,
30303033 } else .{
3031 .decl = .decl_empty_func_generic,
3034 .decl = .decl_func_generic,
30323035 .generic_decl = .generic_decl_func,
3033 .decl_instance = .decl_instance_empty_func_generic,
3036 .decl_instance = .decl_instance_func_generic,
30343037 }, &nav, inst_info.file, &decl);
30353038 try wip_nav.refType(.fromInterned(func_type.return_type));
3036 if (func_type.param_types.len > 0 or func_type.is_var_args) {
3039 if (!is_nullary) {
30373040 for (0..func_type.param_types.len) |param_index| {
3041 if (std.math.cast(u5, param_index)) |small_param_index|
3042 if (func_type.paramIsComptime(small_param_index)) continue;
30383043 try wip_nav.abbrevCode(.func_type_param);
30393044 try wip_nav.refType(.fromInterned(func_type.param_types.get(ip)[param_index]));
30403045 }
......@@ -3568,12 +3573,14 @@ fn updateLazyType(
35683573 };
35693574 try diw.writeByte(@intFromEnum(cc));
35703575 try wip_nav.refType(.fromInterned(func_type.return_type));
3571 for (0..func_type.param_types.len) |param_index| {
3572 try wip_nav.abbrevCode(.func_type_param);
3573 try wip_nav.refType(.fromInterned(func_type.param_types.get(ip)[param_index]));
3576 if (!is_nullary) {
3577 for (0..func_type.param_types.len) |param_index| {
3578 try wip_nav.abbrevCode(.func_type_param);
3579 try wip_nav.refType(.fromInterned(func_type.param_types.get(ip)[param_index]));
3580 }
3581 if (func_type.is_var_args) try wip_nav.abbrevCode(.is_var_args);
3582 try uleb128(diw, @intFromEnum(AbbrevCode.null));
35743583 }
3575 if (func_type.is_var_args) try wip_nav.abbrevCode(.is_var_args);
3576 if (!is_nullary) try uleb128(diw, @intFromEnum(AbbrevCode.null));
35773584 },
35783585 .error_set_type => |error_set_type| {
35793586 try wip_nav.abbrevCode(if (error_set_type.names.len == 0) .generated_empty_enum_type else .generated_enum_type);
......@@ -4787,9 +4794,9 @@ const AbbrevCode = enum {
47874794 decl_const_runtime_bits,
47884795 decl_const_comptime_state,
47894796 decl_const_runtime_bits_comptime_state,
4790 decl_empty_func,
4797 decl_nullary_func,
47914798 decl_func,
4792 decl_empty_func_generic,
4799 decl_nullary_func_generic,
47934800 decl_func_generic,
47944801 generic_decl_var,
47954802 generic_decl_const,
......@@ -4806,9 +4813,9 @@ const AbbrevCode = enum {
48064813 decl_instance_const_runtime_bits,
48074814 decl_instance_const_comptime_state,
48084815 decl_instance_const_runtime_bits_comptime_state,
4809 decl_instance_empty_func,
4816 decl_instance_nullary_func,
48104817 decl_instance_func,
4811 decl_instance_empty_func_generic,
4818 decl_instance_nullary_func_generic,
48124819 decl_instance_func_generic,
48134820 // the rest are unrestricted other than empty variants must not be longer
48144821 // than the non-empty variant, and so should appear first
......@@ -5019,7 +5026,7 @@ const AbbrevCode = enum {
50195026 .{ .ZIG_comptime_value, .ref_addr },
50205027 },
50215028 },
5022 .decl_empty_func = .{
5029 .decl_nullary_func = .{
50235030 .tag = .subprogram,
50245031 .attrs = decl_abbrev_common_attrs ++ .{
50255032 .{ .linkage_name, .strp },
......@@ -5044,7 +5051,7 @@ const AbbrevCode = enum {
50445051 .{ .noreturn, .flag },
50455052 },
50465053 },
5047 .decl_empty_func_generic = .{
5054 .decl_nullary_func_generic = .{
50485055 .tag = .subprogram,
50495056 .attrs = decl_abbrev_common_attrs ++ .{
50505057 .{ .type, .ref_addr },
......@@ -5167,7 +5174,7 @@ const AbbrevCode = enum {
51675174 .{ .ZIG_comptime_value, .ref_addr },
51685175 },
51695176 },
5170 .decl_instance_empty_func = .{
5177 .decl_instance_nullary_func = .{
51715178 .tag = .subprogram,
51725179 .attrs = decl_instance_abbrev_common_attrs ++ .{
51735180 .{ .linkage_name, .strp },
......@@ -5192,7 +5199,7 @@ const AbbrevCode = enum {
51925199 .{ .noreturn, .flag },
51935200 },
51945201 },
5195 .decl_instance_empty_func_generic = .{
5202 .decl_instance_nullary_func_generic = .{
51965203 .tag = .subprogram,
51975204 .attrs = decl_instance_abbrev_common_attrs ++ .{
51985205 .{ .type, .ref_addr },
test/behavior/select.zig+20
......@@ -66,3 +66,23 @@ fn selectArrays() !void {
6666 const xyz = @select(f32, x, y, z);
6767 try expect(mem.eql(f32, &@as([4]f32, xyz), &[4]f32{ 0.0, 312.1, -145.9, -3381.233 }));
6868}
69
70test "@select compare result" {
71 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
72 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest;
73 if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf and builtin.target.ofmt != .macho) return error.SkipZigTest;
74
75 const S = struct {
76 fn min(comptime V: type, lhs: V, rhs: V) V {
77 return @select(@typeInfo(V).vector.child, lhs < rhs, lhs, rhs);
78 }
79
80 fn doTheTest() !void {
81 try expect(@reduce(.And, min(@Vector(4, f32), .{ -1, 2, -3, 4 }, .{ 1, -2, 3, -4 }) == @Vector(4, f32){ -1, -2, -3, -4 }));
82 try expect(@reduce(.And, min(@Vector(2, f64), .{ -1, 2 }, .{ 1, -2 }) == @Vector(2, f64){ -1, -2 }));
83 }
84 };
85
86 try S.doTheTest();
87 try comptime S.doTheTest();
88}