authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-10-18 12:11:27+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-10-18 12:11:27+02:00
log23055273421675a3709218a941d8cbb9c9d6ed0a
treefc6ae05337fe4d6bac3409bd4b35b06b4b483076
parentadcfdce6be955d7d8e3237be5c34f84478cf4636
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.start: fix _start for mipsn32

This is more similar to O32 than N64.

1 files changed, 40 insertions(+), 21 deletions(-)

lib/std/start.zig+40-21
...@@ -343,27 +343,46 @@ fn _start() callconv(.naked) noreturn {...@@ -343,27 +343,46 @@ fn _start() callconv(.naked) noreturn {
343 \\ subu $sp, $sp, 16343 \\ subu $sp, $sp, 16
344 \\ jalr $t9344 \\ jalr $t9
345 ,345 ,
346 .mips64, .mips64el =>346 .mips64, .mips64el => switch (builtin.abi) {
347 \\ move $fp, $zero347 .gnuabin32, .muslabin32 =>
348 // This is needed because early MIPS versions don't support misaligned loads. Without348 \\ move $fp, $zero
349 // this directive, the hidden `nop` inserted to fill the delay slot after `bal` would349 \\ bal 1f
350 // cause the two doublewords to be aligned to 4 bytes instead of 8.350 \\ .gpword .
351 \\ .balign 8351 \\ .gpword %[posixCallMainAndExit]
352 \\ bal 1f352 \\1:
353 \\ .gpdword .353 // The `gp` register on MIPS serves a similar purpose to `r2` (ToC pointer) on PPC64.
354 \\ .gpdword %[posixCallMainAndExit]354 \\ lw $gp, 0($ra)
355 \\1:355 \\ subu $gp, $ra, $gp
356 // The `gp` register on MIPS serves a similar purpose to `r2` (ToC pointer) on PPC64.356 \\ lw $t9, 4($ra)
357 \\ ld $gp, 0($ra)357 \\ addu $t9, $t9, $gp
358 \\ dsubu $gp, $ra, $gp358 \\ move $ra, $zero
359 \\ ld $t9, 8($ra)359 \\ move $a0, $sp
360 \\ daddu $t9, $t9, $gp360 \\ and $sp, -8
361 \\ move $ra, $zero361 \\ subu $sp, $sp, 16
362 \\ move $a0, $sp362 \\ jalr $t9
363 \\ and $sp, -16363 ,
364 \\ dsubu $sp, $sp, 16364 else =>
365 \\ jalr $t9365 \\ move $fp, $zero
366 ,366 // This is needed because early MIPS versions don't support misaligned loads. Without
367 // this directive, the hidden `nop` inserted to fill the delay slot after `bal` would
368 // cause the two doublewords to be aligned to 4 bytes instead of 8.
369 \\ .balign 8
370 \\ bal 1f
371 \\ .gpdword .
372 \\ .gpdword %[posixCallMainAndExit]
373 \\1:
374 // The `gp` register on MIPS serves a similar purpose to `r2` (ToC pointer) on PPC64.
375 \\ ld $gp, 0($ra)
376 \\ dsubu $gp, $ra, $gp
377 \\ ld $t9, 8($ra)
378 \\ daddu $t9, $t9, $gp
379 \\ move $ra, $zero
380 \\ move $a0, $sp
381 \\ and $sp, -16
382 \\ dsubu $sp, $sp, 16
383 \\ jalr $t9
384 ,
385 },
367 .powerpc, .powerpcle =>386 .powerpc, .powerpcle =>
368 // Set up the initial stack frame, and clear the back chain pointer.387 // Set up the initial stack frame, and clear the back chain pointer.
369 // r1 = SP, r31 = FP388 // r1 = SP, r31 = FP