authorgravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-10-07 19:12:16-04:00
committergravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-10-07 19:47:46-04:00
log24c67992e00b0043ab9409d58ffcecb2f689ee6f
tree5c5733861b3e54ff1b5ea4b099d3524188549fb7
parentb19fd485b185743907c71cedc0cc3a87ffcce27b

x86_64: hack around silent `f80` miscompilations

The x87 kind sucks.

2 files changed, 83 insertions(+), 45 deletions(-)

src/arch/x86_64/CodeGen.zig+80-42
......@@ -5263,21 +5263,29 @@ fn airRound(self: *Self, inst: Air.Inst.Index, mode: RoundMode) !void {
52635263 const un_op = self.air.instructions.items(.data)[inst].un_op;
52645264 const ty = self.typeOf(un_op);
52655265
5266 const src_mcv = try self.resolveInst(un_op);
5267 const dst_mcv = if (src_mcv.isRegister() and self.reuseOperand(inst, un_op, 0, src_mcv))
5268 src_mcv
5269 else
5270 try self.copyToRegisterWithInstTracking(inst, ty, src_mcv);
5271 const dst_reg = dst_mcv.getReg().?;
5272 const dst_lock = self.register_manager.lockReg(dst_reg);
5273 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
5274 try self.genRound(ty, dst_reg, src_mcv, mode);
5275 return self.finishAir(inst, dst_mcv, .{ un_op, .none, .none });
5266 const result = result: {
5267 switch (try self.genRoundLibcall(ty, .{ .air_ref = un_op }, mode)) {
5268 .none => {},
5269 else => |dst_mcv| break :result dst_mcv,
5270 }
5271
5272 const src_mcv = try self.resolveInst(un_op);
5273 const dst_mcv = if (src_mcv.isRegister() and self.reuseOperand(inst, un_op, 0, src_mcv))
5274 src_mcv
5275 else
5276 try self.copyToRegisterWithInstTracking(inst, ty, src_mcv);
5277 const dst_reg = dst_mcv.getReg().?;
5278 const dst_lock = self.register_manager.lockReg(dst_reg);
5279 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
5280 try self.genRound(ty, dst_reg, src_mcv, mode);
5281 break :result dst_mcv;
5282 };
5283 return self.finishAir(inst, result, .{ un_op, .none, .none });
52765284}
52775285
5278fn genRound(self: *Self, ty: Type, dst_reg: Register, src_mcv: MCValue, mode: RoundMode) !void {
5286fn getRoundTag(self: *Self, ty: Type) ?Mir.Inst.FixedTag {
52795287 const mod = self.bin_file.options.module.?;
5280 const mir_tag = @as(?Mir.Inst.FixedTag, if (self.hasFeature(.sse4_1)) switch (ty.zigTypeTag(mod)) {
5288 return if (self.hasFeature(.sse4_1)) switch (ty.zigTypeTag(mod)) {
52815289 .Float => switch (ty.floatBits(self.target.*)) {
52825290 32 => if (self.hasFeature(.avx)) .{ .v_ss, .round } else .{ ._ss, .round },
52835291 64 => if (self.hasFeature(.avx)) .{ .v_sd, .round } else .{ ._sd, .round },
......@@ -5304,26 +5312,38 @@ fn genRound(self: *Self, ty: Type, dst_reg: Register, src_mcv: MCValue, mode: Ro
53045312 else => null,
53055313 },
53065314 else => unreachable,
5307 } else null) orelse {
5308 if (ty.zigTypeTag(mod) != .Float)
5309 return self.fail("TODO implement genRound for {}", .{ty.fmt(mod)});
5310
5311 var callee: ["__trunc?".len]u8 = undefined;
5312 const res = try self.genCall(.{ .lib = .{
5313 .return_type = ty.toIntern(),
5314 .param_types = &.{ty.toIntern()},
5315 .callee = std.fmt.bufPrint(&callee, "{s}{s}{s}", .{
5316 floatLibcAbiPrefix(ty),
5317 switch (mode.mode) {
5318 .down => "floor",
5319 .up => "ceil",
5320 .zero => "trunc",
5321 else => unreachable,
5322 },
5323 floatLibcAbiSuffix(ty),
5324 }) catch unreachable,
5325 } }, &.{ty}, &.{src_mcv});
5326 return self.genSetReg(dst_reg, ty, res);
5315 } else null;
5316}
5317
5318fn genRoundLibcall(self: *Self, ty: Type, src_mcv: MCValue, mode: RoundMode) !MCValue {
5319 const mod = self.bin_file.options.module.?;
5320 if (self.getRoundTag(ty)) |_| return .none;
5321
5322 if (ty.zigTypeTag(mod) != .Float)
5323 return self.fail("TODO implement genRound for {}", .{ty.fmt(mod)});
5324
5325 var callee: ["__trunc?".len]u8 = undefined;
5326 return try self.genCall(.{ .lib = .{
5327 .return_type = ty.toIntern(),
5328 .param_types = &.{ty.toIntern()},
5329 .callee = std.fmt.bufPrint(&callee, "{s}{s}{s}", .{
5330 floatLibcAbiPrefix(ty),
5331 switch (mode.mode) {
5332 .down => "floor",
5333 .up => "ceil",
5334 .zero => "trunc",
5335 else => unreachable,
5336 },
5337 floatLibcAbiSuffix(ty),
5338 }) catch unreachable,
5339 } }, &.{ty}, &.{src_mcv});
5340}
5341
5342fn genRound(self: *Self, ty: Type, dst_reg: Register, src_mcv: MCValue, mode: RoundMode) !void {
5343 const mod = self.bin_file.options.module.?;
5344 const mir_tag = self.getRoundTag(ty) orelse {
5345 const result = try self.genRoundLibcall(ty, src_mcv, mode);
5346 return self.genSetReg(dst_reg, ty, result);
53275347 };
53285348 const abi_size: u32 = @intCast(ty.abiSize(mod));
53295349 const dst_alias = registerAlias(dst_reg, abi_size);
......@@ -6760,11 +6780,17 @@ fn genBinOp(
67606780 else => unreachable,
67616781 }) {
67626782 var callee: ["__add?f3".len]u8 = undefined;
6763 return self.genCall(.{ .lib = .{
6783 const result = try self.genCall(.{ .lib = .{
67646784 .return_type = lhs_ty.toIntern(),
67656785 .param_types = &.{ lhs_ty.toIntern(), rhs_ty.toIntern() },
67666786 .callee = switch (air_tag) {
6767 .add, .sub, .mul, .div_float => std.fmt.bufPrint(&callee, "__{s}{c}f3", .{
6787 .add,
6788 .sub,
6789 .mul,
6790 .div_float,
6791 .div_trunc,
6792 .div_floor,
6793 => std.fmt.bufPrint(&callee, "__{s}{c}f3", .{
67686794 @tagName(air_tag)[0..3],
67696795 floatCompilerRtAbiName(lhs_ty.floatBits(self.target.*)),
67706796 }),
......@@ -6778,6 +6804,17 @@ fn genBinOp(
67786804 }),
67796805 } catch unreachable,
67806806 } }, &.{ lhs_ty, rhs_ty }, &.{ .{ .air_ref = lhs_air }, .{ .air_ref = rhs_air } });
6807 return switch (air_tag) {
6808 .div_trunc, .div_floor => try self.genRoundLibcall(lhs_ty, result, .{
6809 .mode = switch (air_tag) {
6810 .div_trunc => .zero,
6811 .div_floor => .down,
6812 else => unreachable,
6813 },
6814 .precision = .inexact,
6815 }),
6816 else => result,
6817 };
67816818 }
67826819
67836820 if ((lhs_ty.scalarType(mod).isRuntimeFloat() and
......@@ -7666,16 +7703,14 @@ fn genBinOp(
76667703
76677704 switch (air_tag) {
76687705 .add, .add_wrap, .sub, .sub_wrap, .mul, .mul_wrap, .div_float, .div_exact => {},
7669 .div_trunc, .div_floor => try self.genRound(
7670 lhs_ty,
7671 dst_reg,
7672 .{ .register = dst_reg },
7673 .{ .mode = switch (air_tag) {
7706 .div_trunc, .div_floor => try self.genRound(lhs_ty, dst_reg, .{ .register = dst_reg }, .{
7707 .mode = switch (air_tag) {
76747708 .div_trunc => .zero,
76757709 .div_floor => .down,
76767710 else => unreachable,
7677 }, .precision = .inexact },
7678 ),
7711 },
7712 .precision = .inexact,
7713 }),
76797714 .bit_and, .bit_or, .xor => {},
76807715 .max, .min => if (maybe_mask_reg) |mask_reg| if (self.hasFeature(.avx)) {
76817716 const rhs_copy_reg = registerAlias(src_mcv.getReg().?, abi_size);
......@@ -8673,7 +8708,10 @@ fn genCall(self: *Self, info: union(enum) {
86738708 try self.spillRegisters(&regs);
86748709 try arg_locks.appendSlice(&self.register_manager.lockRegs(2, regs));
86758710 },
8676 .load_frame => try self.genCopy(arg_ty, dst_arg, src_arg),
8711 .load_frame => {
8712 try self.genCopy(arg_ty, dst_arg, src_arg);
8713 try self.freeValue(src_arg);
8714 },
86778715 else => unreachable,
86788716 };
86798717
test/behavior/floatop.zig+3-3
......@@ -1029,7 +1029,7 @@ test "@floor f80/f128/c_longdouble" {
10291029 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
10301030 if (builtin.zig_backend == .stage2_c and builtin.cpu.arch.isArmOrThumb()) return error.SkipZigTest;
10311031 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
1032 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1032 if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
10331033
10341034 if (builtin.zig_backend == .stage2_llvm and builtin.os.tag == .windows) {
10351035 // https://github.com/ziglang/zig/issues/12602
......@@ -1111,7 +1111,7 @@ test "@ceil f80/f128/c_longdouble" {
11111111 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
11121112 if (builtin.zig_backend == .stage2_c and builtin.cpu.arch.isArmOrThumb()) return error.SkipZigTest;
11131113 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
1114 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1114 if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
11151115
11161116 if (builtin.zig_backend == .stage2_llvm and builtin.os.tag == .windows) {
11171117 // https://github.com/ziglang/zig/issues/12602
......@@ -1203,7 +1203,7 @@ test "@trunc f80/f128/c_longdouble" {
12031203 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
12041204 if (builtin.zig_backend == .stage2_c and builtin.cpu.arch.isArmOrThumb()) return error.SkipZigTest;
12051205 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
1206 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1206 if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
12071207
12081208 if (builtin.zig_backend == .stage2_llvm and builtin.os.tag == .windows) {
12091209 // https://github.com/ziglang/zig/issues/12602