Commit 26ce82d98efce4847307c0b73d1765be7a104256 | zig

1 files changed, 21 insertions(+), 0 deletions(-)

src/arch/riscv64/CodeGen.zig+21

...	...	@@ -3535,6 +3535,27 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, src_mcv: MCValue) InnerError!
3535	3535	}),
3536	3536	},
3537	3537	});
	3538
	3539	const tag: Mir.Inst.Tag = switch (abi_size) {
	3540	1 => .lb,
	3541	2 => .lh,
	3542	4 => .lw,
	3543	8 => .ld,
	3544	else => return self.fail("TODO: genSetReg for size {d}", .{abi_size}),
	3545	};
	3546
	3547	_ = try self.addInst(.{
	3548	.tag = tag,
	3549	.data = .{
	3550	.i_type = .{
	3551	.rd = reg,
	3552	.rs1 = reg,
	3553	.imm12 = 0,
	3554	},
	3555	},
	3556	});
	3557
	3558	unreachable;
3538	3559	},
3539	3560	.air_ref => \|ref\| try self.genSetReg(ty, reg, try self.resolveInst(ref)),
3540	3561	.indirect => \|reg_off\| {