Commit 271505cfc8ed380d974e6f981e261d53884b627a | zig

author	Jacob Young <jacobly@ziglang.org> 2024-02-11 21:37:33+01:00
committer	Jacob Young <jacobly@ziglang.org> 2024-02-12 05:25:07+01:00
log	271505cfc8ed380d974e6f981e261d53884b627a
tree	4fb8be5fe3c55777462bc6964c791d2f18003d84
parent	bcbd49b2a6e6a4dd84a5516bf6d1a6fd1e2af3ae

x86_64: fix compiler_rt tests

2 files changed, 11 insertions(+), 7 deletions(-)

lib
- compiler_rt
  - udivmodei4.zig
src
- arch
  - x86_64
    CodeGen.zig

lib/compiler_rt/udivmodei4.zig+6-6

...	@@ -114,17 +114,17 @@ fn divmod(q: ?[]u32, r: ?[]u32, u: []const u32, v: []const u32) !void {	...	@@ -114,17 +114,17 @@ fn divmod(q: ?[]u32, r: ?[]u32, u: []const u32, v: []const u32) !void {
114		114
115	pub fn __udivei4(r_q: []u32, u_p: []const u32, v_p: [*]const u32, bits: usize) callconv(.C) void {	115	pub fn __udivei4(r_q: []u32, u_p: []const u32, v_p: [*]const u32, bits: usize) callconv(.C) void {
116	@setRuntimeSafety(builtin.is_test);	116	@setRuntimeSafety(builtin.is_test);
117	const u = u_p[0 .. bits / 32];	117	const u = u_p[0 .. std.math.divCeil(usize, bits, 32) catch unreachable];
118	const v = v_p[0 .. bits / 32];	118	const v = v_p[0 .. std.math.divCeil(usize, bits, 32) catch unreachable];
119	const q = r_q[0 .. bits / 32];	119	const q = r_q[0 .. std.math.divCeil(usize, bits, 32) catch unreachable];
120	@call(.always_inline, divmod, .{ q, null, u, v }) catch unreachable;	120	@call(.always_inline, divmod, .{ q, null, u, v }) catch unreachable;
121	}	121	}
122		122
123	pub fn __umodei4(r_p: []u32, u_p: []const u32, v_p: [*]const u32, bits: usize) callconv(.C) void {	123	pub fn __umodei4(r_p: []u32, u_p: []const u32, v_p: [*]const u32, bits: usize) callconv(.C) void {
124	@setRuntimeSafety(builtin.is_test);	124	@setRuntimeSafety(builtin.is_test);
125	const u = u_p[0 .. bits / 32];	125	const u = u_p[0 .. std.math.divCeil(usize, bits, 32) catch unreachable];
126	const v = v_p[0 .. bits / 32];	126	const v = v_p[0 .. std.math.divCeil(usize, bits, 32) catch unreachable];
127	const r = r_p[0 .. bits / 32];	127	const r = r_p[0 .. std.math.divCeil(usize, bits, 32) catch unreachable];
128	@call(.always_inline, divmod, .{ null, r, u, v }) catch unreachable;	128	@call(.always_inline, divmod, .{ null, r, u, v }) catch unreachable;
129	}	129	}
130		130

src/arch/x86_64/CodeGen.zig+5-1

 @@ -3030,7 +3030,11 @@ fn airTrunc(self: *Self, inst: Air.Inst.Index) !void {
             try self.genCopy(dst_ty, dst_mcv, src_mcv, .{});
             break :dst dst_mcv;
-        } else try self.allocRegOrMem(inst, true);
+        } else dst: {
+            const dst_mcv = try self.allocRegOrMem(inst, true);
+            try self.genCopy(dst_ty, dst_mcv, src_mcv, .{});
+            break :dst dst_mcv;
+        };
         if (dst_ty.zigTypeTag(mod) == .Vector) {
             assert(src_ty.zigTypeTag(mod) == .Vector and dst_ty.vectorLen(mod) == src_ty.vectorLen(mod));